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reference:zmod:zmoddac:zmoddac1411libraryuserguide [2020/01/13 08:05]
Cristian Fatu [3.1. ZMODDAC1411 IP Behaviour]
reference:zmod:zmoddac:zmoddac1411libraryuserguide [2020/01/20 13:03] (current)
Cristian Fatu [3.1. ZMODDAC1411 IP Behaviour]
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 ====== 1. Overview ====== ====== 1. Overview ======
-Digilent provides the ZmodDAC1411 Libraryused to access [[https://​store.digilentinc.com/​zmod-adc-1410-syzygy-compatible-dual-channel-14-bit-analog-to-digital-converter-module/​|ZmodDAC1411]] functionality.\\ ​+Digilent provides the ZmodDAC1411 Library used to access [[https://​store.digilentinc.com/​zmod-dac-1411-syzygy-compatible-dual-channel-14-bit-digital-to-analog-converter-module/​|ZmodDAC1411]] functionality.\\ ​
 It is part of a pack of libraries to handle the Zmod modules functionality. They covers both linux and baremetal (standalone) platforms.\\ ​ It is part of a pack of libraries to handle the Zmod modules functionality. They covers both linux and baremetal (standalone) platforms.\\ ​
-[[reference:​zmod:​zmodbaselibraryuserguide|Zmod Base Library]] implements the functionality that is common to all the Zmods.\\ ​+[[reference:​zmod:​zmodbaselibraryuserguide|Zmod Base Library]] implements the functionality that is common to all Zmods.\\ ​
 For each Zmod, separate libraries are implemented,​ based on Zmod Base Library. This document describes the ZmodDAC1411 Library.\\ ​ For each Zmod, separate libraries are implemented,​ based on Zmod Base Library. This document describes the ZmodDAC1411 Library.\\ ​
-The current usage instructions / demos are provided for the ZmodDAC1411 attached to Eclipse board, still ZmodDAC1411 can be attached to any Zynq board providing the SZG connector.\\  +The current usage instructions / demos are provided for the ZmodDAC1411 attached to Eclipse board, still ZmodDAC1411 can be attached to any Zynq board providing the SYZYGY ​connector.\\  
-The following ​picture ​shows the overall structure of Zmod Libraries.+The following ​image shows the overall structure of Zmod Libraries.
 {{ :​reference:​programmable-logic:​eclypse-z7:​zmod_dev-board_structure_-_dac.png}} {{ :​reference:​programmable-logic:​eclypse-z7:​zmod_dev-board_structure_-_dac.png}}
  
-The ZmodDAC1411 and Zmod Base Library run in the Zynq PS (processing system).\\  +The ZmodDAC1411 and Zmod Base Library run on the Zynq PS (processing system).\\  
-In the Zynq PL (FPGAthere is an IP core specific to ZmodDAC1411. This IP core can be accessed from the Zynq PS through its registers. The IP core is able to communicate with the memory ​over the AXI DMA data bus. Each Zmod has associated one particular instance of AXI DMA IP core.\\  +A Zmod DAC 1411 specific IP core needs to be instantiated in the programmable logic (PL).  
-Basically, the ZMODDAC1411 IP (figured ZMOD_DAC in the above image) generates analog values (using an internal buffer that was pre-filled with digital values) using its on-board digital to analog converter device. The ZMODDAC1411 Library initiates an AXI DMA transmit ​ transfer, sending the data from an memory buffer allocated by ZMODDAC1411 Library to the ZmodDAC1411 IP. This buffer contains data for both channels.\\+ 
 +This IP core can be accessed from the Zynq PS through its registers. The IP core is able to communicate with the memory ​through a DMA engine Each Zmod has associated one particular instance of AXI DMA IP core.\\ ​
 Basically: Basically:
-  * The ZMODDAC1411 IP (figured ​ZMOD_DAC in the above image) features an internal buffer. +  * The ZMODDAC1411 IP (labeled ​ZMOD_DAC in the above image) features an internal buffer. 
-  * The ZMODDAC1411 Library initiates an AXI DMA transmit ​transfer, sending the data from a memory buffer allocated by ZMODDAC1411 Library to the ZmodDAC1411 IP internal buffer +  * The AXI DMA transmit ​(Memory Mapped to Stream) is initiated in the ZMODDAC1411 Library, sending the data from a memory buffer allocated by ZMODDAC1411 Library to the ZmodDAC1411 IP internal buffer. 
-  * The ZMODDAC1411 IP generates analog values corresponding to the values from the internal buffer, using its on-board digital ​to analog ​converter device. This is done in repetitive manner.+  * The ZMODDAC1411 IP outputs ​the values from internal buffer to the DAC which generates the analog ​values. This is done in repetitive manner.
 Read more on [[#​zmoddac1411_ip_behaviour|ZMODDAC1411 IP behaviour]]. Read more on [[#​zmoddac1411_ip_behaviour|ZMODDAC1411 IP behaviour]].
  
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 ====== 3. Background Knowledge ====== ====== 3. Background Knowledge ======
 ===== 3.1. ZMODDAC1411 IP Behaviour ===== ===== 3.1. ZMODDAC1411 IP Behaviour =====
-Basically the ZMODDAC1411 ​IP (figured ZMOD_DAC in the above image) controls ​the [[https://​store.digilentinc.com/​zmod-adc-1410-syzygy-compatible-dual-channel-14-bit-analog-to-digital-converter-module/​|ZmodDAC1411]] device. It exposes ​to PS a set of command ​and status registers.\\ ​  +The ZmodDAC1411 ​IP directly interfaces with the [[https://​store.digilentinc.com/​zmod-adc-1410-syzygy-compatible-dual-channel-14-bit-analog-to-digital-converter-module/​|ZmodDAC1411]] device ​performing an initial configuration and providing an easy to use interface that the upper level IPs or the PS can use to transfer data or configuration information. This interface is composed ​of control ​and status registers ​that the library functions can access for configuration purposes and a stream channel that can be connected to a DMA engine for high bandwidth data transfers.\\  
-The ZMODDAC1411 Library uses these registers to control the IP and read its status.\\ +The intended use case of this IP is to load a predefined number of samples in its internal buffercalibrate them and pass them to the ZmodDAC1411 for digital ​to analog conversionThis sequence is defined as the “generate process”. The output buffer is addressed by a counter ​that resets to 0 when it reaches ​the buffer ​length programmed by software. The maximum depth of the buffer is 2^14-1 samples for both channels. The output address counter ​resets after the last buffer sample, implementing a repeated generate process of values from the buffer.\\  ​
-Using these commands, the Digital ​to Analog Converter (DAC) generate process can be configured, started or stoppedDAC generate process ​means that the ZMODDAC1411 IP takes values from an internal ​buffer, calibrates them and generates analog values accordingly on the Zmod outputs using the on-board  Digital to Analog converter device. The index used to parse values from buffer ​resets after the last buffer sample, implementing a repeated generate process of values from the buffer.\\  ​+
 The internal buffer has a maximum length of 0x3FFE (2^14 - 1) samples and is 32 bits wide, accommodating both ZMODDAC1411 channels. The internal buffer length must be set using IP registers.\\ ​ The internal buffer has a maximum length of 0x3FFE (2^14 - 1) samples and is 32 bits wide, accommodating both ZMODDAC1411 channels. The internal buffer length must be set using IP registers.\\ ​
-When generate process ​ is stopped, the index used to parse values from buffer ​maintains its value, meaning that next time when the generate process is started ​the samples sequence will follow the last generated ones. The index used to parse values from buffer ​can be reset, meaning that next time when the generate process is started ​the samples sequence will start with the first sample from the buffer.\\  +When the generate process is stopped, the output address counter ​maintains its value, meaning that when the generate process is resumed ​the samples sequence will follow the last generated ones. The output address counter ​can be reset, meaning that next time when the generate process is resumed ​the samples sequence will start with the first sample from the buffer.\\  
-Before starting the DAC generate process, the ZMODDAC1411 Library ​sends over AXIDMA the data to populate the internal buffer. For this, the ZMODDAC1411 Library initiates an AXIDMA-MM2S (AXIDMA transmit) transfer, transferring data from a memory buffer allocated by ZMODDAC1411 Library.\\  +Before starting the DAC generate process, the ZMODDAC1411 Library ​transfer functions ​populate the internal buffer. For this, the ZMODDAC1411 Library initiates an AXIDMA-MM2S (AXIDMA transmit) transfer, transferring data from a memory buffer allocated by ZMODDAC1411 Library ​in the system memory.\\  
-The ZMODDAC1411 ​IP configures the Digital to Analog converter device using two gains: HIGH and LOW. In the HIGH gain the output ​analog values are in the +/- 5 V range, while in LOW gain the output ​analog values are in the +/- 1 V range.\\  +The Zmod DAC 1411 IP provides ​two gain options: HIGH and LOW. For the HIGH gain option, ​the DAC’s ​output ​range extend from -5 to +5 V, while for the LOW gain option ​the DAC’s ​output ​range extends from -1.25V to +1.25V.\\  
-The ZMODDAC1411 IP applies ​calibration ​coefficients over the digital values before sending them to Digital to Analog converter, in order to provide exact valuesFor this, the IP provides calibration registers where the calibration coefficients are set. Normally these coefficients are computed (by the library) starting from the calibration values ​stored ​during manufacturing process ​in the Zmod persistent ​memory (flash).\\  +The ZMODDAC1411 IP implements a calibration ​block that eliminates ​the offset and gain errors introduced by hardwareThe raw calibration coefficients are stored in the ZmodDAC1411’s nonvolatile ​memory (flash). ​The Zmod DAC1411 library initialization functions ​ read the raw values of the gain and offset calibration coefficients ​from the Zmod’s nonvolatile memoryprocesses them, and configure the calibration registers. The calibration registers further control the calibration block in the IP’s data path. 
-Normally each sample ​from buffer produce one analog value at the Zmod outputsimplementing an 100 MSamples per second output rate. The ZMODDAC1411 ​IP is able to to implement lower output sample rate, by repeating each sample ​from buffer multiple times, as specified using the Output Sample Frequency Divider IP setting.\\ ​+By default, the IP’s buffer ​output ​address counter runs at 100MHz corresponding to a sample rate of 100MSPS on both channels. The default ​sample ​rate can be divided by programming ​the Output Sample Frequency Divider IP setting.\\ ​
 Read more on [[#​terminology|Terminology]] chapter for more details. Read more on [[#​terminology|Terminology]] chapter for more details.
 ===== 3.2. Terminology ===== ===== 3.2. Terminology =====