Programmable Logic

Image
Name
Logic Cells
Block RAM
DSP Slices
Anvyl

6,822 slices

2.1 Mbits

58

Arty

33,280 in 5200 slices

1,800 Kbits

90

Arty Z7

630 KB (270 KB*)

220 (80*)

Atlys

6,822 slices

2.1Mbits

58

Basys 2

72Kbits

Basys 3

33,280 in 5200 slices

1,800 Kbits

90

Cmod

Xilinx CoolRunner-II CPLD
(64 Macrocells)

Cmod A7

112.5KB (15T)
225KB (35T)

Cmod S6

3,840 (6 LUTs)

216Kb

8

CoolRunner-II
Genesys

7,200 slices (4 LUTs and 8 flip-flops)

1.7Mbits

Genesys 2

50,950 logic slices
(4 6-input LUTs & 8 flip-flops each)

16 Mbits

840

NetFPGA-1G-CML

50,950 slices,
(4 6-input LUTs & 8 flip-flops each)

16Mbit

840

NetFPGA-SUME
Nexys 2
Nexys 3

2,278 slices (4 6-input LUTs
& 8 flip-flops each)

576Kbits

32

Nexys 4

15,850 (4 6-input LUTs &
8 flip-flops each)

4,860 Kbits

240

Nexys 4 DDR

4,860 Kbits

240

Nexys Video

33,650 (4 6-input LUTs &
8 flip-flops each)

13Mbits

740

PYNQ-Z1

630 KB

220

Spartan-3E

over 10,000

Virtex-5 OpenSPARC
Virtex-II Pro

30,816

ZedBoard
Getting Started with Zynq
Zybo

4,400 logic slices
(4 6-input LUTs and 8 flip-flops)

240 KB

80