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reference:zmod:zmodadc:zmodadc1410libraryuserguide [2020/01/15 15:26]
Cristian Fatu [4.2. ADC Acquisition Related Functions of ZMODADC1410 Class]
reference:zmod:zmodadc:zmodadc1410libraryuserguide [2020/01/20 14:11] (current)
Cristian Fatu [3.1. ZMODADC1410 IP Behaviour]
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 ====== 1. Overview ====== ====== 1. Overview ======
-Digilent provides the ZmodADC1410 Libraryused to access [[https://​store.digilentinc.com/​zmod-adc-1410-syzygy-compatible-dual-channel-14-bit-analog-to-digital-converter-module/​|ZmodADC1410]] functionality.\\ ​+Digilent provides the ZmodADC1410 Library used to access [[https://​store.digilentinc.com/​zmod-adc-1410-syzygy-compatible-dual-channel-14-bit-analog-to-digital-converter-module/​|ZmodADC1410]] functionality.\\ ​
 It is part of a pack of libraries to handle the Zmod modules functionality. They covers both linux and baremetal (standalone) platforms.\\ ​ It is part of a pack of libraries to handle the Zmod modules functionality. They covers both linux and baremetal (standalone) platforms.\\ ​
-The [[reference:​zmod:​zmodbaselibraryuserguide|Zmod Base Library]] implements the functionality that is common to all the Zmods.\\ ​+The [[reference:​zmod:​zmodbaselibraryuserguide|Zmod Base Library]] implements the functionality that is common to all Zmods.\\ ​
 For each Zmod, separate libraries are implemented,​ based on Zmod Base Library. This document describes the ZmodADC1410 Library.\\ ​ For each Zmod, separate libraries are implemented,​ based on Zmod Base Library. This document describes the ZmodADC1410 Library.\\ ​
-The current usage instructions / demos are provided for the ZmodADC1410 attached to Eclipse board, still ZmodADC1410 can be attached to any Zynq board providing the SZG connector.\\  +The current usage instructions / demos are provided for the ZmodADC1410 attached to Eclipse board, still ZmodADC1410 can be attached to any Zynq board providing the SYZYGY ​connector.\\  
-The following ​picture ​shows the overall structure of Zmod Libraries.+The following ​image shows the overall structure of Zmod Libraries.
 {{ :​reference:​programmable-logic:​eclypse-z7:​zmod_dev-board_structure_-_adc.png}} {{ :​reference:​programmable-logic:​eclypse-z7:​zmod_dev-board_structure_-_adc.png}}
  
-The ZmodADC1410 and Zmod Base Library run in the Zynq PS (processing system).\\  +The ZmodADC1410 and Zmod Base Library run on the Zynq PS (processing system).\\  
-In the Zynq PL (FPGA) there is an IP core specific to ZmodADC1410. This IP core can be accessed from the Zynq PS through its registers. The IP core is able to communicate with the memory ​over the AXI DMA data bus. Each Zmod has associated ​one particular ​instance of AXI DMA IP core.\\ ​+In the Zynq PL (FPGA) there is an IP core specific to ZmodADC1410. This IP core can be accessed from the Zynq PS through its registers. The IP core is able to communicate with the memory ​through a DMA engine. Each Zmod has one particular AXI DMA IP core associated.\\ 
 Basically: Basically:
-  * The ZMODADC1410 IP (figured ​ZMOD_ADC in the above image) features an internal buffer. +  * The ZMODADC1410 IP (labeled ​ZMOD_ADC in the above image) features an internal buffer. 
-  * The ZMODADC1410 IP acquires data (fills its internal buffer) ​using its on-board analog to digital converter device. ​+  * The ZMODADC1410 IP acquires data (fills its internal buffer) ​from its on-board analog to digital converter device. ​
   * Eventually, the ZMODADC1410 IP waits for a trigger condition before starting the acquisition. ​   * Eventually, the ZMODADC1410 IP waits for a trigger condition before starting the acquisition. ​
   * The ZMODADC1410 IP reports when its internal buffer is full.    * The ZMODADC1410 IP reports when its internal buffer is full. 
-  * The ZMODADC1410 Library initiates an AXI DMA receive transfer, transferring data from the IP internal buffer into a memory buffer allocated by ZMODADC1410 Library. This buffer contains data for both channels.+  * The ZMODADC1410 Library initiates an AXI DMA receive transfer, transferring data from the IP'​s ​internal buffer into a memory buffer allocated by ZMODADC1410 Library. This buffer contains data for both channels.
 Read more on [[#​zmodadc1410_ip_behaviour|ZMODADC1410 IP behaviour]]. Read more on [[#​zmodadc1410_ip_behaviour|ZMODADC1410 IP behaviour]].
  
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 ====== 3. Background Knowledge ====== ====== 3. Background Knowledge ======
 ===== 3.1. ZMODADC1410 IP Behaviour ===== ===== 3.1. ZMODADC1410 IP Behaviour =====
-Basically, the ZMODADC1410 IP (figured ​ZMOD_ADC in the above image) ​controls ​the [[https://​store.digilentinc.com/​zmod-adc-1410-syzygy-compatible-dual-channel-14-bit-analog-to-digital-converter-module/​|ZmodADC1410]] device. It exposes to PS a set of command and status registers. The ZMODADC1410 Library uses these registers to control the IP and read its status.\\  +Basically, the ZMODADC1410 IP (labeled ​ZMOD_ADC in the above image) ​directly interfaces with the [[https://​store.digilentinc.com/​zmod-adc-1410-syzygy-compatible-dual-channel-14-bit-analog-to-digital-converter-module/​|ZmodADC1410]] ​device performing an initial configuration and providing an easy to use interface that the upper level IPs or software can use to transfer data or configuration information the device. It exposes to the PS a set of command and status registers ​that the Zmod ADC 1410 library functions use to control the IP. The ZMODADC1410 Library uses these registers to control the IP and read its status.\\  
-Using these registers, the ADC acquisition can be configured, started or stopped. ADC acquisition ​means that the ZMODADC1410 ​IP fills an internal buffer ​with digital values provided by its on-board analog ​to digital converter ​device ​and then calibrated. The internal buffer has a maximum length of 2^14 - 1 samples and is 32 bits wide, accommodating both ZmodADC1410 channels. The internal buffer length must be set using IP registers.\\  +Using these registers, the ADC acquisition can be configured, started or stopped. ​The ADC acquisition ​is composed of the following steps: 
-Eventually, ​the ZMODADC1410 IP waits for a trigger condition before starting the ADC acquisition. This means that the values are compared ​to a trigger condition and acquisition only starts when the trigger condition is metThe trigger module allows setting the trigger mode, trigger edge, trigger level and window position.\\ ​  +  * **ADC output data is captured and decoded**. The Zmod ADC 1410’s ADC multiplexes its 2 channels on one 14bit wide double data rate (DDR) parallel interface. The Zmod ADC 1410 IP demultiplexes the input data channel and resynchronizes the received data with its internal clock. The ZMODADC1410 IP supports two gain options: HIGH and LOW. For the HIGH gain option, the ADC’s input range extends from -25 to +25 V, while for the LOW gain option the ADC’s input range extends from -1V to +1V. The raw data exported by the ZMOD ADC1410 must be analyzed considering the gain option used for the acquisition. 
-The ZMODADC1410 IP reports when its internal buffer is full. While the internal buffer is full, no acquisition is performed. ​ +  * **Sample data is calibrated by applying calibration coefficients**. The ZMODADC1410 IP applies calibration coefficients over the digital ​values received from Analog to Digital ​converter, in order to compensate the offset ​and gain errors introduced by the ADC associated circuitry. For this, the IP provides calibration registers where the calibration coefficients are set. The Zmod ADC1410 Library initialization functions available in the library reads the raw values for the gain and offset calibration coefficients from the Zmod’s nonvolatile memory, processes them, and configures the calibration registers. 
-The ZMODADC1410 Library initiates an AXIDMA-S2MM (AXIDMA receive) transfer, transferring data from the ZMODADC1410 IP internal buffer into a memory buffer allocated by ZMODADC1410 Library. The transferred length must be set using IP registers and AXI DMA registers.\\  +  * **The internal buffer is filled upon detecting a valid trigger condition**. The trigger module allows setting the trigger mode, trigger edge, trigger level and window position. The internal buffer has a maximum length of 2^14 - 1 samples and is 32 bits wide, accommodating both ZmodADC1410 channels. The internal buffer length must be set using the IP registers. 
-The ZMODADC1410 IP can be configured to raise a Buffer Full interrupt, still this interrupt can only be handled by baremetal hardware platform.\\  +  * **Buffer data is transferred from the ZMODADC1410 IP internal buffer ​to system memory through ​DMA engine**. The ZMODADC1410 IP reports when its internal buffer is full. While the internal buffer is full, no acquisition is performed. The ZMODADC1410 Library initiates an AXIDMA-S2MM (AXIDMA receive) transfer, transferring data from the ZMODADC1410 IP internal buffer into a memory buffer allocated by ZMODADC1410 Library. The transferred length must be set using the Zmod ADC 1410 IP registers and the AXI DMA IP registers. The ZMODADC1410 IP can be configured to raise a Buffer Full interrupt, still this interrupt can only be handled by baremetal hardware platform.
-The ZMODADC1410 IP configures the Analog to Digital acquisition using two gains: HIGH and LOW. In the HIGH gain the input analog values are in the +/- 1 V range, while in LOW gain the input analog values are in the +/- 25 V range.\\  +
-The ZMODADC1410 IP applies calibration coefficients over the digital values got from Analog to Digital acquisition,​ in order to provide exact values. For this, the IP provides calibration registers where the calibration coefficients are set. Normally these coefficients are computed (by the library) starting from the calibration values stored during manufacturing process in the Zmod persistent memory (flash).\\ ​+
 Read more on [[#​terminology|Terminology]] chapter for more details. Read more on [[#​terminology|Terminology]] chapter for more details.
 ===== 3.2. Terminology ===== ===== 3.2. Terminology =====