Atlys

Store Reference Manual Technical Support
Atlys
Spartan-6 FPGA Trainer Board
Key Specifications
Logic Cells
6,822 slices
Block RAM
2.1Mbits
Clock Tiles
4 (8 DCMs & 4 PLLs)
PLLs
6
DDR2
128MB with 16-bit wide data
DSP Slices
58
Internal clock
500MHz+
Oscillator
100MHz CMOS
Quad-SPI Flash
16MB
Ethernet
10/100/1000 PHY
Connectivity and Onboard I/O
Pmod Connectors
1 12-pin Pmod port
USB
2 on-board USB2 ports for
programming and data transfer
HDMI
2 HDMI input and output ports
Audio
AC-97 Codec with line-in,
line-out, mic, and headphone
IOs
48 I/Os routed to expansion
connectors
Vmod Connectors
1 Vmod (high-speed VHDC)
connector
Switches
8 slide switches
Buttons
6
LEDs
8
Electrical
Power
5V (2.1mm) supply
Logic Level
3.3v
Physical
Width
4.8 in
Length
5.3 in
Design Resources
Master UCF
ZIP
Atlys Support Files
ZIP
Documentation
Primary IC
Spartan-6 LX45
(XC6SLX45-CSG324C)
VHDCI Plug
VHDCI Receptacle
Reference Manual
Schematic

The Atlys circuit board is a complete, ready-to-use digital circuit development platform based on a Xilinx Spartan-6 LX45 FPGA, speed grade -3. The large FPGA and on-board collection of high-end peripherals including Gbit Ethernet, HDMI Video, 128MByte 16-bit DDR2 memory, and USB and audio ports make the Atlys board an ideal host for a wide range of digital systems, including embedded processor designs based on Xilinx’s MicroBlaze. Atlys is compatible with all Xilinx CAD tools, including ChipScope, EDK, and the free ISE WebPack™, so designs can be completed at no extra cost.

The Spartan-6 LX45 is optimized for high-performance logic and offers:

  • 6,822 slices, each containing four 6-input LUTs and eight flip-flops
  • 2.1Mbits of fast block RAM
  • four clock tiles (eight DCMs & four PLLs)
  • six phase-locked loops
  • 58 DSP slices
  • 500MHz+ clock speeds

The Atlys board includes Digilent's newest Adept USB2 system, which offers device programming, real-time power supply monitoring, automated board tests, virtual I/O, and simplified user-data transfer facilities.

A comprehensive collection of board support IP and reference designs, and a large collection of add-on boards are available on the Digilent website. See the Atlys page at www.digilentinc.com for more information.



Tutorials


Example Projects

  • Atlys Demo/BIST ConfigZIP
    • Source code for Atlys Demo/BIST configuration (factory loaded into SPI Flash)
  • Flash Memory ConfigZIP
    • Source code for Atlys DDR2 and SPI Flash memory controller configuration
  • VmodTFT DemoZIP
    • This demo project is for the VmodTFT and either the Nexys3 or the Atlys. It continuously samples the VmodTFT's touch panel for X, Y and pressure values and lights up the pixels touched.
  • EDK Microblaze DemoDownload
    • This zip file contains an EDK demo project that illustrates how to use the AC97 codec on the Atlys board with Microblaze.
  • EDK HDMI DemoZIP
    • This zip file contains an EDK demo project that demonstrates using HDMI on the Atlys board. It accepts an HDMI input, buffers the input frames into memory, and then outputs the buffer to another HDMI port. This is implemented using PLB bus.
  • ISE DemoZIP
  • Download This zip file contains an ISE demo project that demonstrates the use of general I/O and UART on the Atlys board in VHDL.
  • EDK Web ServerZIP
    • This zip file contains an EDK demo project that illustrates how to host a web server on the Atlys. It was built using EDK 14.3.

Additional Resources

Firmware

  • Binary Image for BISTZIP
    • Built binary image for Atlys_Demo_BIST. This can be used to restore the original factory image in the Atlys SPI Flash. To reprogram, use the Flash tab in the Adept Application.