Sword Reference Manual

Powered by Xilinx's Kintex-7 XC7K325T FPGA, the Sword board provides a wide variety of onboard peripherals, memory devices and I/O. Additional expansion connectors in the form of Pmod connectors and a Chipkit/Arduino header make the potential uses for the Sword board nearly limitless.

Wide high-speed memory interfaces in the form of two SRAMs with a shared address bus and a 1GB DDR3 provide a powerful environment for experimenting with different memory architectures. In addition, these memories provide good support for common networking applications.

The Sword board's Kintex-7 XC7K325T FPGA is compatible with Xilinx’s high-performance Vivado® Design Suite and requires the full software license. WebPack is not supported. Licensing information for Vivado can be found here. Academic institutes can request full Vivado licenses here.


Features

  • Xilinx Kintex-7 325T FPGA (XC7K325T-2FFG900C)
    • 50,950 slices
    • 2,002.5 KB of block RAM
    • 10 clock management tiles, each with phase-locked loop (PLL) and mixed-mode clock manager (MMCM)
    • 840 DSP slices
    • Internal clock speeds exceeding 700MHz
    • On-chip analog-to-digital converter (XADC)
    • GTX multi-gigabit transceivers
  • Memory
    • 1GB DDR3 with 32-bit bus @ 1800MHz
    • 32MB Quad-SPI Flash with three factory programmed 48-bit globally unique EUI-48/64™ compatible identifiers
    • 2MB and 4MB SRAMs with a shared 32-bit address bus.
    • 32MB Parallel Flash with 32-bit bus
    • microSD card slot for bitfile programming only
  • Power
    • Powered from 12V PCI Express auxiliary power supply
    • Pre-installed FPGA heat sink and cooling solution
  • USB, Ethernet, and other Connectivity
    • 10/100/1000 Mbps Ethernet PHY interface
    • 2 10Gbps SFP+ PHY interfaces
    • USB-JTAG programming circuitry
    • USB-UART bridge
    • USB 2.0 PHY with host support
    • USB HID Host for mice and keyboards
    • TTL-compliant UART Header
    • RS232 port
  • Audio and Video
    • HDMI sink port (input)
    • HDMI source port (output)
    • VGA output port with 16-bit color and external display connectors
    • Audio codec with headphone, stereo line out, stereo line in, and microphone jacks
  • Onboard I/O
    • 8-digit 7-segment display
    • 25-button keypad
    • 3 reset buttons
    • 16 slide switches
    • 16 LEDs
    • 2 RGB LEDs
  • Expansion Connectors
    • Arduino/chipKit Shield connector
      • 45 total FPGA I/O
      • 6 Single-ended 0-3.3V Analog inputs to XADC
      • 4 Differential 0-1.0V Analog input pairs to XADC
    • 4 Pmod ports
      • 32 total FPGA I/O

Sword Board with Callouts.

Callout Description Callout Description Callout Description
1 6-pin PCIE power connector 12 Ethernet port 23 User switches
2 Arduino IDE reset jumper 13 2 port SFP+ cage 24 User LEDs
3 Shared USB JTAG / UART port 14 USB host port 25 MicroSD card slot
4 USB HID port 15 User reset buttons 26 User RGB LEDs
5 HDMI sink port 16 FPGA programming reset button 27 SPI header (Arduino/ChipKit compatible)
6 HDMI source port 17 FPGA programming DONE LED 28 Arduino/ChipKit shield connectors
7 VGA connector 18 25-button keypad 29 Pmod headers
8 Audio jacks 19 Kintex-7 FPGA, heat sink, and fan 30 Shield connector I2C pullup-enable jumpers
9 3-pin TTL-Compliant UART Header 20 Parallel flash memory 31 FPGA configuration mode jumpers
10 RS232 Port 21 SRAM memory 32 Power good LED
11 DDR3 memory 22 8-digit seven segment display 33 Power switch

Functional Description

1 Power Supplies

The Sword board power circuitry was carefully designed to meet the requirements of the Kintex-7 and all other peripherals. An overview of the power circuit is shown in Figure 1.1.

Figure 1.1 Power Circuit Overview

All on-board power supplies are enabled or disabled by the power switch (SW16, labeled POWER). The power indicator LED (LD25) is on when all the supply rails reach their nominal voltage.

1.1 Power Input Sources

The Sword board is powered with a power supply that can provide 12V +- 5% through the 6-pin PCIE connector (J32). The minimum current rating of the supply depends on the actual design implemented in the FPGA, but a 10A (120W) supply should be sufficient for the vast majority of applications.

Table 1.1.1 provides an overview of the power input specifications for the Sword board.

Connector Type Connector Label Schematic net name Min/Rec/Max Voltage (V)
6-pin Mini-Fit PCI Express J32 VIN12V0 11.4/12/12.6

Table 1.1.1 Sword Power Input Specifications

1.2 Power Specifications

Input power to the board is gated by the TPS25926X, an e-fuse protection circuit from Texas Instruments providing both inrush and general current limit along with over-voltage protection.

Voltage regulator circuits from Linear Technology create the different voltages required by the FPGA and on-board peripherals from the main power input. Some regulators use the outputs of another regulator as input, depending on design considerations. In some cases this chaining helps in creating the proper power-on sequence for circuits. In other cases the chaining of power supply enable signals achieves the same purpose.

Table 1.2.1 describes the characteristics the Sword's on-board power rails. It can be used to estimate power consumption for a project, or determine how much current attached peripherals can draw before being limited.

Supply Circuits Device Current (max)
12.0V Arduino/chipKit Shield Connector, 12V Display Power IC43: TPS25926 3.0A
1.0V FPGA Core and Block RAM, Ethernet IC42: LTC3866 16.0A
1.8V FPGA Auxiliary, Ethernet IC45: LTC3605 5.0A
2.0V FPGA Auxiliary IC46: LT1762 0.15A
3.3V FPGA I/O, Pmods, Arduino/chipKit Shield Connector, HDMI, USB, Ethernet, SFP+, Flash, SRAM IC50: LTC3855 7.0A
5.0V Arduino/chipKit Shield Connector, 5V Display Power, RGB LEDs, HDMI IC50: LTC3855 5.5A
1.0V Gigabit Transceivers VCC IC49: LTC3083 2.0A
1.2V Gigabit Transceivers VTT IC47: LTC3026 1.5A
1.8V Gigabit Transceivers AUX IC48: LT1762 0.15A
1.5V DDR3 and FPGA I/O IC44: LTC3618 2.0A
0.75V DDR3 Termination IC44: LTC3618 2.0A
0.75V FPGA and DDR3 Reference IC44: LTC3618 10mA
1.25V XADC Reference IC54: LT1790 5mA
1.8V XADC Supply IC53: LT1761 0.1A
3.3V Audio Analog Supply IC16: LT1761 0.1A
5.0V USB Host IC18: TPS2051 0.5A

Table 1.2.1 Sword Power Rail Specifications


2 FPGA Configuration

After power-on, the Kintex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of three ways:

  1. A PC can use the Digilent USB-JTAG circuitry (port J28, labeled PROG) to program the FPGA any time the power is on.
  2. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
  3. A file stored in a FAT32 formatted SD card or USB drive can be used to program the FPGA using the microSD card slot or USB HID port.

Figure 2.1 shows the different options available for configuring the FPGA. On-board “mode” jumpers (JP3 and JP4, labeled CONFIGURATION) select how the FPGA will be programmed on power up.

Figure 2.1 Sword FPGA Configuration.

The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or block-level design.

Bitstreams are stored in volatile memory cells within the FPGA. This data defines the FPGA’s logic functions and circuit connections, and it remains valid until it is erased by removing board power, by pressing the reset button attached to the PROG input, or by writing a new configuration file using the JTAG port.

A Kintex-7 325T bitstream is typically 91,548,896 bits. The time it takes to program the Sword can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.

After being successfully programmed, the FPGA will cause the “DONE” LED (LD24) to illuminate. Pressing the “PROG” button at any time will reset the configuration memory in the FPGA. After being reset, if the “CONFIGURATION” jumper is set to “QSPI” then the FPGA will immediately attempt to reprogram itself from Quad SPI flash.

The following sections provide greater detail about programming the Sword using the different methods available.

2.1 JTAG Configuration

The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (J28) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to the 6-pin JTAG port (J29). JTAG programming can be performed any time after the Sword has been powered on, regardless of whether the configuration jumper (JP4) is set. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Not setting the configuration jumper (seen in Figure 2.1) is useful to prevent the FPGA from being configured from Quad-SPI Flash until a JTAG programming occurs.

Programming the Sword with an uncompressed bitstream using the on-board USB-JTAG circuitry usually takes around 4 seconds. JTAG programming can be done using the hardware manager in Vivado.

2.2 Quad-SPI Configuration

Since the FPGA's memory on the Sword is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. This configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. To that effect, a configuration file needs to be downloaded first to the flash. When programming a non-volatile flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). This is called indirect programming. After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting (see Figure 2.1). Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.

Programming the flash can take several minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written however, FPGA configuration can be very fast — less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Sword supports x1, x2, and x4 bus widths for Quad-SPI programming.

Quad-SPI programming can be done using the hardware manager in Vivado. The target Configuration Memory Device shall be called “s25fl256sxxxxxx0”.

2.3 USB Host and Micro SD Programming

The FPGA can be programmed from a USB drive attached to the USB Host port (J26, labeled PIC) or a microSD card inserted into the SD card slot (J27, on the bottom of the Sword) by doing the following:

  1. Format the storage device (USB drive or microSD card) with a FAT32 file system.
  2. Place a single .bit configuration file in the root directory of the storage device.
  3. Attach the storage device to the Sword.
  4. Set the configuration mode jumper (JP4) on the Sword to “USB/SD”.
  5. Select the desired storage device (USB or SD) with JP3.
  6. Push the PROG button or power-cycle the Sword.

The FPGA will automatically be configured with the .bit file on the selected storage device. Any .bit files that are not built for the proper Kintex-7 device will be rejected by the FPGA.

The Auxiliary Function Status, or “BSY” LED, gives visual feedback on the state of the configuration process when the FPGA is not yet programmed:

  • When steadily lit, the auxiliary microcontroller is either booting up or currently reading the configuration medium (microSD or USB drive) and downloading a bitstream to the FPGA.
  • A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.
  • In case of an error during configuration, the LED will blink rapidly.

When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from a connected USB keyboard or mouse.


3 DDR3

The Sword board includes two Micron MT41K256M16TW-107 DDR3 memory components creating a single rank, 32-bit wide interface. This interface is routed to two 1.5V-powered HP (High Performance) FPGA banks with 40 ohm controlled single-ended trace impedance. For data signals 40 ohm DCI terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side on-die terminations (ODT) are used for impedance matching. Address/Control signals are terminated using discrete resistors.

The highest data rate supported is 1800Mbps.

For proper operation of the memory a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The Xilinx 7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard hides away the complexities of a DDR3 interface. The MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of several DDR3 parameters optimized for the particular application. Table 3.1 below lists the MIG Wizard settings optimized for the Sword.

Setting Value
Memory type DDR3 SDRAM
Max. clock period 1112ps (~900MHz)
Max. data rate ~1800Mbps
Clock ratio 4:1
VCCAUX_IO 2.0V
Memory type Components
Memory part MT41K256M16XX-107
Memory voltage 1.5V
Data width 32
Data mask Enabled
Input clock period 5004ps (~200MHz)
Output driver impedance RZQ/7
Chip Select pin Enabled
Rtt (nominal) – On-die termination RZQ/6
Internal Vref Disabled
Reference clock Use system clock
Internal termination impedance N/A
DCI cascade Disabled

Table 3.1 DDR3 settings for the Sword board

For clocking, it is recommended that the System clock be set to “Differential”, and connected directly to the onboard 200MHz oscillator on pins AD12 and AD11 (P and N respectively). No reference clock is required.

The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core. For those using the MIG with a MicroBlaze project, the Sword MIG settings and pinout will be automatically imported from the Digilent Vivado board files.

For more details on the Xilinx memory interface solutions refer to the 7 Series FPGAs Memory Interface Solutions User Guide (ug586).


4 SRAM

The Sword board includes 6 MB of Static Random-Access Memory (SRAM). The SRAM is made up of two memories with a shared 20-bit address bus and separate control signals. SRAM1 has 16 bi-directional data signals and can contain up to 2MB of data. SRAM2 has 32 bi-directional data signals and can contain up to 4MB of data. The parts used to implement these memories are three CY7C1061GE30-10BVXI chips. Each of the three parts has a theoretical maximum data bandwidth of 100Mbps per data signal used.

The Xilinx AXI External Memory Controller (EMC) IP can be used to connect the SRAM memories to a Microblaze processor. At the time of writing, this is not supported in Digilent's board files, meaning that the SRAM interface pins must be manually constrained. For pin-mappings between the FPGA and SRAM, please see the Sword Master XDC available at the Sword Resource Center. See the datasheet for the CY7C1061GE30 part for more information about the memories.


5 Quad-SPI Flash

FPGA configuration files can be written to the Quad-SPI Flash (Spansion part number S25FL256S), and setting the mode jumper (labeled CONFIGURATION) to QSPI will cause the FPGA to automatically read a configuration from this device at power on. A Kintex-7 325T configuration file requires 91,548,896 bits of memory, leaving about 61% of the flash device (or ~20MB) available for user data. A common use for this extra memory is to store Microblaze programs too big to fit in the onboard Block memory. These programs are then loaded and executed using a smaller bootloader program that can fit in the block memory. It is possible to automatically generate this bootloader, roll it into your bitstream, and then program the bitstream and large Microblaze program into the Quad SPI Flash using Xilinx SDK.

The contents of the memory can be manipulated by issuing certain commands on the SPI bus. The implementation of this protocol is outside the scope of this document. Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to Spansion's datasheet for the flash device to learn how to implement a custom controller.

The Sword comes with three MAC addresses pre-programmed in a special one time programmable region (OTP Region 1) of the Quad-SPI Flash. These addresses are intended to be used to uniquely identify the Ethernet and SFP+ ports on a network. They can be read with the OTP Read command (0x4B) and are placed in the first eighteen bytes of OTP Region 1 (byte addresses 0x20 to 0x31). Each MAC address takes up six consecutive bytes.

All signals in the SPI bus are general-purpose user I/O pins after FPGA configuration and can be used like any other FPGA I/O, except for the SPI clock (SCK). SCK can only be accessed by instantiating a special primitive called STARTUPE2. The Xilinx AXI Quad SPI IP core has a configuration option that will automatically instantiate the primitive, and this option should be enabled when using it with the Sword. For information on instantiating the primitive from HDL, refer to the “Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide” (UG953) from Xilinx.

Figure 5.1 Sword Quad SPI flash.

Figure 5.1 Sword Quad SPI Flash


6 Parallel Flash

The Parallel Flash consists of two Cypress devices (part number S29GL128S10DHI010) and is organized as 8 Mwords of 32bits each. The two devices share address signals and have separate control signals. They each contain 128 individually erasable 1 Mbit sectors. Several Address Space Overlays provide a variety of additional functions, including data protection, and access to the status register, device identification and common flash interface. The parallel flash offers 90 ns read cycle times, with 15 ns page-mode reads within blocks. Each device has an internal 512-byte write buffer that can be used to program the flash at an effective rate of 1.33us per word (typical).

The Xilinx AXI External Memory Controller (EMC) IP can be used to connect the Parallel Flash to a Microblaze processor. At the time of writing, this is not supported in Digilent's board files, meaning that the Flash interface pins must be manually constrained. For pin-mappings between the FPGA and Parallel Flash devices, please see the Sword Master XDC available at the Sword Resource Center. For more information about the memories, please see the Cypress part datasheet.


7 Oscillators/Clocks

The Sword board includes several oscillators and crystals, of which one is connected to the FPGA. One differential LVDS 200MHz oscillator is connected to MRCC GPIO pins AD12/AD11 in bank 33. The clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 200MHz input clock. For a full description of these rules and of the capabilities of the Kintex-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” (ug472) available from Xilinx.

Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard will properly instantiate the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy-to-use wrapper component around these clocking resources that can be inserted into the user’s design. The clocking wizard can be accessed from within the Vivado and IP Integrator tools.

The FPGA's GTX transceivers should be clocked using the clock generated by the on-board Si5324 clock multiplication circuit discussed in Section 9 SFP+ Interfaces.


8 Ethernet PHY

The Sword board includes a Realtek RTL8211E-VL PHY paired with an RJ-45 Ethernet jack with integrated magnetics to implement a 10/100/1000 Ethernet port for network connection. All FPGA-connected ethernet signals are connected to Bank 32, powered at 1.8V. The PHY interfaces with the FPGA via RGMII for data and MDIO for management. The auxiliary interrupt (INTB), power management (PMEB) signals are open-drain outputs from the PHY and need internal pull-ups enabled in the FPGA if they are to be used. The connection diagram can be seen on Figure 8.1.

At power-on reset, the PHY is set to the following defaults using the configuration pins in parenthesis:

  • Auto-negotiation enabled, advertising all 10/100/1000 modes (AN[1:0])
  • PHY address=00001 (PHY_AD[2:0])
  • No delay for TXD and RXD relative to TXC and RXC for data latching (RXDLY, TXDLY)

If an Ethernet cable is plugged in, establishing link is attempted straight after power-up, even if the FPGA is not programmed.

Two status indicator LEDs are on-board near the RJ-45 connector that indicate traffic (LD20) and valid link state (LD19). The table below shows the default behavior.

Function Designator State Description
ACT LD20 Blinking Transmitting or receiving
LINK LD19 On Link up
Blinking 0.4s ON, 2s OFF Link up, Energy Efficient Ethernet (EEE) mode

Table 8.1 Ethernet status LEDs

The on-board PHY implements Layer 1 in the Ethernet stack, interfacing between the physical copper medium and the media access control (MAC). The MAC must be implemented in the FPGA and mapped to the PHY’s RGMII interface. Vivado-based design can use the Xilinx AXI Ethernet Subsystem IP core to implement the MAC and wire it to the processor and the memory subsystem. At the time of writing the IP core needed to be licensed separately.

On an Ethernet network each node needs a unique MAC address. To this end the Sword comes with three MAC address pre-programmed in a special one-time programmable region (OTP Region 1) of the Quad-SPI Flash. Two of these MAC addresses are intended for use with the Sword's SFP+ connectors. These unique identifiers can be read with the OTP Read command (0x4B).

Figure 8.1 Ethernet Connections Figure 8.1 Ethernet Connections


9 SFP+ Interfaces

The Sword board provides two enhanced small form factor pluggable (SFP+) connectors, each supporting 10Gbps. Two of the FPGA’s high speed serial GTX transceivers on Bank 118 are dedicated to these ports. These connectors are capable of implementing 10GBase-SR/LR Ethernet Protocols. In addition, a high-precision clock multiplication circuit (Silicon Labs' Si5324, datasheet available here) is provided on the Sword to provide clock frequencies in excess of 1GHz to the GTX tranceivers. The Si5324 can be configured with an IIC interface connected to Bank 12 of the FPGA (IIC address 0b1101000) and uses an on-board 114.285 MHz oscillator as an input clock source.

As mentioned in Section 8 Ethernet PHY, two unique MAC addresses intended for use with the SFP+ connectors are provided in OTP Region 1 of the Quad-SPI Flash.


10 USB-UART Bridge

The Sword board includes an FTDI FT2232HQ USB-UART bridge (attached to connector J20) that allows you to use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from www.ftdichip.com under the “Virtual Com Port” or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the G29 and F30 FPGA pins.

Two on-board status LEDs provide visual feedback on traffic flowing through the port: the transmit LED (LD23) and the receive LED (LD22). Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.

The FT2232HQ is also used as the controller for the Digilent USB-JTAG circuitry, but the USB-UART and USB-JTAG functions behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with the UART data transfers, and vice-versa. The combination of these two features into a single device allows the Sword board to be programmed and communicated with via UART with a single Micro USB cable.

The CK_RST signal (see the Sword board Schematic) is also connected to the FT2232HQ device via JP2. When JP2 is shorted, the FT2232HQ can trigger a Microblaze reset, mimicking the behavior of Arduino and chipKIT boards when sketches are loaded. Note the CK_RST signal is also connected to the red RESET button and the RST pin of J8 on the shield connector (these connections are not shown in Figure 10.1). It is recommended that this jumper is not shorted unless attempting to run Arduino IDE on Microblaze, because it can interfere with normal Microblaze function.

The connections between the FT2232HQ and the Kintex-7 are shown in Figure 10.1.

Figure 10.1 UART connections

Figure 10.1 UART connections


11 USB PHY Host

The Sword uses a Maxim MAX3421E PHY to implement a USB 2.0 Host port on the USB A connector (J22, labeled USBH). This port can be used to interact with a massive variety of peripherals, including mice, keyboards, additional external memory, etc. The Sword board can provide 5 Volts at up to 500mA of current to peripherals connected to the port. The PHY connects to the FPGA on Bank 18 using a SPI interface with maximum SCLK frequency of 26MHz with several additional signals. The behavior of the interrupt (USBH_INT) and general purpose output (USBH_GPX) signals should be configured through the use of the SPI interface. Xilinx's AXI Quad SPI, with an optional AXI GPIO IP for usage of the USBH_INT and USH_GPX signals, can be used to connect the Maxim PHY to a Microblaze processor. For pin-mappings between the FPGA and PHY, see the Sword Master XDC available at the Sword Resource Center. Additional information about the PHY, including the datasheet, can be found at Maxim's product page.


12 USB HID Host

The Auxiliary Function microcontroller (Microchip PIC24FJ128, IC26) provides the Sword with USB HID host capability. More information on this part can be found here.

After power-up, the microcontroller is in configuration mode, either downloading a bitstream to the FPGA, or waiting for it to be programmed from other sources. Once the FPGA is programmed, the microcontroller switches to application mode, which, in this case, is USB HID Host mode. Firmware in the microcontroller can drive a mouse or a keyboard attached to the type A USB connector at J26 labeled “USB”. Hub support is not currently available, so only a single mouse or a single keyboard can be used. The PIC24 drives several signals into the FPGA, of which two are used to implement a standard PS/2 interface for communication with a mouse or keyboard, while the others are connected to the FPGA’s two-wire serial programming port, so the FPGA can be programmed from a file stored on a USB drive.

Figure 12.1 PS/2 connections

Figure 12.1 PS/2 connections

12.1 HID Controller

The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host. On the Sword, the microcontroller emulates a PS/2 device while the FPGA plays the role of the host. Both the mouse and the keyboard use 11-bit words that include a start bit, data byte (LSB first), odd parity, and stop bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in the below figure. As seen in Figure 12.1, the HID controller is connected to the FPGA via two PS/2 interfaces. When a keyboard is connected, PS/2 interface 0 is used. When a mouse is connected, PS/2 interface 1 is used.

Figure 12.1.1 PS/2 Timing Diagram Figure 12.1.1 PS/2 Timing Diagram

The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic ‘1.’ This requires that when the PS/2 signals are used in a design, internal pull-ups must be enabled in the FPGA on the data and clock pins. The clock signal is normally driven by the device, but may be held low by the host in special cases. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface.

When a keyboard or mouse is connected to the Sword, a “self-test passed” command (0xAA) is sent to the host. After this, commands may be issued to the device. Since both the keyboard and the mouse use the same PS/2 port, one can tell the type of device connected using the device ID. This ID can be read by issuing a Read ID command (0xF2). Also, a mouse sends its ID (0x00) right after the “self-test passed” command, which distinguishes it from a keyboard.

12.2 Keyboard

The keyboard uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire interface of PS2_CLK0 and PS2_DATA0 (if the host device will not send data to the keyboard, then the host can use input-only ports).

PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms. When a key is released, an F0 key-up code is sent, followed by the scan code of the released key. If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an E0 ahead of the scan code (and they may send more than one scan code). When an extended key is released, an E0 F0 key-up code is sent, followed by the scan code. Scan codes for most keys are shown in the below figure.

Figure 12.2.1 Keyboard Scan Codes

A host device can also send data to the keyboard. The keyboard can send data to the host only when both the data and clock lines are high (or idle). Because the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host drives the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30KHz) when the data is sent, and data is valid on the falling edge of the clock.

Command Action
ED Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns FA after receiving ED, then host sends a byte to set LED status: bit 0 sets Scroll Lock, bit 1 sets Num Lock, and bit 2 sets Caps lock. Bits 3 to 7 are ignored.
EE Echo (test). Keyboard returns EE after receiving EE
F3 Set scan code repeat rate. Keyboard returns F3 on receiving FA, then host sends second byte to set the repeat rate.
FE Resend. FE directs keyboard to re-send most recent scan code.
FF Reset. Resets the keyboard.

Table 12.2.1 Keyboard Command Codes

12.3 Mouse

When a mouse is connected to the USBHID port, the PIC24 uses the two-wire interface of PS2_CLK1 and PS2_DATA1 to facilitate communication between the mouse and FPGA.

Once entered in stream mode and data reporting has been enabled, the mouse outputs a clock and data signal when it is moved: otherwise, these signals remain at logic ‘1.’ Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device, as shown in Fig 10. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in the below figure. Data is valid at the falling edge of the clock, and the clock period is 20 to 30KHz.

Figure 12.3.1 Mouse Codes

The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a ‘1’ indicates the button is being pressed).

The microcontroller also supports Microsoft Intellimouse-type extensions for reporting back a third axis representing the mouse wheel, as shown in the below table.

Command Action
EA Set stream mode. The mouse responds with “acknowledge” (0xFA) then resets its movement counters and enters stream mode.
F4 Enable data reporting. The mouse responds with “acknowledge” (0xFA) then enables data reporting and resets its movement counters. This command only affects behavior in stream mode. Once issued, mouse movement will automatically generate a data packet.
F5 Disable data reporting. The mouse responds with “acknowledge” (0xFA) then disables data reporting and resets its movement counters.
F3 Set mouse sample rate. The mouse responds with “acknowledge” (0xFA) then reads one more byte from the host. This byte is then saved as the new sample rate, and a new “acknowledge” packet is issued.
FE Resend. FE directs mouse to re-send last packet.
FF Reset. The mouse responds with “acknowledge” (0xFA) then enters reset mode.

Table 12.3.1 Mouse Command Codes


13 HDMI Ports

The Sword board contains two buffered HDMI ports: one source port (HDMI OUT, J16), and one sink port (HDMI IN, J17). Both ports use HDMI type-A receptacles and include HDMI buffer TMDS141. The buffers work by terminating, equalizing, conditioning, and forwarding the HDMI stream between the connector and FPGA pins.

Both HDMI and DVI systems use the same TMDS signaling standard, directly supported by Kintex-7 user I/O infrastructure. Also, HDMI sources are backward compatible with DVI sinks, and vice versa. Thus, simple passive adaptors (available at most electronics stores) can be used to drive a DVI monitor or accept a DVI input. The HDMI receptacle only includes digital signals, so only DVI-D mode is possible.

The 19-pin HDMI connectors include three differential data channels, one differential clock channel, five GND connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus that is essentially an I2C bus, a Hot Plug Detect (HPD) signal, a 5V signal capable of delivering up to 50mA, and one reserved (RES) pin. All non-power signals are wired to the FPGA with the exception of RES.

Pin/Signal HDMI OUT HDMI IN
Description FPGA pin Description FPGA pin
D[2]_P, D[2]_N Data output AG22, AH22 Data input AF26, AF27
D[1]_P, D[1]_N Data output AJ22, AJ23 Data input AH26, AH27
D[0]_P, D[0]_N Data output AH21, AJ21 Data input AJ26, AK26
CLK_P, CLK_N Clock output AG20, AH20 Clock input AG29, AH29
CEC Consumer Electronics Control bidirectional (optional) AH25 CEC bidirectional (optional) AF21
SCL, SDA DDC bidirectional (optional) AK20, AK21 DDC bidirectional AK24, AK23
HPD/HPA Hot-plug detect input (inverted, optional) AG25 Hot-plug assert output AF20

Table 13.1 HDMI pin description and assignment

13.1 TMDS Signals

HDMI/DVI is a high-speed digital video stream interface using transition-minimized differential signaling (TMDS). To make proper use of either of the HDMI ports, a standard-compliant transmitter or receiver needs to be implemented in the FPGA. The implementation details are outside the scope of this manual. Check out the vivado-library IP Core repository on the Digilent github for ready-to-use reference IP. The IP cores for transmitting and receiving are called rgb2dvi and dvi2rgb, respectively.

13.2 Hot Plug Signals

Whenever a sink is ready and wishes to announce its presence, it connects the 5V0 supply pin to the HPD pin. On the Sword board, this is done by driving the Hot Plug Assert signal (HDMI_RX_HPD) high. This signal defaults low. The source reads the Hot Plug Detect signal (HDMI_TX_HPD) through an inverting level-translator, so the signal reads low when a sink is present.

13.3 DDC Signals

The Display Data Channel, or DDC, is a collection of protocols that enable communication between the display (sink) and graphics adapter (source). The DDC2B variant is based on I2C, the bus master being the source and the bus slave the sink. When a source detects high level on the HPD pin, it queries the sink over the DDC bus for video capabilities. It determines whether the sink is DVI or HDMI-capable and what resolutions are supported. Only afterwards will video transmission begin. Refer to VESA E-DDC specifications for more information. IP supplied by Digilent in our Github repository vivado-library (Digilent Github) include DDC support and some pre-defined display descriptor data. Note that Digilent-provided IP intended for use with the VGA connectors (described later in this document) do not support DDC. Since the DDC connection is based on IIC, Xilinx's AXI IIC IP core can be used to read the VGA interface's DDC bus.

13.4 CEC Signal

The Consumer Electronics Control, or CEC, is an optional protocol that allows control messages to be passed around on an HDMI chain between different products. A common use case is a TV passing control messages originating from a universal remote to a DVR or satellite receiver. It is a one-wire protocol at 3.3V level connected to an FPGA user I/O pin. The wire can be controlled in an open-drain fashion allowing for multiple devices sharing a common CEC wire. Refer to the CEC addendum of HDMI 1.3 or later specifications for more information.


14 VGA Ports

The Sword board uses 20 programmable logic pins to create an analog VGA output port. This translates to 16-bit color depth, two standard sync signals (HS – Horizontal Sync, and VS – Vertical Sync), and an optional DDC interface. The digital-to-analog conversion is done using a simple R-2R resistor ladder¹. The ladder works in conjunction with the 75-ohm termination resistance of the VGA display to create different analog signal levels on the red, blue, and green wires. This circuit, shown in Fig. 14.1, produces video color signals that proceed in equal increments between 0V (fully off) and 0.7V (fully on). With 5 bits each for red and blue and 6 bits for green, 65,536 (32×32×64) different colors can be displayed, one for each unique 16-bit pattern.

More information about the DDC interface (signals VGA_SCL and VGA_SDA) can be found in Section 13.3 DDC Signals.

Figure 14.1 Sword VGA circuit Figure 14.1 Sword VGA circuit

A video controller circuit must be created in programmable logic to drive the sync and color signals with the correct timing in order to produce a working display system.

This VGA interface can be used with one of two different connectors on the Sword. A standard DB15 connector is provided (J12, labeled VGA), which allows the Sword to be connected to any typical VGA-supporting monitor. The DB15 connector can supply up to 50mA at 5V on pin 9 to the connected display and uses additional circuitry to protect against shorts. In addition, a custom expansion connector (J15, Centronic Precision Electronic Company PXWS12TB4A2) can be used to connect the Sword to other displays.

Two Centronic expansion power connectors (J13, labeled 5V0 OUT, and J14, labeled 12V0 OUT) can be used to provide power to 5V and 12V external displays. Each of these connectors can provide up to 2A of current.

¹http://en.wikipedia.org/wiki/Resistor_ladder

14.1 VGA System Timing

VGA signal timings are specified, published, copyrighted, and sold by the VESA organization (www.vesa.org). The following VGA system timing information is provided as an example of how a VGA monitor might be driven in 640 by 480 mode.

NOTE: For more precise information, or for information on other VGA frequencies, refer to documentation available at the VESA website.

CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs). Color CRT displays use three electron beams (one for red, one for blue, and one for green) to energize the phosphor that coats the inner side of the display end of a cathode ray tube (see Fig. 14.1.1).

Figure 14.1.1 Color CRT display.

Electron beams emanate from “electron guns” which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid.” The electrostatic force imposed by the grid pulls rays of energized electrons from the cathodes, and those rays are fed by the current that flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor-coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow.

Between the grid and the display surface, the beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), they can be deflected by these magnetic fields. Current waveforms are passed through the coils to produce magnetic fields that interact with the cathode rays and cause them to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom, as shown in Fig. 14.1.2. As the cathode ray moves over the surface of the display, the current sent to the electron guns can be increased or decreased to change the brightness of the display at the cathode ray impact point.

Information is only displayed when the beam is moving in the “forward” direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution.

Modern VGA displays can accommodate different resolutions, and a VGA controller circuit dictates the resolution by producing timing signals to control the raster patterns. The controller must produce synchronizing pulses at 3.3V (or 5V) to set the frequency at which current flows through the deflection coils, and it must ensure that video data is applied to the electron guns at the correct time. Raster video displays define a number of “rows” that corresponds to the number of horizontal passes the cathode makes over the display area, and a number of “columns” that corresponds to an area on each row that is assigned to one “picture element”, or pixel. Typical displays use from 240 to 1200 rows and from 320 to 1600 columns. The overall size of a display and the number of rows and columns determines the size of each pixel.

Figure 14.1.2 VGA horizontal synchronization.

Video data typically comes from a video refresh memory; with one or more bytes assigned to each pixel location (the Sword uses 16 bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel.

A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in Fig. 14.1.3 can be derived. Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot be displayed) are based on observations taken from actual VGA displays.

Figure 14.1.3 Signal timings for a 640-pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh

A VGA controller circuit, such as the one diagramed in Fig. 14.1.4, decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. You can use this counter to locate any pixel location on a given row. Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and you can use this counter to locate any given row. These two continually running counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so you can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation.

Figure 14.1.4 VGA display controller block diagram.


15 Audio Codec

The Sword board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC15) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for headphone-out (J18-black), line-out (J19-green), line-in (J20-blue), and microphone-in (J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono.

To record or play back audio in an FPGA design, the audio data needs to be converted from/to analog signals. The audio codec bridges the gap between the analog jacks and the digital FPGA pins. Analog-to-digital and digital-to-analog conversion is done at up to 24 bits and 96 kHz sampling rate. Digital audio data is carried to/from the FPGA on a serial, full-duplex interface, which supports several different formats, the default being I2S. This interface is clocked by the FPGA through BCLK by default, but the codec can be configured to provide the clock itself.

Configuring the audio codec can be done over I2C. It responds to slave address 0b0111011, followed by a 16-bit register address and one or more data bytes. These registers control every functional aspect of the codec.

The codec is clocked from the FPGA through the Master Clock (MCLK) pin. A clock must be provided for the codec to function, including the I2C port. The exact frequency depends on the desired sample rate and whether a PLL will be used to generate the clock, but 12 MHz is a good start. The clocking infrastructure of 7 series FPGA is more than capable of synthesizing the right frequency from the on-board 200 MHz reference oscillator.

For proper use, the concept of audio paths needs to be understood. Internal to the codec there are two signal paths: Playback and Record. Both are highly configurable analog paths with mixers and amplifiers that route audio signals through the chip. The Playback path is the output path that routes audio from different sources like the digital-to-analog converter or input mixers towards the headphone and line out jacks. On the other hand, the record path routes audio from the line-in and microphone-in towards the analog-to-digital converters. Having routing elements at every step enables signal mixing between channels, amplification, muting and bypass. However, it also means that each element has to be properly configured along the path.

Keep in mind that audio jack designations might differ from codec analog frontend designators. For example, the line-in jack connects to the AUX port of the codec. The microphone jack is wired to the IN port. Also, notice that although some ports offer differential amplifiers and signaling, they are not used on the Sword. For example, the OUT port is differential, comprising 4 pins: LOUTP, LOUTN, ROUTP, and ROUTN. However, the N-side of the differential pairs is left floating, while the P-side connects to the jack.

At the very least an audio-aware FPGA design should do the following:

  1. Provide MCLK for the audio codec.
  2. Use an I2C master controller to configure the core clocking, sample rates, serial interface format and audio path.
  3. Send or receive audio samples over the serial audio data channel for playback or record.

More advanced users might want to use additional features of the ADAU1761. For example, the on-chip SigmaDSP core can be programmed to do user-defined digital signal processing.

All relevant information can be found in the ADAU1761 datasheet.

Figure 15.1 Audio signal connections

Figure 15.1 Audio signal connections

Signal Name FPGA Pin Pin Function
ADC_SDATA AJ18 Serialized audio resulting from the analog-to-digital conversion (record).
DAC_SDATA AK18 Serialized audio is converted to analog by the codec (playback).
BCLK AD19 Serial data port clock.
LRCLK AE19 Serial data port frame clock.
MCLK AF17 Master clock.
SDA Y14 I2C configuration interface.
SCL AB14 I2C configuration interface.

Table 15.1 Audio signal description.


16 RS232 Port

The Sword board includes a RS232 Port (J9, labeled UART) so that the Sword can be connected to other systems that may not support the its other connectivity. An Analog Devices RS232 Line Driver/Receiver (part number ADM3232EARNZ) is used to drive the RS232 connection and electrically isolate the FPGA. This part supports data rates up to 460 Kbps and protects the FPGA against electrostatic discharges of up to +-15 kV. The RS232 port's TX and RX signals are connected to UART1_TXD and UART1_RXD (FPGA pins G12 and D11, respectively). The Xilinx Uartlite or Uartns16550 IP cores can be used to easily connect a Microblaze processor to the RS232 port. Additional information can be found in the Analog Devices datasheet.

Note: Directional names are given relative to the FPGA, so UART1_TXD is an output from the FPGA and UART1_RXD is an input to the FPGA.


17 3-Pin UART Header

The Sword board includes a TTL-compliant 3-pin UART header (J11) so that the Sword can be connected to systems that may require this voltage standard. Two Texas Instruments Single-bit Dual-supply Bus Transceivers (part number SN74LVC1T45) are used to translate between 3.3V logic levels required by the FPGA's bank 18 and the 5.0V levels of the TTL standard. The 3-Pin UART header's TX and RX signals are connected to UART2_TXD and UART2_RXD (F16 and C11 respectively). The Xilinx Uartlite or Uartns16550 IP cores can be used to easily connect a Microblaze processor to the 3-pin TTL UART header.

Note: Directional names are given relative to the FPGA, so UART2_TXD is an output from the FPGA and UART2_RXD is an input to the FPGA.


18 Basic I/O

The Sword board includes sixteen slide switches, sixteen individual LEDs, and two RGB LEDs, as shown in the below diagram.

Figure 18.1 Sword Basic I/O

Figure 18.1 Sword Basic I/O

The slide switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a slide switch was inadvertently defined as an output). Slide switches generate constant high or low inputs depending on their position.

The sixteen individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs, which are not user-accessible, indicate power-on, FPGA programming status, and USB port status.

18.1 User Reset Buttons

The red reset buttons BTNURST (labeled “RESET”) and BTNCK generate high outputs when at rest and low outputs when pressed. These buttons are intended to be used in Microblaze designs to reset the processor, but can also be used as a general purpose push buttons. Note that BTNCK is also tied to the RST pin on J8 of the shield connector and can be connected to the FT2232 UART device via jumper JP2, though these connections are not shown in the figure above.

18.2 Tri-Color LEDs

The Sword board contains two tri-color LEDs, labeled LD16 and LD17. Each tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the signal corresponding to one of these colors high will illuminate the internal LED. The input signals are driven by the FPGA through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding signals need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color.

Note: Digilent strongly recommends the use of pulse-width modulation (PWM) when driving the tri-color LEDs. Driving any of the inputs to a steady logic ‘1’ will result in the LED being illuminated at an uncomfortably bright level. This can be avoided by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the tri-color LED. Individually adjusting the duty cycle of each color between 50% and 0% causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed.


19 Twenty-Five-Button Keypad

The Sword board contains a 25-button keypad. Five row pins and five column pins are used to read the state of an array of 25 pushbuttons. For each column pin, as long as no corresponding button is pressed, a pull-up resistor maintains a logic level high voltage. When a button is pressed and the corresponding row pin is driven to a logic level low voltage, the column pin corresponding to that button will be read as a logic level low voltage instead. By driving the row pins low one at a time, the corresponding voltage on the column pins may be read to determine which button, if any, is currently being pressed. If more than two buttons are pressed at any one time, it may be impossible to determine which buttons these are.

Note: Since neither the column nor row pins have current-limiting series resistors, Digilent strongly recommends to place row pins that are not being driven low into high-impedance states in order to avoid short circuits while multiple buttons are pressed.

Figure 19.1 Twenty-Five Button Keypad Connections Figure 19.1 Twenty-Five Button Keypad Connections


20 Seven Segment Display

The Sword board contains eight one-digit common cathode seven-segment LED displays. Each of the eight digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 individual patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in the diagram below. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful.

To illuminate a segment, the anode should be driven high while the cathode is driven low. However, since the Sword uses a transistor to drive enough current into the common cathode point, the cathode enable is inverted. Therefore the seven segment enable signal (7SEG_EN) is driven high when active.

Eight 8-bit shift registers, chained together into a single 64-bit shift register, are used to control the anode signals. These shift registers clock data in from the shift-data-in signal (7SEG_SDO) on the positive edge of the seven segment clock signal (7SEG_CLK). While data is being clocked into the shift registers, the seven segment enable pin should be held low to deactivate the display and prevent LEDs from lighting up in an unintended way. When data has been fully shifted into the shift registers, the seven segment enable pin can be brought high again to activate the display. Data only needs to be loaded into the shift registers this way when the display's contents need to be changed. When shifting data into the shift registers, the data corresponding to the least-significant digit (DISP0) should be shifted out first, followed by the other digits in ascending order. The order of data bits within each segment is shown in Table 20.1. The naming convention for the seven segments and decimal point signals are expanded on in Figure 20.1.

Figure 20.2 Seven Segment Labels Figure 20.1 Seven Segment Labels

Bit 7 (First) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Last)
DP AG AF AE AD AC AB AA

Table 20.1 Seven Segment Bit Order

Figure 20.2 and Table 20.2 show the timing requirements of the Sword's Seven Segment circuitry.

Figure 20.2 Seven Segment Timing Diagram

Figure 20.2 Seven Segment Timing Diagram

Symbol Parameter Min
TCK Clock Time 6.5ns
TSU Data-to-clock setup time 5.0ns
THLD Clock-to-data hold time 0.5ns

Table 20.2 Seven Segment Minimum Timing Requirements


21 Pmod Connectors

Pmod connectors are 2×6, right-angle, 100-mil spaced female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 21.1. Each Pmod header can deliver up to 250mA of current, but care should be taken not to exceed any of the power budgets of the onboard regulators or the external power supply (these are described in Section 1 Power Supplies).

Warning: Since the Pmod pins are connected to Kintex-7 FPGA pins using a 3.3V logic standard, care should be taken not to drive these pins over 3.4V.

Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information.

The Sword board has four Pmod connectors, some of which behave differently than others. Each Pmod connector falls into one of two categories: standard or high-speed. Table 21.1 specifies which category each Pmod falls into and lists the FPGA pins they are connected to. The following sections describe the different types of Pmods.

Figure 19.1 Pmod connector Figure 21.1. Pmod connector

Pmod JA Pmod JB Pmod JC Pmod JD
Pmod Type High-Speed High-Speed Standard Standard
Pin 1 E24 B28 E28 E29
Pin 2 D24 A28 D28 E30
Pin 3 G23 A25 C29 H24
Pin 4 G24 A26 B29 H25
Pin 7 F26 D26 D29 G28
Pin 8 E26 C26 C30 F28
Pin 9 B27 C25 B30 G27
Pin 10 A27 B25 A30 F27

Table 21.1 Sword Pmod Pinout

21.1 Standard Pmod

The standard Pmod connectors are connected to the FPGA via 200 Ohm series resistors. The series resistors prevent short circuits that can occur if the user accidentally drives a signal that is supposed to be used as an input. The downside to this added protection is that these resistors can limit the maximum switching speed of the data signals. If the Pmod being used does not require high-speed access, then a standard Pmod connector should be used to help prevent damage to the devices.

21.2 High-Speed Pmod

The High-speed Pmods use the standard Pmod connector, but have their data signals routed as impedance matched differential pairs for maximum switching speeds. They have pads for loading resistors for added protection, but the Sword ships with these loaded as 0-Ohm shunts. With the series resistors shunted, these Pmods offer no protection against short circuits, but allow for much faster switching speeds. The signals are paired to the adjacent signals in the same row: pins 1 and 2, pins 3 and 4, pins 7 and 8, and pins 9 and 10.

Traces are routed 100 ohm (+/- 10%) differential.

These connectors should be used only when high speed differential signaling is required or the other Pmods are all occupied. If used as single-ended, coupled pairs may have significant crosstalk. In applications where this is a concern, the standard Pmod connector shall be used. Another option would be to ground one of the signals (drive it low from the FPGA) and use its pair for the signal-ended signal.

Since the High-Speed Pmods have 0-ohm shunts instead of protection resistors, the operator must take precaution to ensure that they do not cause any shorts.


22 Arduino/chipKIT Shield Connector

The Sword can be connected to standard Arduino and chipKIT shields to add extended functionality. Special care was taken while designing the Sword to make sure it is compatible with the majority of Arduino and chipKIT shields on the market. The shield connector has 45 pins connected to the FPGA for general purpose Digital I/O. Due to the flexibility of FPGAs, it is possible to use these pins for just about anything including digital read/write, SPI connections, UART connections, I2C connections, and PWM. Six of these pins (labeled AN0-AN5) can also be used as single-ended analog inputs with an input range of 0V-3.3V, and another six (labeled AN6-11) can be used as differential analog input pairs with an input range of 0V-1.0V.

Note: The Sword board is not compatible with shields that output 5V digital or analog signals. Driving pins on the Sword shield connector above 5V may cause damage to the FPGA.

Figure 22.1 diagrams the pins found on the shield connector of the Sword.

Figure 22.1 Shield connector pin diagram Figure 22.1 Shield connector pin diagram

Pin Name Shield Function Sword Connection Shared Connections
IO0-IO9, A (IO42) General purpose I/O pins See Section titled “Shield Digital I/O”
IO26-IO33 General purpose I/O pins See Section titled “Shield Digital I/O”
IO34-IO41 General purpose I/O pins See Section titled “Shield Digital I/O”
SCL I2C Clock See Section titled “Shield Digital I/O”
SDA I2C Data See Section titled “Shield Digital I/O”
IO13 General purpose I/O, SPI Clock See Section titled “Shield Digital I/O” SCLK pin of SPI Connector
IO11 General purpose I/O, SPI Data out See Section titled “Shield Digital I/O” MOSI pin of SPI Connector
IO12 General purpose I/O, SPI Data in See Section titled “Shield Digital I/O” MISO pin of SPI Connector
IO10 General purpose I/O, SPI Slave Select See Section titled “Shield Digital I/O” SS pin of SPI Connector
A0-A5 Single-Ended Analog Input See Section titled “Shield Analog I/O”
A6-A11 Differential Analog Input See Section titled “Shield Analog I/O”
V_P, V_N Dedicated Differential Analog Input See Section titled “Shield Analog I/O”
XGND XADC Analog Ground Connected to net used to drive the XADC ground reference on the FPGA (VREFN)
XVREF XADC Analog Voltage Reference Connected to 1.25 V, 25mA rail used to drive the XADC voltage reference on the FPGA (VREFP)
N/C Not Connected Not Connected
IOREF Digital I/O Voltage reference Connected to the Sword 3.3V Power Rail (See the “Power Supplies” section)
RST Reset to Shield Connected to the red “RESET” button and a Digital I/O of the FPGA. When JP2 is shorted, it is also connected to the DTR signal of the FTDI USB-UART bridge.
3V3 3.3V Power Rail Connected to the Sword 3.3V Power Rail (See the “Power Supplies” section)
5V0 5.0V Power Rail Connected to the Sword 5.0V Power Rail (See the “Power Supplies” section)
GND, G Ground Connected to the Ground plane of Sword
VIN Power Input Connected in parallel with the external power supply connector (J12).

Table 22.1. Sword Shield Pinout

22.1 Shield Digital I/O

The pins connected directly to the FPGA can be used as general purpose inputs or outputs. These pins include the I2C, SPI, and general purpose I/O pins. There are 200 Ohm series resistors between the FPGA and the digital I/O pins to help provide protection against accidental short circuits. The absolute maximum and recommended operating voltages for these pins are outlined in Table 22.1.1.

Absolute Minimum Voltage Recommended Minimum Operating Voltage Recommended Maximum Operating Voltage Absolute Maximum Voltage
Powered -0.4 V -0.2 V 3.4 V 3.75 V
Unpowered -0.4 V N/A N/A 0.55 V

Table 22.1.1. Shield Voltage Specifications

For more information on the electrical characteristics of the pins connected to the FPGA, please see the Kintex-7 datasheet from Xilinx.

The pins on the shield connector typically used for I2C signals are labeled as SCL and SDA. When using these signals to implement an I2C bus it is necessary to attach a pull-up resistor to them. On the Sword, this can be done by placing two shorting blocks horizontally across the J4 header.

22.2 Shield Analog I/O

The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5 an external circuit is used to scale down the input voltage from 3.3V. This circuit is shown in Figure 22.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Sword's GND) that is applied to any of these pins. The pins labeled A0-A5 can also be used as Digital inputs or outputs since they are also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 22.2.1).

Figure 22.2.1 Single-Ended Analog Inputs Figure 22.2.1 Single-Ended Analog Inputs

The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 22.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even numbers are connected to the positive pins of the pair and the odd numbers are connected to the negative pins (for example, A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O.

The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 22.2.2 for this pair of pins is not loaded on the Sword.

Figure 22.2.2. Differential Analog Inputs Figure 22.2.2 Differential Analog Inputs

The XADC core within the Kintex-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.