Nexys4-DDR Migration Guide: Nexys3


This guide describes how to migrate an ISE or EDK project that targeted the Nexys3 board to the Nexys4-DDR.

Step 1: Update the Project

The first step to following this guide is to upgrade the project to ISE or EDK 14.7 if it was designed in an earlier version. This is handled differently in ISE versus EDK.

ISE Projects

This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the Digilent Forum.

EDK Projects

If your design is an AXI design, Open the Project in Xilinx Platform Studio. Allow the tools to upgrade any IP that it says is safe to upgrade. If the project is too old, it is possible that the version of an IP core you have used is no longer present in 14.7. If this is the case, you may have to upgrade the project to an earlier version that still contains the core before upgrading to 14.7. For example, if your project was created in 13.3, you may need to open it up and upgrade it in 14.2, and then open it again in 14.7. If you run into a problem upgrading your project, try posting the issue on the Digilent Forum.

If your design is a PLB design, then it will need to be redesigned with equivalent AXI versions of the PLB cores. This is because Xilinx does not support the PLB bus in 7-series devices. If you still wish to use EDK, then you will need to do this from scratch: we do not have any EDK based reference designs or a base system builder package for the Nexys4-DDR. If you would like to migrate your design to Vivado, many example projects and tutorials are available on the Nexys 4 DDR Resource Center that can help you become acquainted with it.

Step 2: Target the Nexys4-DDR FPGA

Next, you need to edit your project settings so that the Artix-7 FPGA on the Nexys4-DDR is targeted. Change the device to XC7A100T, the package to CSG324, and the speed grade to 1. If using ISE, you will need to regenerate any IP cores in your design.

Step 3: Modifying the constraints

You will need to update the pin constraints of your design. Open up your UCF file and the Nexys4-DDR Master UCF file (Available here) and replace the constraints in your file with those found in the Master UCF. For example, say you have LD0 on the Nexys3 constrained as follows:

NET "myled"         LOC=U16 | IOSTANDARD=LVCMOS33;

And the Nexys4-DDR UCF has this constraint for LD0:

#NET "led<0>"         LOC=H17 | IOSTANDARD=LVCMOS33; #IO_L18P_T2_A24_15

Then you should replace the constraint in your UCF with the constraint from the Nexys4-DDR Master UCF. Then replace the NET name with the name of your top level port and uncomment it:

NET "myled"         LOC=H17 | IOSTANDARD=LVCMOS33; #IO_L18P_T2_A24_15

You will need to do this for each top level port in your design. If it is not clear what pin for a particular component on the Nexys3 corresponds to the what pin on the Nexys4-DDR, try looking for your component in the next section to see if that clears things up.

Step 4: Components that require additional changes

Some hardware changes have been made to the Nexys4-DDR design that will affect how you interact with some components. If your Nexys3 design uses any of the components below, you will need to read what changes you will have to make in order for the design to work on the Nexys4-DDR.

Instantiated FPGA Resources

Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the 7 Series Libraries Guide.

VHDCI Connector

The Nexys4-DDR no longer has a high-density/high-speed connector. You will have to remove any aspect of your design that communicates with a device over the VHDCI connector, unless you can modify the device to connect to Pmods instead. If your design requires a high-density/high-speed connector, you should consider migrating to the NexysVideo platform instead, which has a fully populated LPC FMC connector.


The Nexys4-DDR does not support DEPP or DSTM data transfers over USB anymore. If your design used one of these methods to send data to/from a host computer then it will need to be modified to communicate using a different method. Possible options include the onboard USB-UART, JTAG paired with an instantiated BSCAN primitive, and Ethernet. If your design includes a microblaze processor, then the best option is likely ethernet. Non-microblaze designs that don't require high bandwidth can use UART, which is the easiest to use. JTAG is the hardest to implement, but provides faster data rates (1MHz-~30MHz).

Parallel PCM for data storage

The Nexys4-DDR no longer has parallel PCM. You will need to modify your design to use the onboard Quad-SPI flash or an attached microSD card for data storage.


The Quad-SPI PCM has been replaced with a Quad-SPI Flash. The interface is identical, but the read/write timing is slightly different, so your design will have to account for this. The part number of the Quad-SPI flash on the Nexys4-DDR is S25FL128S.


The Nexys4-DDR no longer has CellRAM, it has been replaced by 128 MB of DDR2. If you have a non-microblaze design that used the CellRAM, then you can use the “SRAM to DDR” component as an adapter between your design and the DDR2. This component is described here. This component does not support synchronous burst accesses like the CellRAM did, so if you need high bandwidth accesses, you will need to directly instantiate the Memory Interface Generator (MIG) in your design. Files that properly configure the MIG to work with the memory on the Nexys4-DDR are available in the “Design Resources” section here.

If you have a microblaze design that used either the External Memory Controller (EMC) core or a custom Digilent made memory controller core, then you should remove it and replace it with the MIG. This will greatly increase the performance of your Microblaze system. Use the files mentioned above to properly configure the MIG.


The Nexys4-DDR UART port is now shared with the JTAG port. This will not affect your design, however you will only need to attach one micro-USB cable to your computer now.


The Nexys4-DDR has 12-bit VGA, versus the 8-bit VGA on the Nexys3. You can connect the most significant bits of the RGB data in your design to the most significant bits on the Nexys4-DDR, and then drive the leftover lower bits to zero. Another option is to update your design to generate 12-bit video data and take advantage of the additional color resolution.


The LAN8710 Ethernet PHY on the Nexys3 has been replaced with a LAN8720A on the Nexys4-DDR. This PHY uses a RMII interface instead of a MII interface, so microblaze designs will need to insert a mii_to_rmii core in between the external interface and the axi_ethernetlite core. The RMII core requires a 50 MHz reference clock that must be generated from a clock_generator core. You must also provide a 50MHz reference clock directly to the PHY that is phase shifted 45 degrees from the clock provided to the mii_to_rmii core. This accounts for the delay introduced by the mii_to_rmii core.

Step 5: Programming options

The Nexys4-DDR has different programming options than the Nexys3. Here is an overview of what has changed with the methods you can use to configure the FPGA:

JTAG Programming

JTAG programming can still be done in Adept or iMPACT, same as the Nexys3.

Onboard Flash Memory

The Nexys4-DDR has kept only the Quad-SPI flash and has done away with the Platform and parallel PCMs. You can program the Quad-SPI flash from iMPACT. The part number of the Quad-SPI flash on the Nexys4-DDR is S25FL128S. You can no longer program the Quad-SPI flash from the Adept GUI in Windows.

Attachable memory

The Nexys4-DDR can be programmed from a bitfile stored on a thumbdrive or a microSD card. Simply format the device as FAT32 and place the .bit file in the root directory (only place one bitfile on the device). Then attach the device to either the microSD connector (J1) or the USB-HOST port (J5). Finally, set the mode jumper to USB/SD, and select the desired device with JP2. Next time you powercycle the board, the FPGA will be programmed with your bitfile.

Step 6: Take advantage of new features

The Nexys4-DDR has many features you may want to take advantage of and use in your design. Here is a short list of them:

  • microSD card for high-density data storage
  • 12-bit VGA (increased from 8-bit color)
  • PWM Audio output
  • Onboard PDM Microphone
  • 3-axis SPI Accelerometer
  • IIC Temperature sensor
  • Additional pushbutton/LEDs/switches
  • 8 digit 7-segment display (increased from 4 digit)
  • 2 RGB LEDs
  • Analog input via the XADC Pmod
  • Higher density/Higher bandwidth RAM (DDR2)
  • Faster 30MHz JTAG bus for faster programming speeds (increased from 1.6MHz)
  • A wealth of new features inside the FPGA fabric

Still Stuck?

If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the Digilent Forum, and we will do our best to get your design up and running.