Using Pmod IPs


This guide will describe how to implement Digilent's Pmod interfaces in a Microblaze or Zynq design in Vivado. Digilent provides several IPs that are designed to make implementing and using a Pmod on an FPGA as straightforward as possible.

At the end of this tutorial you will have a design that uses a Digilent Pmod IP core.



  • A Digilent 7-Series FPGA Board or Zybo
  • USB Cables
  • A Digilent Pmod


  • Xilinx Vivado 2015.X
    • Vivado 2015.4 is used in this tutorial
  • Xilinx SDK
    • Same version as your Vivado installation

Board Support Files

  • Board Support Files – These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.
  • Digilent Library FilesZIPGithub
    • Extract these files to a directory you will remember


1. Create a new Microblaze/Zynq Block Design

1.1) Follow the “Getting Started with Microblaze” tutorial found on the resource center of your FPGA platform to obtain a basic Microblaze block design. If you are using a Zynq platform, follow the “Getting Started with Zynq” tutorial on your platform's resource center instead.

2. Add the Digilent Library Repository

2.1) Click Project Settings under Project Manager.

2.2) Click IP then open the Repository Manager tab. Click the Add button and select the vivado-library folder and click OK.

3. Add the Pmod to your Block Design

3.1) Click the Board tab (Highlighted in orange below)

This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.
3.2) Scroll down to the Pmod section of the board components. Double click the connector that you want to set up.

3.3) Select the Pmod IP for your specific Pmod and click OK. In this tutorial, we will choose the PmodOLEDrgb.

3.4) If your Pmod is not in the list, you can use the Pmod Bridge IP. This routes the signals to the correct pins on the Pmod Connector, and provides several interfaces that can be chosen in the re-customization menu.

4. Run Connection Automation

4.1) Click Run Connection Automation, select All Automation and click OK

4.2) The PmodOLEDrgb requires a 50MHz ext_spi_clk, so we must generate this clock from the MIG (in a Microblaze design) or from the Zynq processor(in a Zynq design).
Microblaze: Double click the mig_7series block to re-customize it. In the Xilinx Memory Interface Generator window, keep clicking Next until you see Select Additional Clocks (shown below). Click this box and select a 50MHz or less clock from the drop down list.

When finished, keep clicking Next. When you reach the pin selection screen, click Validate and then OK. Keep clicking Next. Click Accept on the license agreement screen, then continue to click Next. Once you've reached the end, click Generate to regenerate your MIG block with your additional clocks.

Zynq: Double click the ZYNQ block to re-customize it. In the menu to the left, click Clock Configuration. Open the PL Fabric Clocks drop down and check the next free FCLK_CLK and set the requested frequency to 50MHz or less. Click OK.

4.3) Connect this new clock to the ext_spi_clk input on the PmodOLEDrgb block.

5. Connect the Interrupts

5.1) If your Pmod has any Interrupts, make sure to connect them. In a Microblaze design, these signals are connected to the Concat block connected to an AXI Interrupt Controller. In a Zynq design, you must enable fabric interrupts in the Zynq re-customize menu. The correct interrupt to use is the IRQ_F2P[15:0] interrupt under Fabric Interrupts>PL-PS Interrupt Ports.

6. Validating Design and making an HDL Wrapper

6.1) Click the Regenerate Layout button to rearrange your block design.

6.2) Select Validate Design. This will check for design and connection errors.
6.3) After the design validation step we will proceed with creating a HDL System Wrapper. Click on the Sources tab and find your block design.

6.4) Right click on your block design and click Create HDL Wrapper. Let Vivado manage wrapper and auto-update and click OK.

This will create a top module in VHDL and will allow you to generate a bitstream.

7. Generating Bit File

7.1) In the top toolbar in Vivado, click Generate Bitstream. This can also be found in the Flow Navigator panel on the left, under Program and Debug.
If you haven't already saved your design, you will get a prompt to save the block design.
7.2) The bit file generation will begin. The tool will run Synthesis and Implementation. After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.

This process can take anywhere from 5 to 60 minutes depending on your computer.
7.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click Cancel.

8. Exporting Hardware Design to SDK

8.1) On the main toolbar, click File and select Export Hardware. Check the box to Include Bitstream and click OK. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.

A new file directory will be created under echo_server.SDK similar to the Vivado hardware design project name. Two other files, .sysdef and .hdf are also created. This step essentially creates a new SDK Workspace.
8.2) On the main toolbar, click File and then Launch SDK. Leave both of the dropdown menus as their default Local to Project and click OK. This will open Xilinx SDK and import your hardware.

9. Inside Xilinx SDK

9.1) The HW design specification and included IP blocks are displayed in the system.hdf file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

9.2) Within the Project Explorer tab on the left, you can see your hardware platform.

system is the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

10. Creating New Application Project in SDK

10.1) Click the New dropdown arrow and select Application Project.

Give your project a name that has no empty spaces and click Next.
10.2) Select Empty Application from the list of templates and click OK.

You will see two new folders in the Project Explorer panel.

  • Pmods which contains all the binaries, .C and .H (Header) files
  • Pmods_bsp which is the board support folder

Pmods is our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

11. Import the Example Project

11.1) Expand the design_1_wrapper_platform_0 folder. Within the drivers folder, you will find the list of Pmods that you are using in your design. Expand the PmodOLEDrgb_v1_0/examples folder and copy main.c and bitmap.h into the Pmods/src folder.

12. Programming FPGA with Bit File

12.1) Make sure that your board is turned on and connected to the host PC via both the JTAG USB port and the UART USB port.

On the top toolbar, click the Program FPGA button.
12.2) Click Program to program your FPGA with your hardware design.

13. Program the Microblaze Processor

13.1) Make sure you have your board plugged in before beginning.
13.2) Back in SDK, select your Pmods project and click the Run As… button. Select Launch on Hardware (System Debugger) and click OK.

13.3) Xilinx SDK will program your Microblaze/Zynq processor with the code in main.c