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learn:courses:unit-3:start [2019/10/28 17:22] – Andrew Holzerlearn:courses:unit-3:start [2019/10/28 17:37] – [Listing 7.2. PMP Initialization Code for LCD Interface] Arthur Brown
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 //Figure 7.17. The PMP timing diagram for the beginning, middle, and end wait periods.// //Figure 7.17. The PMP timing diagram for the beginning, middle, and end wait periods.//
  
-The minimum settings for the three PMP WAIT intervals can be determined by dividing the value for t<sub>SU</sub> on the LCD datasheet by T<sub>PB</sub>. For example, assume that the peripheral bus clock is configured for 10 MHz. The t<sub>SU</sub> specified in the KU0066U data sheet is 60 ns, resulting in interval B being equal to 0.6 T<sub>PB</sub> periods. Of course, this should be rounded up, so a proper setting is PMP_WAIT_BEG_1. The value for the interval M is computed using the value specified for t<sub>W</sub>. In this case, M+1 is equal to 2.5, and after rounding up and subtracting one, M equals 2. Thus, PMP_WAIT_MID_2 can be used. The value for interval E is 0.1, resulting in PMP_WAIT_END_1. Since \[(B+\[M+1\]+E) * T<sub>PB</sub> \] represents the minimum time to complete an LCD read or write operation, this minimum time must be greater than the LCD enable cycle time, t<sub>C</sub>, which is specified as 450 ns. For the configuration described above, \[(B+[M+1]+E) * TPB\] = \[(5) * 100 ns\] = 500 ns, thereby satisfying the LCD timing specifications. If the cycle time is too short, wait periods can be added to any segment within the allowable ranges.+The minimum settings for the three PMP WAIT intervals can be determined by dividing the value for t<sub>SU</sub> on the LCD datasheet by T<sub>PB</sub>. For example, assume that the peripheral bus clock is configured for 10 MHz. The t<sub>SU</sub> specified in the KU0066U data sheet is 60 ns, resulting in interval B being equal to 0.6 T<sub>PB</sub> periods. Of course, this should be rounded up, so a proper setting is PMP_WAIT_BEG_1. The value for the interval M is computed using the value specified for t<sub>W</sub>. In this case, M+1 is equal to 2.5, and after rounding up and subtracting one, M equals 2. Thus, PMP_WAIT_MID_2 can be used. The value for interval E is 0.1, resulting in PMP_WAIT_END_1. Since  formula (1), below, represents the minimum time to complete an LCD read or write operation, this minimum time must be greater than the LCD enable cycle time, t<sub>C</sub>, which is specified as 450 ns. For the configuration described above, formula (2), below, follows thereby satisfying the LCD timing specifications. If the cycle time is too short, wait periods can be added to any segment within the allowable ranges. 
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 +(1) $[B+(M+1)+E] * T_PB$    
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 +(2) $[B+(M+1)+E] * T_PB = (5) * 100 ns = 500 ns$ 
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 Since the PMP is clocked from the peripheral bus clock, it is likely that the PMP cycle is slower than the core CPU, which means that the PMP also has a busy flag that must be polled before writing or reading the next byte. With the PMP interrupt disabled, the only way to determine if the PMP is ready for the next read or write cycle is to poll the PMP flag. The //PMPMasterWrite// function provided in the PIC32 Peripheral Library polls the PMP flag to ensure it has been cleared prior to writing. The code for writing to the LCD using the PMP is shown in Listing 7.3. Since the PMP is clocked from the peripheral bus clock, it is likely that the PMP cycle is slower than the core CPU, which means that the PMP also has a busy flag that must be polled before writing or reading the next byte. With the PMP interrupt disabled, the only way to determine if the PMP is ready for the next read or write cycle is to poll the PMP flag. The //PMPMasterWrite// function provided in the PIC32 Peripheral Library polls the PMP flag to ensure it has been cleared prior to writing. The code for writing to the LCD using the PMP is shown in Listing 7.3.
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