Zmod ADC 1410 Low Level Controller IP Core User Guide

This user guide describes the Digilent Zmod ADC 1410 Low Level Controller Intellectual Property. This IP interfaces directly with the Zmod ADC 1410 configuring the gain and coupling select relays, writing an initial configuration to the AD9648 analog to digital converter (ADC) featured by this module, demultiplexing the data received over the ADC’s parallel interface and forwarding it to the user logic. The Zmod ADC 1410 Low Level Controller is intended to be used as a stand-alone IP (the stand alone mode) in projects that do not require processor interaction or it can be used in conjunction with the Digilent Zmod ADC1410 AXI Adapter IP that provides connectivity with the processing system.

• Initializes the hardware on the Zmod ADC 1410.
• Demultiplexes the double data rate (DDR) parallel interface featured by the Zmod ADC 1410 and exports two single data rate (SDR) channels to the user logic in the user clock domain.
• Provides the possibility of overwriting the initial ADC configuration by providing an optional upper level interface that allows indirect access to the ADC’s SPI interface.
• Performs offset and gain calibration based on coefficients specified by the user/upper level IPs.

The IP is designed to forward a 400 MHz clock to the ADC’s clock input and expects to receive data from the ADC on a 14 bit double data rate (DDR) parallel bus running at 200 MSPS. Both the Zmod’s ADC Channel1 and Channel2 data are multiplexed on this interface. The Zmod ADC1410 Low Level Controller further exports to the user logic two distinct 100 MSPS single data rate (SDR) 14 bit channels synchronized with the user clock domain. The Zmod ADC 1410 synchronization input (SYNC) signal is also generated by Zmod ADC1410 Low Level Controller in the AdcInClk clock domain (400 MHz) allowing the ADC’s sampling instant can be configured with a resolution of 2.5 ns. The latency of the data path is to be determined.

The following image shows the structure of the IP Core.

The main functionalities are divided as ADC input clock generation, SYNC generation, data capture and calibration (data path) and Zmod ADC 1410 configuration (two items related with configuration functionalities will be detailed separately: the configuration state machine and the SPI controller).

The AD9648 on the Zmod ADC 1410 requires a differential sample clock as input. The IP is designed to forward a 400 MHz which will be further divided by 4 by the ADC (option programmed in the ADC … register by the configuration state machine). The IP does not generate the clock internally, instead it requires it as an input expecting it to be generated in the top level design. The IP only instantiates the IO primitives required to generate the differential clock derived from it.

The SYNC signal allows multiple AD9648 devices to have their sample clock synchronized by resetting their internal clock dividers. An OSERDES primitive with a ratio between the divided input clock (100MHz) and the high speed clock (400MHz) of 4 is used by the IP core to generate the SYNC signal. The ExternalSyncEn parameter enables the user to control the SYNC signal through the optional ExtSync port which represents the 4 bit wide parallel input of the OSERDES primitive. The valid values that this input signal can take are “0001”, “0010”, “0100”, “1000”. If the ExtSync port is disabled, the default value of the OSERDES input will be “0001”. Since the ADC clock divider is programmed by the configuration state machine to divide the input clock by 4, the ADC sampling instant can be configured with a resolution of 2.5 ns. This feature can also be used for oversampling purposes.

The data path consists of three stages. First, each bit of the input parallel data bus is passed to an IDDR primitive used to demultiplex the DDR interleaved format exported by the ADC (Figure 2), obtaining two SDR data channels.

The following image shows the input data channel demultiplexing .

Each channel is further connected to a shallow FIFO used only to synchronize the received data with the IP core’s system clock. The final stage is represented by the calibration stage which is responsible for compensating the offset and gain errors associated with each channel and with each gain option. The output of each channel is computed based on relation (1):

$$ChxOut=Chx_{FIFO}*CoefxMult_{LH/HG}+CoefxAdd_{LG/HG}\tag{1}$$

In the previous relation, the IP core’s data output channels are labeled ChxOut, the synchronization stage outputs are labeled CHxFIFO while CoefxMultLG/HG and CoefxAddLG/HG represent the gain and offset calibration coefficients. The multiplicative and additive coefficients are passed by the upper layer IP Core if the Zmod ADC 1410 Low Level controller is used in a processor system (the external calibration interface is enabled) or they can be passed as IP core parameters otherwise. The user should run the to be determined executable to obtain the calibration parameters if the IP core is not connected to the processing system.

The IP core provides the choice of selecting the Zmod ADC 1410 coupling and gain options statically or dynamically. For static configuration, the ExtRelayConfigEn needs to be set as “false” and the relay configuration parameters (See Table x) need to be configured in the IP core GUI. For dynamic relay control, the ExtRelayConfigEn needs to be set as “true” and the configuration state machine will constantly monitor the external relay configuration ports and will reconfigure the AC DC coupling relays or the gain relays in response to user request.

The configuration state machine first configures the AC DC coupling and gain select relays according to the values specified in the relay configuration parameters or on the external relay configuration ports as explained in AC DC Coupling and Gain Select Relay Control section. The next step is to send a predefined list of SPI commands to the Zmods’s ADC, performing the ADC initialization. Once the initialization is complete, the state machine enters the idle state where it monitors if there is any valid data on the upper level SPI command interface or any changes on the external relay configuration ports. After reconfiguring the relays or after executing the requested SPI transfers the state machine passes the received SPI data (for read commands) and returns to the idle state. The initial configuration command sequence is listed below. After configuring each register, the register data is read back and checked against the expected value in order to determine any SPI transaction error.

1. SPI Port config register: Soft Reset (Address: 00h; Data: 3C)
2. Chip ID Register: Check ID (Read, Address: 01h; Data: -)
3. Device Index Register: Select CHA & CHB (Address: 05h; Data: 03h)
4. Power modes Register: digital reset (Address: 08h; Data: 03h)
5. Device Index Register: Select CHA (Address: 05h; Data: 01h)
6. Output mode register: Output port logic type → CMOS 1.8V, Output interleave enable, disable port (port A), Output invert disable, Gray code (Address: 14h; Data: 32h)
7. Device Index Register: Select CHB (Address: 05h; Data: 02h)
8. Output mode register: Output port logic type → CMOS 1.8V, Output interleave enable, Enable port (port B), Output invert disable, Gray code (Address: 14h; Data: 22h)
9. Device Index Register: Select None (Address: 05h; Data: 00h)
10. Clock Divide register: Divide by 4 (Address: 0Bh; Data: 03h)
11. Clock Phase Control register: Invert DCO (Address: 16h; Data: 80h)
12. Overrange Control register: disable overage output (Address: 2Ah; Data: 00h)
13. Output Adjust register: DCO and DATA 2X drive strength (Address: 15h; Data: 00h)
14. Output delay register: 0.56ns delay added to DCO (Address: 17h; Data: 80h);
15. Sync control register: SYNC enable, continuous SYNC (Address: 3Ah; Data: 02h)
16. Device Index Register: Select CHA & CHB (Address: 05h; Data: 03h)
17. Power modes: Normal operation (Address: 08h; Data: 00h)
18. Device Index Register: Select None (Address: 05h; Data: 00h)

The SPI controller is designed to carry out basic register access over the AD9648’s SPI interface. Only single byte data transfers are currently supported. More details about the AD9648’s SPI interface can be found in [Reference 3]. The SPI controller’s ports are described below.

The IP is divided in three clock domains:

1. The system clock domain (100 MHz), which clocks the configuration state machine, the data FIFOs read ports, the calibration logic and the Zmod ADC 1410 SPI interface.
2. The ADC input clock domain (400 MHz), which is used to clock the primitives responsible with generating the SYNC signal and with passing the ADC_InClk input clock to the Zmod ADC 1410.
3. The DCO clock domain, which is used to clock the IDDR primitives that demultiplex the ADC incoming DDR data bus and the write pots of the data FIFOs.

The IP does not constrain the clocks it requires as inputs, therefore clocks need to be constrained in the top-level design either manually or by relying on the auto-derived constraints, if using clock modifying blocks. For more information see [4].

The IP, through its customizable parameters (ExtRelayConfigEn , ExtCalibEn, ExtCmdInterfaceEn, ExtSyncEn), enables the user to opt for a more basic design with minimal external ports or a more configurable but also more complex design with several ports that enable dynamic configuration of several hardware features. When using the IP Core with the Zmod ADC 1410 AXI adapter, the hardware configuration features are expected to be controlled by the processing system, so all interfaces should be enabled and connected to the upper layer IP Core.

The following documents provide additional information on the subjects discussed:

1. Xilinx Inc., UG471: 7 Series FPGAs SelectIO Resources, v1.4, May 13, 2014.
2. Xilinx Inc., UG472: 7 Series FPGAs Clocking Resources, v1.6, October 2, 2012
3. Analog Devices, AD9646 Datasheet, Rev C.
4. Xilinx Inc., UG903: Using Constraints, v2014.3, October 31, 2014