System Design Flow in Vivado
This workshop serves as an introduction into FPGA design flow using Vivado. It is split into six labs that explore various tools and processes in FPGA design flow. The labs are as follows:
- Lab1 has you create a simple HDL design where you'll learn how to simulate the design.
- In Lab2 you'll learn the synthesis process and the effects that take place as a result of changing the synthesis settings.
- Lab3 builds off what you've done in Lab2 and focuses on timing analysis. You'll verify your design on your hardware at the conclusion of the lab.
- Lab4 introduces you to the IP Catolog. You'll instantiate a generated clock core for use in your design. Using the IP Integrator, you'll also learn how to generate a FIFO core for your design.
- You'll learn how to create a project using the I/O Planning tools in Lab5. Once you've defined the pin locations and have exported the project, you'll perform timing analysis on the design.
- Lab6 finsihes the workshop by teaching you how to debug your design using the Mark Debug feature and the Integrated Logic Analizer (ILA) core found in the IP Catalog.
After completing this workshop's series of labs, you should be able to:
- Understand the FPGA design flow in Vivado to create and debug HDL designs.
- Identify design bottlenecks and use the FPGA architecture features and synthesis options to improve performance.
- Perform design verification through simulation, on-chip verification using the ILA or configuration of the FPGA.
- Experience with digital logic and FPGA design
- Familiarity with Vivado Design Software
- Digilent Nexys Video, Nexys 4 DDR, or Basys 3 FPGA Board
- Micro USB Cable
- Used for UART communications JTAG programming.
- Vivado Design Suite 2015.2
1. Starting the Workshop
1.1) Open the Xilinx University Program Workshops page in a new tab and click the FPGA Design Flow using Vivado link.
1.3) Follow the labs as they guide you through FPGA design flow.