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vivado:library [2020/05/15 20:54]
Monica Ignat [IPcores]
vivado:library [2020/05/15 20:55] (current)
Monica Ignat [IPcores]
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     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​hls_saturation_enhance_1_0/​doc/​HLS_Saturation_Enhancement_v1_0.pdf|documentation]]     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​hls_saturation_enhance_1_0|hls_saturation_enhance_1_0]] - This IP interfaces to both Axi-Lite and Axi-Stream in order to process a video stream and control the resolution and the saturation factor. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​hls_saturation_enhance_1_0/​doc/​HLS_Saturation_Enhancement_v1_0.pdf|documentation]]
     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​rgb2dpvid_v1_0/​docs/​rgb2dpvid_v1_0.pdf|documentation]]     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​rgb2dpvid_v1_0|rgb2dpvid_v1_0]] - This IP interfaces to an RGB video data bus at its inputs and outputs a video data interface of the Xilinx LogiCORE IP DisplayPort. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​rgb2dpvid_v1_0/​docs/​rgb2dpvid_v1_0.pdf|documentation]]
-    * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. More details about its functionality can be found in the[[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​rgb2dvi/​docs/​rgb2dvi.pdf|documentation]]+    * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​rgb2dvi|rgb2dvi]] - This IP interfaces directly to raw transition-minimized differential signaling (TMDS) clock and data channel outputs as defined in DVI 1.0 specs for Source devices. It encodes 24-bit RGB video data along with the pixel clock and synchronization signals. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​rgb2dvi/​docs/​rgb2dvi.pdf|documentation]]
     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​rgb2vga_v1_0|rgb2vga_v1_0]] - It accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​rgb2vga_v1_0/​docs/​rgb2vga_v1_0.pdf|documentation]]     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​rgb2vga_v1_0|rgb2vga_v1_0]] - It accepts a Xilinx vid_io input and outputs an independently customizable color depth, properly blanked RGB pixel bus to connect to a VGA DAC. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​rgb2vga_v1_0/​docs/​rgb2vga_v1_0.pdf|documentation]]
     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​usb2device_v1_0|usb2device_v1_0]] - It provides communication between an AXI Microblaze system and a USB 2.0 Host. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​usb2device_v1_0/​docs/​USB_Device.docx|documentation]]     * [[https://​github.com/​Digilent/​vivado-library/​tree/​master/​ip/​usb2device_v1_0|usb2device_v1_0]] - It provides communication between an AXI Microblaze system and a USB 2.0 Host. More details about its functionality can be found in the [[https://​github.com/​Digilent/​vivado-library/​blob/​master/​ip/​usb2device_v1_0/​docs/​USB_Device.docx|documentation]]