Getting Started with Zynq and the Vivado IP Integrator

1.1

With Vivado freshly opened, click Create New Project.

1.2

The first page of this wizard summarizes the steps involved in creating a project. Click Next.

1.3

The first step is to set the name of the project. Vivado will use this name when generating its folder structure.

Click Next to continue.

1.4

At the Select Project Type screen, choose RTL Project and check the Do not specify sources at this time box. Advanced users may want to use the other options on this screen, but they will not be covered in this guide.

Click Next to continue.

1.5

This screen selects the part targeted by the project. If you haven't yet installed Digilent's Board Files, return to the prerequisites section of this guide and follow the link to that tutorial, Vivado will then need to be restarted to load these files properly. Select the Boards tab, then find and select your board from the list. Click Next.

1.6

This screen summarizes selections chosen in the previous screens. Click Next to finish opening the new project.

2.1

A more complete run-down of the standard Vivado work-flow can be found in Digilent's Getting Started with Vivado tutorial. This guide will be exclusively using the IP Integrator tool, which can be opened from the Flow Navigator on the right side of the window. Expand the IP Integrator tab and select Create Block Design.

2.2

In the dialog box, give the block design a name. The directory location is where the block design will be stored, this can be changed, but it is recommended to leave it as <Local to Project>. Make sure that Specify source set is set to Design Sources.

Click OK to create the block design and open IPI.

3.1

The Sources tab, highlighted in orange in the image to the right, contains several sub-tabs, of these, Hierarchy and IP Sources are the most immediately useful.

The Hierarchy sub-tab shows the set of sources that exist in the project. These are split up into three groups, Design Sources contains the block design, and beneath that, sources for all of the IP cores or other files that are included in the block design. The Constraints sub-tab contains Xilinx Design Constraint (XDC) files that have been added to the project. XDC files can be used to constrain ports that have been omitted from the board file.

The IP Sources sub-tab shows the files generated when a new IP core has been added to the block design. Some annoying errors can be solved by right clicking on the block design in this screen and selecting Reset Output Products followed by Generate Output Products.

3.2

When the Design tab is selected, a list of all input and output ports, IP core ports, and connections between IP cores is shown. Selecting an entry in this list will highlight that object in the block design diagram.

3.3

The Signals tab allows the user to view lists of all clock and reset signals in the block design. As before, selecting an entry in either of these lists will highlight that signal in the block design diagram. This tool can be useful for figuring out where data crosses clock domains in a more complicated design.

3.4

The Board tab displays all of the external connections that Digilent has provided as part of the board file selected as part of creating the project. This tool makes connecting these ports to a design extremely straightforward. The process of connecting one of these ports will be gone through later in this guide.

3.5

The Properties pane, found below the tabbed pane described above, shows the properties of the currently selected object. This pane is typically used to quickly view the clock frequency of a selected clock pin, or to change the name of an IP core or port.

3.6

Most of the upper right of the Vivado window is taken up by the Diagram pane. This pane displays a graphical rendition of the current block design. Many of the buttons in the toolbar to the left side of this pane will be described in Step 4 of this guide.

3.7

The Address Editor tab, contained in the same pane as the Diagram, describes the memory addresses that the processor can find each installed AXI peripheral at. Changing values in this pane is not recommended, except for advanced users. Errors in the block design validation process that refer to unmapped peripherals can be solved by right clicking anywhere in this pane and selecting Auto-Assign Address.

3.8

The first tab of the pane at the bottom of the window is the TCL Console. This tool displays the scripted commands that Vivado is running whenever a change is made in the graphical interface. Scripts can be created to be run using this tool through the use of the 'source' command.

3.9

The Messages tab displays Error, Warning, Info, and Status messages created when Vivado takes different actions. These messages can also be found in the TCL Console but are presented in a relatively easy to navigate format.

3.10

The Reports tab contains a list of different reports that Vivado generates as part of the process of generating a bitstream.

3.11

By selecting Tools → Reports → Report IP Status in the toolbar at the top of the Vivado window, another tab will be added to the bottom-most pane - though this will not do anything until an IP is added to the design. This IP Status tab displays the versions and target devices of each IP core added to the project. If an IP is not Up-to-date, clicking the Upgrade All button will reload the IP with the most recent version, or make any updates needed to make the IP work in the version of Vivado being used.

4.1

The core of most IPI designs for a Zynq board is the Zynq block. Click the Add IP () button, then search for and double click on Zynq.

The block that is added represents the Zynq ARM processor and its available connections to other hardware on the Zynq chip, including the FPGA.

4.2

Before doing anything else, select Run Block Automation in the green tab at the top of the block design Diagram pane. This button launches a dialog that will add several important required connections for the processor.

4.3

The Options box shows what will be done when OK is clicked. FIXED_IO and DDR connections will be made external automatically. FIXED_IO represents all of the on-chip peripherals that can be enabled when configuring the Zynq block (more on this later), while the DDR connection represents the processor's connection to the on-board memory.

Make sure that Apply Board Preset is checked, so that various important settings like DDR timings will be imported from the selected target board file. Applying these settings manually is extremely tedious and easy to get wrong.

Cross Trigger In/Out are outside of the scope of this guide, so leave them Disabled.

4.4

Click OK to have Vivado add these connections and apply the preset. When this process is complete, the FIXED_IO and DDR connections can be seen in the block design, represented as ports directly connected to the Zynq block. Several other changes to the set of ports to and from the Zynq block can be seen.

5.2

The page that is open when the Re-Customize dialog is launched for the Zynq block is called Zynq Block Design. This page displays the hardware used by the Zynq chip. Note the I/O Peripherals block, the check-marks display what peripherals are currently enabled. All of the information shown in this screen is available in lists in the other pages.

5.3

The PS-PL Configuration page allows the user to customize how the processor will communicate with the FPGA. There are several settings of particular note here.

• The UART baud rate settings found in the General drop-down are used to change the baud rate that the Zynq communicates with a computer serial port at.
• GP/HP Slave AXI Interfaces (General Purpose / High Performance) are used when an AXI peripheral requires control over a memory interface, this can be seen in Digilent's HDMI and Audio DMA demo projects.

5.4

The Peripheral I/O Pins page allows the user to enable or disable a large number of different hardware peripherals that cannot be controlled directly from the FPGA. As an example, enabling GPIO MIO allows the user to control LED 4 (LD4/MIO7) on the Zybo board.

5.5

The MIO Configuration page shares much of its information with Peripheral I/O Pins, and allows the user to view this in a list, rather than the graphical table format.

5.6

The Clock Configuration page contains important settings that allow the user to provide additional clocks at different speeds to the FPGA, as well as tweaking the clock frequencies of several IO Peripherals. Take note of the PL Fabric Clocks drop-down, checking a box for one of FCLK_CLK1-3 will provide an additional clock output from the Zynq block, at or near the provided Requested Frequency.

5.7

The DDR Configuration page contains a large number of settings about the DDR chip connected to the Zynq chip. This page alone is the reason to use the board preset brought in from Digilent's board file. Changing these settings is not recommended.

5.8

The Interrupts page is another extremely useful one. To use any interrupts with the FPGA, the Fabric Interrupts checkbox must be checked. Many AXI IP cores can be configured to generate an interrupt on some trigger, for instance AXI GPIO cores can be set up to trigger an interrupt whenever an input changes. Checking the IRQ_F2P box in the PL-PS Interrupt Ports drop-down creates a new input port on the Zynq block which can be connected to up to sixteen individual interrupt pins via a Concat (concatenation) IP core. To use interrupts, the 'xscugic' driver for the generic interrupt controller found in the Zynq hardware must be used.

Additionally, interrupts generated by hardware peripherals connected using the Peripheral I/O Pins or MIO Configuration pages can be provided to the FPGA using the fields in the PS-PL Interrupt Ports drop-down.

6.1

In the Board tab to the left of the diagram pane, right click on RGB LEDs and select Connect Board Component. If the board does not have RGB LEDs, use the normal LEDs instead.

6.2

This launches a dialog that provides the different IP blocks that this port can be connected to. Select AXI GPIO.

6.3

This will place a general purpose input/output (GPIO) controller into the block design. Required configuration settings for the size of the GPIO channel will already be done, but additional options, like creating an interrupt port, or adding a second channel can be enabled by configuring the IP. The IP can be customized by double clicking on it, or by selecting it and clicking the Customize Block button ().

6.4

Since an AXI GPIO controller with a free channel - each block can control up to two different peripherals - already exists, when making a connection with the User Buttons port, the option of connecting the port to the second channel of axi_gpio_0 will be available. Select this option from the menu, then continue.

7.1

At this point, the green bar at the top of the screen will have reappeared, this time saying Run Connection Automation. Click this.

7.2

Make sure that the axi_gpio_0 block is checked in the menu to the left. Several options are present here, including the a drop-down to select the clock that the AXI Interface will run off of - keep this field as Auto to let Vivado pick.

Click Finish to generate the AXI connection and its related blocks.

At this point the block diagram may have become very messy, the Regenerate Layout () button can be clicked to have Vivado place the blocks and signals in more sensible locations.

8.1

At this point, a complete design has been created. Click the Validate Design button () to have Vivado confirm that everything looks good.

Click OK to continue.

8.2

The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the Sources tab in the pane to the left of the Block Design pane - this pane likely has the Board tab currently selected.

In the right-click menu, select Create HDL Wrapper. In the confirmation dialog that pops up, make sure that Let Vivado manage wrapper and auto-update is selected in the options list. If manual changes need to be made to the wrapper file, the other option here can be selected, but it is not recommended except for advanced users. Click OK to have Vivado finish making the wrapper file.

8.3

With a validated design and a top module, a bitstream can now be generated. The Getting Started with Vivado guide explains this process in a little more detail, but for now, click the Generate Bitstream button in the Flow Navigator.

8.4

The Launch Runs dialog that pops up has several options to choose between. Select Launch runs on local host to actually generate the bitstream now. The other option is to Generate scripts only, which will not generate a bitstream, but rather the scripts required to generate the bitstream on a different machine. The Number of jobs field allows the user to change how much of the resources of the computer Vivado is running on will be used. This process can take some time for complex designs, so it is recommended to devote as much of the resources as possible (typically by selecting '8').

8.5

In the next dialog, No Implementation Results Available, Vivado will ask whether to run Synthesis and Implementation. These steps are required to generate a bitstream, so click Yes.

8.6

Once the bitstream is generated, which may take a little while, Vivado will ask what to do next. None of the available options are required for this guide, so click Cancel.

9.1

In the File drop-down, select Export then Export to SDK.

9.2

Make sure that the Include Bitstream box is checked, so that the FPGA can be programmed from Vivado SDK. The Export Location is <Local To Project> by default. This means that Vivado will create a new directory in the project directory called '<project name>.sdk' where the hardware handoff file - named '<HDL wrapper name>.hdf' - can be found. If a different location is chosen for the hardware handoff file, make sure to remember where it is.

Click OK to continue.

9.3

Just below Export in the File drop-down, select Launch SDK.

9.4

The dialog that pops up will tell Vivado where to find the exported files, as well as where to create the SDK workspace. Make sure to set Exported Location to the location chosen earlier. The Workspace field is <Local To Project> by default. This means that Vivado will use a directory in the project directory called '<project name>.sdk' to store the sources and projects created in Vivado SDK. If this directory does not exist, it will be created. This location can be changed if somewhere else is desired, but it is recommended to leave it as is.

Click OK to continue.

10.1

Vivado SDK will now launch, and will import the hardware definition, creating a workspace containing only a hw_platform project. This project contains the files exported from Vivado. There are only a few relevant panes to this guide.

• The Project Explorer, found to the left hand side of the window, displays all projects imported into the workspace, each of which can be expanded to view the sources, scripts, and other files that they contain.
• The File View, directly in the center of the window, displays currently opened files. Upon launch of SDK, an overview of the hardware platform exported from Vivado is displayed. Note the AXI GPIO cell contained in the Address Map, and the corresponding entry in the list of IP blocks.

10.2

In order to create a project to store C source code, click File in the top toolbar, followed by New > Application Project.

10.3

In the New Project dialog, give the project a name, and make sure that C is selected as the Language in the Target Software box.

Click Next to continue.

10.4

From the list of Available Templates, select Empty Application, then click Finish.

10.5

Expand the newly created project - not its board support package - then expand the 'src' folder. Right-click on the 'src' folder and select New > Source File from the menu.

10.6

Name the new source file 'main.c', then click Finish.

10.7

The new main file will now open in the file view pane. Copy-Paste the code to the right into this file, then hit Ctrl-S to save the file and build the project.

#include "xgpio.h"
#include "xparameters.h"
 
int main() {
    XGpio gpio;
    u32 button_data;
 
    // look up the settings for the AXI GPIO IP core and initialize a driver for it
    XGpio_Initialize(&gpio, XPAR_AXI_GPIO_0_DEVICE_ID);
 
    // set LED channel (1) tristates to all output
    XGpio_SetDataDirection(&gpio, 1, 0b0000);
    //set Button channel (2) tristates to all input
    XGpio_SetDataDirection(&gpio, 2, 0b1111);
 
    while (1) {
    	//capture button data
    	button_data = XGpio_DiscreteRead(&gpio, 2);
 
    	//if any button is pressed, set all LED pins high, else turn LEDs off
    	if (button_data != 0) {
    		XGpio_DiscreteWrite(&gpio, 1, 0b1111);
    	}
    	else {
    		XGpio_DiscreteWrite(&gpio, 1, 0b0000);
    	}
    }
}

11.1

From the top toolbar, select Xilinx Tools, then Program FPGA.

11.2

Leave all of the settings in the Program FPGA dialog as they are, then click Program. This only programs the FPGA, not the processor, so that is next.

11.3

Right click on the application project in the Project Explorer, then select Run As > Launch on Hardware (System Debugger).