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vivado:getting_started_tutorial:start [2016/09/06 19:02] (current)
James Colvin created
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 +====== Getting Started with Vivado ======
 +-----
  
 +===== Prerequisites =====
 +Prior to starting this guide make sure to install Vivado. For more information see our [[learn:​software:​tutorials:​vivado-install-guide:​|Installing Vivado]] guide.
 +===== Introduction =====
 +
 +{{ :​vivado:​getting_started:​vivado_home.png?​direct&​500 |The Vivado Start Page}}
 +
 +The goal of this guide is to familiarize the reader with the Vivado tools through the hello world of hardware, blinking an LED.
 +
 +This guide was created using Vivado 2016.2.
 +==== 1. Starting Vivado ====
 +<WRAP group>
 +<WRAP column half>
 +**Windows**\\
 +Open the start menu and go to //All Programs->​Xilinx Design Tools->​Vivado <​version>​->​Vivado <​version>//​
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​windows_start_vivado.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +**Linux**\\
 +Open a Terminal and run
 +<​code>​source <​install_path>/​Vivado/<​version>/​settings64.sh && vivado</​code>​
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​linux_start_vivado.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +==== 2. The Start Page ====
 +This is the screen that displays after Vivado starts up. The buttons are described below using the image as a guide.
 +
 +{{ :​vivado:​getting_started:​vivado_home_outlined.png?​direct&​500 |}}
 +
 +== 1. Create New Project ==
 +
 +This button will open the New Project wizard. This wizard steps the user through creating a new project. The wizard is stepped through in section 3.
 +
 +== 2. Open Project ==
 +
 +This button will open a file browser. Navigate to the desired XPR file and click //Open// to open the project in Vivado.
 +
 +== 3. Open Example Project ==
 +
 +This will guide the user through creating a new project based on an example project. These projects will not work on all devices.
 +
 +== 4. Open Hardware Manager ==
 +
 +This will open the Hardware Manager without an associated project. If connecting to and programming a device is all that is required by the user this is the button to use.
 +==== 3. Creating a New Project ====
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.1 ===
 +From the start page, select the //Create New Project// button to start the New Project Wizard.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​create_new_project_button.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.2 ===
 +The text in the dialog describes the steps that will be taken to create a project. Click //Next// to continue to the first step.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​new_project.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.3 ===
 +The first step is to set the name of the project. Vivado will use this name when generating its folder structure.
 +
 +<WRAP center round important>​
 +Important: Do NOT use spaces in your project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>​CamelCase]].
 +</​WRAP>​
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​project_name.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.4 ===
 +Now that the project has a name and a place to save important files we need to create the necessary source files. To add a Verilog or VHDL file click the create file button.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​add_sources.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.5 ===
 +This will open the //Create Source File// dialog, shown below. This dialog has three options for the new file. The first is the type of file. This allows for selecting between different HDL file types, Verilog, VHDL, Verilog Header, and SystemVerilog. The final type available is the Memory File option. This is used for memory device initialization,​ most of the time this can be ignored.
 +
 +The second box is for the file name. Enter the name for the file to create. Including the file extension is optional, Vivado will add one based on the file type selected. The final option is where to store the file. Most of the time this can be left as //<Local to Project>//​.
 +
 +<WRAP center round important>​
 +Important: Do NOT use spaces in your file name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>​CamelCase]].
 +</​WRAP>​
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​create_source_file.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.6 ===
 +It is also possible to import source files into the project. In the //Add Sources// dialog click the //Add Files// button and navigate to the source file to import into the project. Unless there is reason not to, make sure that the //Copy sources into project// check box is checked to make a copy of the source file local to the project. Since the file is copied, any changes made to the file inside one project do not affect the original file.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​import_sources.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.7 ===
 +After adding the HDL files and clicking //Next// in the main dialog, the next dialog is displayed. This dialog is for adding IP to the project. This is used in more advanced designs and is outside the scope of this guide. Click //Next//.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​add_existing_ip.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.8 ===
 +The next section is for adding a constraints file. Constraints files control how signals are routed, define clocks, and define timing constraints. Click the //Create File// button to open the //Create Constraints File// dialog.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​add_constraints.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.9 ===
 +Again the dialog presents three options. the file name and file location have the same properties as the ones in the //Create Source File// dialog. What is different is the file types that can be created. The only option available is XDC which stands for Xilinx Design Constraints. This file will define clocking, pin mapping, and timing restrictions.
 +
 +<WRAP center round important>​
 +Important: Do NOT use spaces in your file name. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>​CamelCase]].
 +</​WRAP>​
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​create_constraints_file.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP column half>
 +=== 3.10 ===
 +Now that the necessary files have been created it is time to choose the target device. There are two ways to choose a target. The first is from the actual on board component and the second is from installing the appropriate board files and picking a board.
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +== 3.10.1 ==
 +To pick a target from the on board component find the part number for the IC and find it in the selection list. There are two places to find a part number for our boards. The first is to look at the actual component on the board and try to discern the writing. The other is to look on the [[reference:​programmable-logic:​|reference page]] for the target board.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​default_part_-_parts.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +== 3.10.2 ==
 +To pick a target from the boards list, install the [[reference:​software:​vivado:​board-files#​installation|board files]] prior to creating a new project. Then select the board to use as a target from the list.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​default_part_-_boards.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.11 ==
 +The next section gives a summary of the options selected throughout the wizard. Verify that the information looks correct and click //Finish//.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​new_project_summary.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +=== 3.12 ===
 +Since new source files were created, Vivado will now show a new dialog box for defining a module for each new source file that it was told to create. Here the inputs and outputs of a module can be defined.
 +
 +Each section can be interpreted as follows:
 +
 +
 +^ Field      ^ Description ​                                     ^ Example ​   ^
 +^ Port Name  | The name to give the new port                    | //​leds// ​  |
 +^ Direction ​ | Is the port an input, output, or bi-directional ​ | //output// |
 +^ Bus        | Is the port a bus/​multiple bits?                 | //x//      |
 +^ MSB        | What is the Most Significant Bit?                | //7//      |
 +^ LSB        | What is the Least Significant Bit?               | //0//      |
 +
 +Fill out the port definitions for clk and led as shown then click //OK//.
 +</​WRAP>​
 +<WRAP column half>
 + {{ :​vivado:​getting_started:​define_module.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +==== 4. The Flow Navigator ====
 +<WRAP group>
 +<WRAP column half>
 +The Flow Navigator is the most important pane to know. It is how a user navigates between different Vivado tools.
 +
 +The Navigator is broken into seven sections:
 +  * Project Manager
 +    * Allows for quick access to project settings, adding sources, language templates, and the IP catalog
 +  * IP Integrator
 +    * Tools for creating Block Designs
 +  * Simulator
 +    * Allows a developer to verify the output prior to programming their device
 +  * RTL Analysis
 +    * lets the developer see how the tools are interpreting their code
 +  * Synthesis
 +    * Gives access to Synthesis settings and post-synthesis reports
 +  * Implementation
 +    * Gives access to Implementation settings and post-implementation reports
 +  * Program and Debug
 +    * Access to settings for bitstream generation and the Hardware Manager
 +</​WRAP>​
 +<WRAP column half>
 +{{ vivado:​getting_started:​flownav.png?​direct&​200 |}}
 +
 +</​WRAP>​
 +</​WRAP>​
 +==== 5. The Project Manager ====
 +
 +<WRAP group>
 +<WRAP column half>
 +This tool is where most development will occur and is the initial tool open after creating a new project.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man.png?​direct&​600 |}}
 +
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The Project Manager consists of four panes, Sources, Properties, Results, and the Workspace.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_outlined.png?​direct&​600 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The Sources pane contains the project hierarchy and is used for opening up files. The folder structure is organized such that the HDL files are kept under the //Design Sources// folder, constraints are kept under the //​Constraints//​ folder, and simulation files are kept under the //​Simulation Sources// folder. Files can be opened in the Workspace by double-clicking on the corresponding entry in the Sources pane. Sources can also be added by either right clicking the folder to add the file to and selecting //Add Sources// or by clicking the //Add Sources// button ({{:​vivado:​getting_started:​add_sources_btn.png?​nolink}}).
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_sources_pane.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The Properties pane allows for viewing and editing of file properties. When a file is selected in the Sources pane its properties are shown in here. This pane can usually be ignored.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_props_pane.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The Results pane consists of several different useful tools for debugging a project. The most important one to know is the Messages tool. This tool parses the Tcl console for errors, warnings, and other important information and displays it in an informative way.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_results_msgs.png?​direct&​700 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The Tcl console is a tool that allows for running commands directly without the use of the main user interface. Some messages may direct to the Tcl console for more information regarding an error.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_results_tcl_con.png?​direct&​700 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The Reports tool is useful for quickly jumping to any one of the many reports that Vivado generates on a design. These reports include power, timing, and utilization just to name a few.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_results_reports.png?​direct&​700 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The Log displays the output from the latest Synthesis, Implementation,​ and Simulation runs. Digging into this is not necessary as the reports and messages view store the information in the log in a more readable format.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_results_log.png?​direct&​700 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The last tool is the Design Runs. Using this tool run settings can be edited and new runs can be created. This tool is useful when targeting multiple devices with the same design.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_results_runs.png?​direct&​700 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The most important pane in the Project Manager is the Workspace. The Workspace is where reports are opened for viewing and HDL/​constraints files are opened for editing. Initially the Workspace displays the Project Summary which show some basic information from some of the reports.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​proj_man_ws.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +==== 6. Writing HDL and Constraints ====
 +
 +<WRAP group>
 +<WRAP column half>
 +To actually get the board to blink an LED, code needs to be written in both the Verilog and the constraints files. Opening up the Verilog file (top.v in this guide) this window should open in the workspace area.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​src_init.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +Between lines 26 and 27 add the following code:
 +
 +<code verilog>
 +reg [24:0] count = 0;
 +
 +assign led = count[24];
 +
 +always @ (posedge(clk)) count <= count + 1;
 +</​code>​
 +
 +If the Genesys 2, NetFPGA-1G-CML,​ or NetFPGA-SUME is being targeted, clear the contents of the whole file and replace it with the following:
 +
 +<code verilog>
 +module top(
 +    input clk_p,
 +    input clk_n,
 +    output led
 +    );
 +    ​
 +    wire clk;
 +    ​
 +    IBUFGDS #(
 +    ​
 +    ) clk_inst (
 +        .O(clk),
 +        .I(clk_p),
 +        .IB(clk_n)
 +    );
 +    ​
 +    reg [25:0] count = 0;
 +
 +    assign led = count[25];
 +
 +    always @ (posedge(clk)) count <= count + 1;
 +
 +endmodule
 +</​code>​
 +
 +This is different because those boards have a input clock that uses differential logic. If you want to know more read this article on [[wp>​low-voltage differential signalling]].
 +
 +<WRAP group>
 +<WRAP column half>
 +Once added the source file will look like this:
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​src_final.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +Now open the XDC file. At the moment it is empty so paste in the code below depending on the target board.
 +
 +^  Constraint File Source Code                     ||
 +^ Board                         ^ Constraint Code   ^
 +| Arty                          | <​code>​
 +set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 +set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +| Basys 3                       | <​code>​
 +set_property -dict { PACKAGE_PIN W5   ​IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 +set_property -dict { PACKAGE_PIN U16  IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +| CmodA7 ​                       | <​code>​
 +set_property -dict { PACKAGE_PIN L17   ​IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports clk]
 +set_property -dict { PACKAGE_PIN A17   ​IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +| Genesys 2                     | <​code>​
 +set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS} [get_ports clk_n]
 +set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS} [get_ports clk_p]
 +    create_clock -period 5.000 -name sys_clk_pin -waveform {0.000 2.500} -add [get_ports clk_p]
 +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports led]
 +</​code> ​                                            |
 +| Nexys 4                       | <​code>​
 +set_property -dict { PACKAGE_PIN E3   ​IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 +set_property -dict { PACKAGE_PIN T8   ​IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +| Nexys 4 DDR                   | <​code>​
 +set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 +set_property -dict { PACKAGE_PIN H17   ​IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +| Nexys Video                   | <​code>​
 +set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 +set_property -dict { PACKAGE_PIN T14   ​IOSTANDARD LVCMOS25 } [get_ports led]
 +</​code> ​                                            |
 +| NetFPGA-1G-CML ​               | <​code>​
 +set_property -dict { PACKAGE_PIN AA2   ​IOSTANDARD LVDS     } [get_ports clk_n]
 +set_property -dict { PACKAGE_PIN AA3   ​IOSTANDARD LVDS     } [get_ports clk_p]
 +    create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk_n]
 +set_property -dict { PACKAGE_PIN E17   ​IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +| NetFPGA-SUME ​                 | <​code>​
 +set_property -dict { PACKAGE_PIN G18   ​IOSTANDARD LVDS     } [get_ports clk_n]
 +set_property -dict { PACKAGE_PIN H19   ​IOSTANDARD LVDS     } [get_ports clk_p]
 +    create_clock -add -name sys_clk_pin -period 5.00 -waveform {0 2.5} [get_ports clk_n]
 +set_property -dict { PACKAGE_PIN AR22  IOSTANDARD LVCMOS15 } [get_ports led]
 +</​code> ​                                            |
 +| ZedBoard ​                     | <​code>​
 +set_property -dict { PACKAGE_PIN Y9    IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 +set_property -dict { PACKAGE_PIN T22   ​IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +| Zybo                          | <​code>​
 +set_property -dict { PACKAGE_PIN L16   ​IOSTANDARD LVCMOS33 } [get_ports clk]
 +    create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports clk]
 +set_property -dict { PACKAGE_PIN M14   ​IOSTANDARD LVCMOS33 } [get_ports led]
 +</​code> ​                                            |
 +
 +Once that is done the code is ready to be "​compiled."​
 +
 +==== 8. Synthesis, Implementation,​ and Bitstream Generation ====
 +
 +In order to create a file that can be used to program the target the "​compilation-pipeline"​ needs to be done.
 +
 +This starts with Synthesis. Synthesis turns HDL files into a transistor level description based on timing and I/O constraints. To run Synthesis click either {{:​vivado:​getting_started:​synth_ico.png?​nolink}} in the toolbar or {{:​vivado:​getting_started:​synth_btn.png?​nolink}} in the Flow Navigator. The output of Synthesis is then passed to Implementation.
 +
 +Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Layout the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either {{:​vivado:​getting_started:​impl_ico.png?​nolink}} in the toolbar or {{:​vivado:​getting_started:​impl_btn.png?​nolink}} in the Flow Navigator. This output is then passed on to the Bitstream Generator.
 +
 +The Bitstream Generator generates the final outputs needed for programming the FPGA. To run Bitstream Generation click either {{:​vivado:​getting_started:​gen_bit_ico.png?​nolink}} in the toolbar or {{:​vivado:​getting_started:​gen_bit_btn.png?​nolink}} in the Flow Navigator. With no settings changed, the generator will create a BIT file.
 +
 +==== 9. The Hardware Manager ====
 +
 +The Hardware Manager is used for programming the target device.
 +
 +{{ :​vivado:​getting_started:​hard_man.png?​direct&​500 |}}
 +
 +The first step to programming a device is to connect to it. There are two ways to do this.
 +
 +**1. Open New Hardware Target**
 +
 +<WRAP group>
 +<WRAP column half>
 +The first method is to manually open the target. This is required if the hardware is connected to another computer. To get to the Open Hardware Target wizard either open the Hardware Manager and click the {{:​vivado:​getting_started:​open_target_banner.png?​nolink}} link in the green banner or click the {{:​vivado:​getting_started:​open_target_btn.png?​nolink}} button in the Flow Navigator under {{:​vivado:​getting_started:​hw_man_btn.png?​nolink}}. From the dropdown that opens select {{:​vivado:​getting_started:​open_new_target_btn.png?​nolink}}. The wizard will open, click //Next//.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​open_target.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the //Host Name// and //Port// fields appropriately. Click //Next//.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​open_target_hw_srvr_settings.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +This screen gives a list of devices connected to the hardware server. If there is only one connected it should be the only device shown. If there are multiple connected determine the serial number of the device to connect to and find it in the list. Click //Next//.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​open_target_slct_hw_trgt.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +<WRAP group>
 +<WRAP column half>
 +The final screen shows a summary of the options selected in the wizard. Verify the information and click //Finish//. The board is now connected to the hardware manager.
 +</​WRAP>​
 +<WRAP column half>
 +{{ :​vivado:​getting_started:​open_target_summary.png?​direct&​500 |}}
 +</​WRAP>​
 +</​WRAP>​
 +
 +**2. Auto-Connect**
 +
 +The second method is to automatically open the target. To get to the {{:​vivado:​getting_started:​auto_connect_btn.png?​nolink}} button either open the Hardware Manager and click the {{:​vivado:​getting_started:​open_target_banner.png?​nolink}} link in the green banner or click the {{:​vivado:​getting_started:​open_target_btn.png?​nolink}} button in the Flow Navigator under {{:​vivado:​getting_started:​hw_man_btn.png?​nolink}}. From the dropdown that opens select {{:​vivado:​getting_started:​auto_connect_btn.png?​nolink}}. Vivado will attempt to find a hardware server running on the local machine and will connect to the device on the server.
 +
 +----
 +
 +**Programming**
 +
 +To program the device with the BIT file generated earlier either click the {{:​vivado:​getting_started:​prog_dev_banner.png?​nolink}} link in the green banner or click the {{:​vivado:​getting_started:​prog_dev_btn.png?​nolink}} button in the Flow Navigator under {{:​vivado:​getting_started:​hw_man_btn.png?​nolink}}. From the dropdown that opens select the device to program (Example: {{:​vivado:​getting_started:​prog_dev_ex.png?​nolink}}) and the following window will open:
 +
 +{{ :​vivado:​getting_started:​prog_dev_diag.png?​direct&​500 |}}
 +
 +The //Bitstream File// field should be filled in with the bit file generated earlier. If not, click the {{:​vivado:​getting_started:​browse_btn.png?​nolink}} button at the right end of the field and navigate to \\ //<​Project Directory>/<​Project Name>​.runs/​impl_1///​ and select the bit file (Example: {{:​vivado:​getting_started:​bit_file_ex.png?​nolink}}). Now click //​Program//​. This will connect to the board, clear the current configuration,​ and program using the new bit file.