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Getting Started with Vivado IP Integrator

Prerequisites


Introduction

This guide will explain the use of most of the major features of the IP Integrator design flow for a Digilent FPGA board. At the end of the demo, a simple design that receives data from on-board switches and controls LEDs will have been created.


Guide

1. Create a New IPI Project

1.1

With Vivado freshly opened, click Create New Project.

1.2

The first page of this wizard summarizes the steps involved in creating a project. Click Next.

1.3

The first step is to set the name of the project. Vivado will use this name when generating its folder structure.

Note: To aid in finding files within the project folder, it is recommended to either place the project in an empty folder or to leave the “Create project subdirectory” box checked.

Important: Do NOT use spaces in the project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or CamelCase.

Click Next to continue.

1.4

At the Select Project Type screen, choose RTL Project and check the Do not specify sources at this time box. Advanced users may want to use the other options on this screen, but they will not be covered in this guide.

Click Next to continue.

1.5

This screen selects the part targeted by the project. If Digilent's Board Files haven't yet been installed, return to the Prerequisites section of this guide and follow the link to that tutorial, Vivado will then need to be restarted to load these files properly. Select the Boards tab, then find and select the target board from the list. Click Next.

1.6

This screen summarizes selections chosen in the previous screens. Click Finish to create and open the project.


2. Open the IP Integrator

2.1

A more complete run-down of the standard Vivado workflow can be found in Digilent's Getting Started with Vivado tutorial. This guide will be exclusively using the IP Integrator tool, which can be opened from the Flow Navigator on the right side of the window. Make sure that the IP Integrator dropdown is expanded, then select Create Block Design.

2.2

In the dialog box, give the block design a name. The directory location is where the block design will be stored, this can be changed, but it is recommended to leave it as <Local to Project>. Make sure that Specify source set is set to Design Sources.

Important: Do NOT use spaces in the block design name or directory path. This will cause problems with Vivado. Instead use an underscore, a dash, or CamelCase.

Click OK to create the block design and open IPI.


3. IP Integrator Tools

The project described in this guide consists of two major segments, logic implemented in an FPGA and a processor. Depending on the target board, the processor may be implemented within the FPGA fabric, rather than being a distinct hardware component, but for the most part, this is irrelevant.

The communications protocol used to move data between peripherals implemented on the FPGA and processor is called AXI (Advanced eXtensible Interface). Each AXI peripheral implemented onto the FPGA will be assigned an area of the Zynq's memory space that will be used to address each of its control registers. Adding a simple AXI interface to a design will require the addition of two new blocks, the AXI Interconnect, which defines how the AXI signals are routed, and the reset controller, which will generate the resets of each AXI block and the interface.

Much of basic block design consists of connecting different AXI peripherals to a processor and using them to read from and write to input and output ports.

With this context out of the way, many of the tools that can be used to create a design in Vivado IPI will be described.

3.1

The Sources tab, highlighted in the image to the right, contains several sub-tabs, of these, Hierarchy and IP Sources are the most immediately useful.

The Hierarchy sub-tab shows the set of sources that exist in the project. These are split up into three groups, Design Sources contains the block design, and beneath that, sources for all of the IP cores or other files that are included in the block design. The Constraints dropdown contains Xilinx Design Constraint (XDC) files that have been added to the project. XDC files can be used to constrain ports that have been omitted from the board file.

The IP Sources sub-tab shows the files generated when a new IP core has been added to the block design. Some annoying errors can be solved by right clicking on the block design in this screen and selecting Reset Output Products followed by Generate Output Products.

3.2

When the Design tab is selected, a list of all input and output ports, IP core ports, and connections between IP cores is shown. Selecting an entry in this list will highlight that object in the block design diagram.

3.3

The Signals tab allows the user to view lists of all clock and reset signals in the block design. As before, selecting an entry in either of these lists will highlight that signal in the block design diagram. This tool can be useful for figuring out where data crosses clock domains in a more complicated design.

3.4

The Board tab displays all of the external connections that Digilent has provided as part of the board file selected as part of creating the project. This tool makes connecting these ports to a design extremely straightforward. The process of connecting one of these ports will be gone through later in this guide.

3.5

The Properties pane, found below the tabbed pane described above, shows the properties of the currently selected object. This pane is typically used to quickly view the clock frequency of a selected clock pin, or to change the name of an IP core or port.

3.6

Most of the upper right of the Vivado window is taken up by the Diagram pane. This pane displays a graphical rendition of the current block design. Many of the buttons in the toolbar to the left side of this pane will be described in Step 4 of this guide.

3.7

The Address Editor tab, contained in the same pane as the Diagram, describes the memory addresses that the processor can find each installed AXI peripheral at. Changing values in this pane is not recommended, except for advanced users. Errors in the block design validation process that refer to unmapped peripherals can be solved by right clicking anywhere in this pane and selecting Auto-Assign Address.

Note: The screenshot to the right was taken at a later stage in this process. The Address Editor tab does not appear until some memory mapped peripherals have been added to the design.

3.8

The first tab of the pane at the bottom of the window is the TCL Console. This tool displays the scripted commands that Vivado is running whenever a change is made in the graphical interface. Scripts can be created to be run using this tool through the use of the 'source' command.

3.9

The Messages tab displays Error, Warning, Info, and Status messages created when Vivado takes different actions. These messages can also be found in the TCL Console but are presented in a relatively easy to navigate format.

3.10

The Logs tab contains a set of log files that Vivado generates as part of the process of generating a bitstream.

3.11

The Reports tab contains a list of different reports that Vivado generates as part of the process of generating a bitstream.

3.12

The Design Runs tab displays the status of the different runs that make up the process of generating a bitstream.

3.13

By selecting ToolsReportsReport IP Status in the toolbar at the top of the Vivado window, another tab will be added to the bottom-most pane - though this will not do anything until an IP is added to the design. This IP Status tab displays the versions and target devices of each IP core added to the project. If an IP is not Up-to-date, clicking the Upgrade All button will reload the IP with the most recent version, or make any updates needed to make the IP work in the version of Vivado being used.

3.14

The toolbar at the top of the Diagram pane has a large number of buttons that all do different things:

  • : Zoom In and Zoom Out zoom the view of the design.
  • : Zoom Fit zooms the view so that all blocks in the current design are shown on screen.
  • : Select Area selects every block in a drawn rectangle, useful for moving groups of blocks at once.
  • : Auto-Fit Selection zooms the view to center on the currently selected block/s.
  • : Search launches a search through the nets, ports, and IPs in the current design.
  • : Collapse All and Expand All are used to maximize or minimize nested designs, referred to as Hierarchies.
  • : Add IP launches a search dialog to add a new IP block to the design. More on this later.
  • : Make External creates an input or output port for the currently selected pin. See the sidebar below for more information.
  • : Customize Block launches the customization dialog for the currently selected block. More on this later.
  • : Validate Design tells Vivado to look for mistakes in the block design, required before generating a bitstream. More on this later.
  • : Pinning Options provides a variety of options for locking blocks in place when the next two buttons are used.
  • : Regenerate Layout tells Vivado to visually clean up the block design by moving IP blocks and rerouting signals.
  • : Optimize Routing tells Vivado to visually clean up the block design by only rerouting signals.
  • : Settings and the Views dropdown next to it provide options for focusing on only part of the block design, like the interface connections between blocks.

Additionally, changes to the design can be made by interacting directly with the Diagram pane's graphical interface. Objects can be moved by clicking and dragging them. Connections can be made by hovering over a port until the pencil cursor () appears, then drawing a line to another port, pin, or wire.

With a general understanding of the actions that can be taken in IPI, a design can now be created.

Sidebar: Make External - Manual Constraint Flow
The Make External button can be used to connect an IPs pin or port to an external port, which can then be constrained to an FPGA pin (or set of pins).

Master XDC (Xilinx Design Constraint) files for Digilent boards can be downloaded from the Digilent XDC repository on GitHub. An archive of the entire set of XDCs can be downloaded here: digilent-xdc-master.zip. Use of these files will be familiar to those who have run through Getting Started with Vivado.

Once downloaded, the master XDC file corresponding to the target board can be added to the project by right-clicking within the Sources pane, and selecting “Add Sources”.

Once the port has been made external, the block design validated, and the HDL wrapper created or updated, the external port names used by Vivado can be found within the HDL wrapper file. This file can be found in Vivado's Sources pane, under Design Sources.

With the names of external port/s known, the master XDC should be opened and edited, uncommenting the lines for the pins that are to be connected to the external port, and changing the name found after the “get_ports” call to match those found in the HDL wrapper. For example, if an AXI GPIO controller has been added to the project, and its GPIO port has been configured to be 4 bits wide, and made external, the names of the corresponding ports in the constraints file will need to be changed to “GPIO_0_tri_io[0]”, “GPIO_0_tri_io[1]”, “GPIO_0_tri_io[2]”, and “GPIO_0_tri_io[3]”. These names correspond to the name of the external interface port (GPIO_0), the type of IO (tri_io, a bidirectional port using a tristate buffer), and the pin number within the interface (0..3).


4. Create a Simple Block Design

4.1

Right click on Push Buttons in the Board tab, then select connect component. In the dialog that pops up, select GPIO under Create new IP → AXI GPIO.

4.1 (Continued)

In the resulting popup, make sure to connect the button component to GPIO specifically, not GPIO2. The C source code provided later assumes this to be the case.

Click OK to continue.

Repeat these steps to connect the LEDs to the now Existing IP's GPIO2 port.

The remainder of this section branches depending on the board the project is being designed for. If the target board uses a Zynq chip, open the Zynq drop-down below, otherwise, open the Microblaze drop-down below.

Zynq

4.2

Click the Add IP button () and search for 'Zynq'. Select Zynq7 Processing System from the list of results and press Enter on the keyboard to continue.

Doing this adds a Zynq processor to the block design. A Zynq chip contains both FPGA fabric and a hardware processor. This block represents the processor, as well as other hardware components not part of the FPGA.

4.3

Click Run Block Automation in the green bar at the top of the screen. This will launch a dialog that allows initial configuration of the Zynq block.

In the Run Block Automation dialog, make sure that the Apply Board Preset is checked. This option configures the Zynq block with a preset pulled from Digilent's board files, including some settings like DDR timing parameters that are specific to the board and should not be changed.

Click OK to continue.

4.4

Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. For example, the Zynq block can be used to generate new clocks of different frequencies. Select the Zynq block by clicking on it and then clicking the Customize Block () button, or by double-clicking on the Zynq block.

The Zynq Configuration drop-down below walks through each of the screens in the Zynq's Re-Customize IP dialog.

Zynq Configuration

4.4.1

The page that opens when the Zynq block is re-customized is called the Zynq Block Design. This page displays the hardware used by the Zynq chip. Note the I/O Peripherals block, the check-marks display what peripherals are currently enabled. All of the information shown in this screen is available in lists in the other pages.

4.4.2

The PS-PL Configuration page allows the user to customize how the processor will communicate with the FPGA. There are several settings of particular note here.

  • The UART baud rate settings found in the General drop-down are used to change the baud rate that the Zynq communicates with a computer serial port at.
  • GP/HP Slave AXI Interfaces (General Purpose / High Performance) are used when an AXI peripheral requires control over a memory interface, this can be seen in Digilent's HDMI and Audio DMA demo projects.

4.4.3

The Peripheral I/O Pins page allows the user to enable or disable a large number of different hardware peripherals that cannot be controlled directly from the FPGA. As an example, enabling GPIO MIO allows the user to control LED 4 (LD4/MIO7) on the Zybo board.

4.4.4

The MIO Configuration page shares much of its information with Peripheral I/O Pins, and allows the user to view this in a list, rather than the graphical table format.

4.4.5

The Clock Configuration page contains important settings that allow the user to provide additional clocks at different speeds to the FPGA, as well as tweaking the clock frequencies of several IO Peripherals. Take note of the PL Fabric Clocks drop-down, checking a box for one of FCLK_CLK1-3 will provide an additional clock output from the Zynq block, at or near the provided Requested Frequency.

4.4.6

The DDR Configuration page contains a large number of settings related to the DDR chip connected to the Zynq chip. This page alone is a good reason to use the board preset brought in from Digilent's board files. Changing these settings is not recommended.

4.4.7

The Interrupts page is another extremely useful one. To use any interrupts with the FPGA, the Fabric Interrupts checkbox must be checked. Many AXI IP cores can be configured to generate an interrupt on some trigger, for instance AXI GPIO cores can be set up to trigger an interrupt whenever an input changes. Checking the IRQ_F2P box in the PL-PS Interrupt Ports drop-down creates a new input port on the Zynq block which can be connected to up to sixteen individual interrupt pins via a Concat (concatenation) IP core. To use interrupts, the 'xscugic' driver for the generic interrupt controller found in the Zynq hardware must be used.

Additionally, interrupts generated by hardware peripherals connected using the Peripheral I/O Pins or MIO Configuration pages can be provided to the FPGA using the fields in the PS-PL Interrupt Ports drop-down.

4.5

In order to connect the GPIO peripheral to the Zynq block, click Run Connection Automation in the green bar at the top of the block design diagram pane.

In the Run Connection Automation dialog's list pane, make sure that the S_AXI entry is checked and selected.

In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select /processing_system7_0/FCLK_CLK0 from the drop-down list.

Note: Selecting “Auto” as the clock source will often work perfectly for simple designs. The section dropdown is highlighted here for users who continue on to create more complex designs with many clocks.

Click OK to continue.

Microblaze

4.2

In the Board tab, right click on System Clock and select Connect Board Component.

4.3

In the Connect Board Component dialog make sure that the clock_CLK_IN1 checkbox under Create New IP → Clocking Wizard is checked.

Click OK to continue.

4.4

Double click on the newly created clocking wizard block or select it and click the Customize IP button ().

In the Board tab, make sure that sys clock is selected in the CLK_IN1 dropdown, then choose reset from the EXT_RESET_IN drop-down.

4.5

Select the Output Clocks tab. On this page there are several different options for how to configure the clocking wizard. For the purposes of this guide, the reset type needs to be configured, and a single 100MHz clock needs to be generated.

Make sure that the clk_out1 box is checked and that it's Requested Frequency is 100.000 (MHz).

Depending on how the specific board's reset button works, select Active Low or Active High for the Reset Polarity. The Basys 3 and Cmod A7 are the only boards that use an active high reset polarity at the time of writing.

Click OK to save changes and continue.

4.6

In the Board tab, right click on the USB UART and select Connect Board Component.

4.7

In the Connect Board Component dialog, make sure to select the AXI Uartlite variant of the IP.

Click OK to continue.

4.8

Click Run Connection Automation in the green bar at the top of the block design diagram pane.

Make sure that the reset entry the list on the left-hand side of the Run Connection Automation dialog is checked and selected. With this box checked, Vivado will automatically connect the reset component selected in the Board pane of the Clocking Wizard Configuration dialog to the clocking wizard, as specified in the Board tab of the Clocking Wizard configuration dialog.

Click OK to continue.

4.9

Click the Add IP button () and search for 'MicroBlaze'. Select MicroBlaze from the list of results and press Enter on the keyboard to continue.

4.10

Click Run Block Automation in the green bar at the top of the screen. This will launch a dialog that allows initial configuration of the MicroBlaze and several different IP cores that are key to the function of the design.

In the Run Block Automation dialog, make sure that MicroBlaze_0 under All Automation in the panel to the left is selected and checked.

There are a number of different options available. For the purposes of this guide, set these options to the value found in parentheses below.

  • Local Memory (32KB): This option allows the selection of the amount of memory available to the processor. The program to be run on the board must be able to fit in this memory, and this memory must fit within the block RAM available on the board.
  • Local Memory ECC (None): This option enables or disables Error Correction in the local memory.
  • Cache Configuration (None): This option allows the selection of the size of the Cache. If required, this can be used to speed up memory access.
  • Debug Module (Debug Only): This option lets the user select the extent of hardware debug features to be used.
  • Peripheral AXI Port (Enabled): This option enables or disables an AXI master port on the MicroBlaze block, which is used to connect the processor to many different Xilinx provided peripheral IP cores.
  • Interrupt Controller (Unchecked): This option lets the user select whether or not to automatically generate an interrupt controller, which can be used to trigger the processor to process timing critical functions.
  • Clock Connection (/clk_wiz_0/clk_out1): This option allows the user to select which clock source should be used to clock the processor. This can either be a clock that already exists in the design, or block automation can automatically generate a new one.

Click OK to continue.

4.11

In order to connect the Uartlite and GPIO peripherals to the MicroBlaze block, in the green bar at the top of the window, click Run Connection Automation. Similarly to the Run Block Automation dialog, the pane to the left of the dialog contains a list of things that can be automated. In this case, the AXI connections for axi_gpio_0 and axi_uartlite_0, are available.

Check the box next to All Automation to make sure that all of the connections will be made.

The clock source for the AXI connection can be changed by selecting the S_AXI entry in the list, and changing the value in the Clock Connection option. Make sure that this option is set to Auto or /clk_wiz_0/clk_out1 for each of the two AXI connections.

Click OK to continue.


5. Generate the Bitstream

5.1

Click the Validate Design button () to have Vivado confirm that everything looks good.

Click OK to continue.

Note: Some Zynq boards may produce critical warnings at this stage relating to the the PS DDR DQS to CLK delay. These are expected and will not affect the functionality of the project. See the Hardware Errata section of the board's resource center for more information.

5.2

The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the Sources tab to the left of the Diagram - likely the Board tab is currently selected.

In the right-click menu, select Create HDL Wrapper. In the confirmation dialog that pops up, make sure that Let Vivado manage wrapper and auto-update is selected in the options list. If manual changes need to be made to the wrapper file, the other option here can be selected, but it is not recommended except for advanced users. Click OK to have Vivado finish making the wrapper file.

5.3

With a validated design and a top module, a bitstream can now be generated. The Getting Started with Vivado guide explains this process in a little more detail, but for now, click the Generate Bitstream button in the Flow Navigator.

5.4

In the next dialog, No Implementation Results Available, Vivado will ask whether to run Synthesis and Implementation. These steps are required to generate a bitstream, so click Yes.

5.5

The Launch Runs dialog that pops up has several options to choose between. Select Launch runs on local host to actually generate the bitstream now. The other option is to Generate scripts only, which will not generate a bitstream, but rather the scripts required to generate the bitstream on a different machine. The Number of jobs field allows the user to change how much of the resources of the computer Vivado is running on will be used. This process can take some time for complex designs, so it is recommended to devote as much of the resources as possible (typically by selecting '8').

Click OK to continue.

5.6

Once the bitstream is generated, which may take some time, Vivado will ask what to do next. None of the available options are required for this guide, so click Cancel.

5.7

The final steps to take place in Vivado involve exporting an XSA (Xilinx Shell Architecture) file which includes all parts of the design relevant to Vitis.

In the File drop-down, select Export then Export Hardware. This function collects all of the files that Vitis needs to program the FPGA and control the hardware instantiated in the design and puts them all into one place.

5.8

Make sure that the Include Bitstream box is checked, so that the FPGA can be programmed from Vitis. The Export Location is <Local To Project> by default. This means that Vivado will place the XSA file - named '<HDL wrapper name>.xsa' by default - within the Vivado project directory (D:/Work/blinky as seen in the screenshots). If a different location is chosen for the XSA file, make sure to remember where it is.

Important: Do NOT use spaces in the export location path. This will cause problems with Vivado. Instead use an underscore, a dash, or CamelCase.

Click OK to continue.


6. Launch Vitis

6.1

In Vivado's Tools menu, select Launch Vitis.

6.2

Upon launch of Vitis, a dialog pops up to select where to place the Vitis workspace. The chosen folder will contain the project and all of the source files. Choose a memorable location for the workspace, then click Launch.

Important: Do NOT use spaces in the workspace path. This will cause problems with Vivado. Instead use an underscore, a dash, or CamelCase.

Click OK to continue.


7. Create a Project and a Platform

7.1

Vitis will now launch creating the workspace with no projects or platforms in it. Clicking on Create Application Project will launch a wizard that can be used to create both a project and a platform to support it.

7.2

The first page of this wizard is for entering a name for the application project being created. Enter a name (without spaces, as usual), then click Next.

7.3

The next page is for choosing the hardware platform that the project will run on. In this case, a new hardware platform will be created from the XSA file that was exported from Vivado. Select the Create a new platform … tab at the top of the window, then click the plus (+) button in the upper left.

7.4

In the popup dialog, navigate to and select the exported XSA file, then click Open.

Note: If the Exported Location was left default when exporting the XSA from Vivado, the file can be found in the directory the Vivado project is located in.

In the New Application Project wizard, make sure that the exported XSA file is selected, then click Next.

7.5

Next, the project domain will be configured. The default settings will typically work for this.

Note: The Generate boot components checkbox tells Vitis whether or not it should create a first stage bootloader, which can be used to boot the project from SPI flash, an SD card, or some other supported medium. Using these boot methods is outside of the scope of this guide.

7.6

From the list of Available Templates, select Empty Application, then click Finish.

7.7

At this point, the structure of the workspace has been created. Two files will automatically be opened:

  1. The System Project Settings contains a list of all application projects associated with the system project.
  2. The Application Project Settings contains project settings like environment variables, additional linked sources, and other details of interest.

Of particular note is the Navigate to BSP Settings button in the Application Project Settings. Clicking this will navigate to the Board Support Package (BSP) settings page. This lists drivers and libraries available to the application project. New users may find the links to documentation and examples listed for each Peripheral Driver of particular interest.

7.8

Next, a main source file will be created. In the application project (under the “_system” and project dropdowns), right click on the “src” folder, then click New → File

7.9

In the popup dialog, leave the “parent folder” field as default, as it was chosen based on where the New File option was selected. Name the file “main.c”, then click Finish.

7.10

The new main file will now open in the file view pane. Copy-Paste the code found below into this file, then hit Ctrl-S to save the file and build the project.

This code uses the xgpio driver for Xilinx's AXI GPIO IP to read the state of the buttons, then toggle the LEDs whenever the state of any button changes. In addition, the code prints the button state out to stdout (UART by default).

Depending on the board used, and additional changes that may have been made to the block design (like changing the name of the AXI GPIO IP), changes may need to be made to the “Block Design Details section. The AXI GPIO's device ID is pulled in from the xparameters header. The details of the interfaces that the AXI GPIO is connected to must be manually filled in. The _CH macros correspond to which GPIO channel the interface in question is connected to (1=GPIO, 2=GPIO2). The _TRI macros are written in binary, and must contain a 0 (output) or 1 (input) for each LED or button (respectively) that is connected to that interface. The values that are filled in by default correspond to a board with 4 buttons and 4 LEDs. The _MASK macros are used to discard irrelevant data from unused bits, and should contain a 1 for each button or LED in the interface.

// Header Inclusions
#include "xparameters.h"
#include "xgpio.h"
#include "xil_types.h"
#include "xil_printf.h"
#include "xstatus.h"
#include "sleep.h"

// Block Design Details
#define GPIO_ID XPAR_AXI_GPIO_0_DEVICE_ID

#define GPIO_BTN_CH 1
#define GPIO_BTN_TRI 0b1111
#define GPIO_BTN_MASK 0b1111

#define GPIO_LED_CH 2
#define GPIO_LED_TRI 0b0000
#define GPIO_LED_MASK 0b1111

// GPIO Driver Device
XGpio device;

// Demo Main
int main() {
	u32 btn_data, btn_old_data, led_data = 0;
	XStatus status;

	// Initialize the GPIO device
	status = XGpio_Initialize(&device, GPIO_ID);
	if (status != XST_SUCCESS) {
		xil_printf("Initialization failed\n\r");
		return 1;
	}

	// Set tristates, '1' for input, '0' for output
	XGpio_SetDataDirection(&device, GPIO_BTN_CH, GPIO_BTN_TRI);
	XGpio_SetDataDirection(&device, GPIO_LED_CH, GPIO_LED_TRI);

	xil_printf("Demo initialized successfully\n\r");

	while (1) {
		btn_data = XGpio_DiscreteRead(&device, GPIO_BTN_CH);
		btn_data &= GPIO_BTN_MASK;

		if (btn_data != btn_old_data) {
			// When any button is pressed or released, toggle the LEDs
			//  and report the state over UART.
			xil_printf("Button state changed: 0x%x\n\r", btn_data);
			led_data = (~led_data) & GPIO_LED_MASK;
			XGpio_DiscreteWrite(&device, GPIO_LED_CH, led_data);
			btn_old_data = btn_data;
			// Wait (10 us) to check the state again until bounces settle
			usleep(10);
		}
	}
}

7.11

Now that the application project has some code associated with it, build it, either by right-clicking on the application project and selecting Build Project, or by using the Ctrl-B hotkey.


8. Program and Run the Design

The next step is to program the bit file into the FPGA and run the C application on the processor.

First, plug the board into the computer via a microUSB programming cable, set its programming mode select jumper to JTAG, and power it on (connecting a power supply if necessary).

8.1

In order to receive UART messages, which are sent by the 'xil_printf' statements in the project's C source code, it is recommended to use a serial console application like Tera Term or PuTTY. Serial Port settings are determined by the configuration of the Zynq block or the AXI Uartlite block's customization settings.

Typically these settings will be 8 Data Bits, No Parity Bit, 1 Stop Bit, and a baud rate of 115200 for Zynq and 9600 for MicroBlaze by default.

More information on serial terminal applications can be found here: Installing and Using a Terminal Emulator (Redirect)

8.2

In Vitis, right click on the application project in the Explorer, then select Run As → Launch on Hardware (Single Application Debug).

Note: While this process also programs the bit file into the FPGA, it can also be done manually through the Xilnx → Program FPGA option in the menu bar at the top of the window.

8.3

The application is now running on the board! Printed statements can be viewed in the serial terminal application, and the application can be interacted with by pressing the board's buttons.


Next Steps

Examples of more complicated IPI designs - including examples of the use of DDR memory in MicroBlaze designs - are linked from the target board's resource center, which can be found in the list on this Wiki's Programmable Logic (Redirect) page.