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vivado:getting-started-with-ipi:v2019.2 [2020/03/18 16:18] – Arthur Brownvivado:getting-started-with-ipi:v2019.2 [2020/04/15 16:33] – [8. Program and Run the Design] Arthur Brown
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 === 1.3 === === 1.3 ===
 The first step is to set the name of the project. Vivado will use this name when generating its folder structure. The first step is to set the name of the project. Vivado will use this name when generating its folder structure.
 +
 +**Note:** //To aid in finding files within the project folder, it is recommended to either place the project in an empty folder or to leave the "Create project subdirectory" box checked.//
  
 **Important:** //Do NOT use spaces in the project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].// **Important:** //Do NOT use spaces in the project name or location path. This will cause problems with Vivado. Instead use an underscore, a dash, or [[wp>CamelCase]].//
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 <WRAP column half> <WRAP column half>
 === 1.6 === === 1.6 ===
-This screen summarizes selections chosen in the previous screens. Click **Next** to finish opening the new project.+This screen summarizes selections chosen in the previous screens. Click **Finish** to create and open the project.
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 === 2.1 === === 2.1 ===
-A more complete run-down of the standard Vivado workflow can be found in Digilent's [[:vivado:getting_started:v2019.2]] tutorial. This guide will be exclusively using the IP Integrator tool, which can be opened from the **Flow Navigator** on the right side of the window. Expand the **IP Integrator** tab and select **Create Block Design**.+A more complete run-down of the standard Vivado workflow can be found in Digilent's [[:vivado:getting_started:v2019.2]] tutorial. This guide will be exclusively using the IP Integrator tool, which can be opened from the **Flow Navigator** on the right side of the window. Make sure that the **IP Integrator** dropdown is expanded, then select **Create Block Design**.
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 === 3.1 === === 3.1 ===
-The **Sources** tab, highlighted in the image to the right, contains several sub-tabs, of these, **Hierarchy** and **IP Sources** are the most immediately useful.+The //Sources// tab, highlighted in the image to the right, contains several sub-tabs, of these, //Hierarchy// and //IP Sources// are the most immediately useful.
  
-The **Hierarchy** sub-tab shows the set of sources that exist in the project. These are split up into three groups, **Design Sources** contains the block design, and beneath that, sources for all of the IP cores or other files that are included in the block design. The **Constraints** sub-tab contains Xilinx Design Constraint (XDC) files that have been added to the project. XDC files can be used to constrain ports that have been omitted from the board file.+The //Hierarchy// sub-tab shows the set of sources that exist in the project. These are split up into three groups, //Design Sources// contains the block design, and beneath that, sources for all of the IP cores or other files that are included in the block design. The //Constraints// dropdown contains Xilinx Design Constraint (XDC) files that have been added to the project. XDC files can be used to constrain ports that have been omitted from the board file.
  
-The **IP Sources** sub-tab shows the files generated when a new IP core has been added to the block design. Some annoying errors can be solved by right clicking on the block design in this screen and selecting **Reset Output Products** followed by **Generate Output Products**.+The //IP Sources// sub-tab shows the files generated when a new IP core has been added to the block design. Some annoying errors can be solved by right clicking on the block design in this screen and selecting **Reset Output Products** followed by **Generate Output Products**.
 </WRAP> </WRAP>
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 === 3.2 === === 3.2 ===
-When the **Design** tab is selected, a list of all input and output ports, IP core ports, and connections between IP cores is shown. Selecting an entry in this list will highlight that object in the block design diagram.+When the //Design// tab is selected, a list of all input and output ports, IP core ports, and connections between IP cores is shown. Selecting an entry in this list will highlight that object in the block design diagram.
 </WRAP> </WRAP>
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 === 3.3 === === 3.3 ===
-The **Signals** tab allows the user to view lists of all clock and reset signals in the block design. As before, selecting an entry in either of these lists will highlight that signal in the block design diagram. This tool can be useful for figuring out where data crosses clock domains in a more complicated design.+The //Signals// tab allows the user to view lists of all clock and reset signals in the block design. As before, selecting an entry in either of these lists will highlight that signal in the block design diagram. This tool can be useful for figuring out where data crosses clock domains in a more complicated design.
 </WRAP> </WRAP>
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 === 3.4 === === 3.4 ===
-The **Board** tab displays all of the external connections that Digilent has provided as part of the board file selected as part of creating the project. This tool makes connecting these ports to a design extremely straightforward. The process of connecting one of these ports will be gone through later in this guide.+The //Board// tab displays all of the external connections that Digilent has provided as part of the board file selected as part of creating the project. This tool makes connecting these ports to a design extremely straightforward. The process of connecting one of these ports will be gone through later in this guide.
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 === 3.5 === === 3.5 ===
-The **Properties** pane, found below the tabbed pane described above, shows the properties of the currently selected object. This pane is typically used to quickly view the clock frequency of a selected clock pin, or to change the name of an IP core or port.+The //Properties// pane, found below the tabbed pane described above, shows the properties of the currently selected object. This pane is typically used to quickly view the clock frequency of a selected clock pin, or to change the name of an IP core or port.
 </WRAP> </WRAP>
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 === 3.7 === === 3.7 ===
-The **Address Editor** tab, contained in the same pane as the Diagram, describes the memory addresses that the processor can find each installed AXI peripheral at. Changing values in this pane is not recommended, except for advanced users. Errors in the block design validation process that refer to unmapped peripherals can be solved by right clicking anywhere in this pane and selecting **Auto-Assign Address**.+The //Address Editor// tab, contained in the same pane as the Diagram, describes the memory addresses that the processor can find each installed AXI peripheral at. Changing values in this pane is not recommended, except for advanced users. Errors in the block design validation process that refer to unmapped peripherals can be solved by right clicking anywhere in this pane and selecting **Auto-Assign Address**.
  
 **Note:** //The screenshot to the right was taken at a later stage in this process. The Address Editor tab does not appear until some memory mapped peripherals have been added to the design.// **Note:** //The screenshot to the right was taken at a later stage in this process. The Address Editor tab does not appear until some memory mapped peripherals have been added to the design.//
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 === 3.8 === === 3.8 ===
-The first tab of the pane at the bottom of the window is the **TCL Console**. This tool displays the scripted commands that Vivado is running whenever a change is made in the graphical interface. Scripts can be created to be run using this tool through the use of the 'source' command.+The first tab of the pane at the bottom of the window is the //TCL Console//. This tool displays the scripted commands that Vivado is running whenever a change is made in the graphical interface. Scripts can be created to be run using this tool through the use of the 'source' command.
 </WRAP> </WRAP>
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 === 3.9 === === 3.9 ===
-The **Messages** tab displays Error, Warning, Info, and Status messages created when Vivado takes different actions. These messages can also be found in the TCL Console but are presented in a relatively easy to navigate format.+The //Messages// tab displays Error, Warning, Info, and Status messages created when Vivado takes different actions. These messages can also be found in the TCL Console but are presented in a relatively easy to navigate format.
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 === 3.10 === === 3.10 ===
-The **Logs** tab contains a set of log files that Vivado generates as part of the process of generating a bitstream.+The //Logs// tab contains a set of log files that Vivado generates as part of the process of generating a bitstream.
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 === 3.11 === === 3.11 ===
-The **Reports** tab contains a list of different reports that Vivado generates as part of the process of generating a bitstream.+The //Reports// tab contains a list of different reports that Vivado generates as part of the process of generating a bitstream.
 </WRAP> </WRAP>
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 === 3.12 === === 3.12 ===
-The **Reports** tab displays the status of the different runs that make up the process of generating a bitstream.+The //Design Runs// tab displays the status of the different runs that make up the process of generating a bitstream.
 </WRAP> </WRAP>
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 === 3.13 === === 3.13 ===
-By selecting **Tools** -> **Reports** -> **Report IP Status** in the toolbar at the top of the Vivado window, another tab will be added to the bottom-most pane - though this will not do anything until an IP is added to the design. This **IP Status** tab displays the versions and target devices of each IP core added to the project. If an IP is not **Up-to-date**, clicking the **Upgrade All** button will reload the IP with the most recent version, or make any updates needed to make the IP work in the version of Vivado being used.+By selecting **Tools** -> **Reports** -> **Report IP Status** in the toolbar at the top of the Vivado window, another tab will be added to the bottom-most pane - though this will not do anything until an IP is added to the design. This //IP Status// tab displays the versions and target devices of each IP core added to the project. If an IP is not **Up-to-date**, clicking the **Upgrade All** button will reload the IP with the most recent version, or make any updates needed to make the IP work in the version of Vivado being used.
 </WRAP> </WRAP>
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 === 3.14 === === 3.14 ===
  
-The toolbar at the top of the **Diagram** pane has a large number of buttons that all do different things:+The toolbar at the top of the //Diagram// pane has a large number of buttons that all do different things:
   * {{vivado:getting-started-with-ipi:v2019.2:button-zoom-in.png|}} {{vivado:getting-started-with-ipi:v2019.2:button-zoom-out.png|}} : //Zoom In// and //Zoom Out// zoom the view of the design.   * {{vivado:getting-started-with-ipi:v2019.2:button-zoom-in.png|}} {{vivado:getting-started-with-ipi:v2019.2:button-zoom-out.png|}} : //Zoom In// and //Zoom Out// zoom the view of the design.
   * {{vivado:getting-started-with-ipi:v2019.2:button-zoom-fit.png|}} : //Zoom Fit// zooms the view so that all blocks in the current design are shown on screen.   * {{vivado:getting-started-with-ipi:v2019.2:button-zoom-fit.png|}} : //Zoom Fit// zooms the view so that all blocks in the current design are shown on screen.
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 ==== 4. Create a Simple Block Design ==== ==== 4. Create a Simple Block Design ====
  
-<WRAP group> +<WRAP group> <WRAP column half>
-<WRAP column half>+
 === 4.1 === === 4.1 ===
-Right click on **Push Buttons** in the board tab, then select connect component. In the dialog that pops up, select **GPIO** under **Create new IP -> AXI GPIO**.+Right click on **Push Buttons** in the //Board// tab, then select connect component. In the dialog that pops up, select **GPIO** under **Create new IP -> AXI GPIO**. 
 +</WRAP> <WRAP column half> 
 +{{ :vivado:getting-started-with-ipi:v2019.2:connect-buttons.png?800 |}} 
 +</WRAP> </WRAP>
  
-**Important:** //Make sure to connect the button component to //GPIO// specifically, not //GPIO2//. The C source code provided later assumes this to be the case.//+<WRAP group> <WRAP column half> 
 +=== 4.1 (Continued) === 
 +In the resulting popup, make sure to connect the button component to //GPIO// specifically, not //GPIO2//. The C source code provided later assumes this to be the case.
  
 Click **OK** to continue. Click **OK** to continue.
  
-Do the same to connect the **LEDs** to the now **Existing IP's** **GPIO2** port. +Repeat these steps to connect the **LEDs** to the now //Existing IP's// **GPIO2** port. 
-</WRAP> +</WRAP> <WRAP column half> 
-<WRAP column half> +{{ :vivado:getting-started-with-ipi:v2019.2:connect-buttons-dialog.png?400 |}} 
-{{ :vivado:getting-started-with-ipi:v2019.2:connect-buttons.png?800 |}} +</WRAP> </WRAP>
-</WRAP> +
-</WRAP>+
  
 The remainder of this section branches depending on the board the project is being designed for. If the target board uses a Zynq chip, open the //Zynq// drop-down below, otherwise, open the //Microblaze// drop-down below. The remainder of this section branches depending on the board the project is being designed for. If the target board uses a Zynq chip, open the //Zynq// drop-down below, otherwise, open the //Microblaze// drop-down below.
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 === 4.2 === === 4.2 ===
-Click the **Add IP** button ({{vivado:getting-started-with-ipi:v2019.2:buttons:add-ip.png|}}) and search for 'Zynq'. Select **Zynq7 Processing System** from the list of results and press **Enter** on the keyboard to continue.+Click the **Add IP** button ({{vivado:getting-started-with-ipi:v2019.2:button-add-ip.png|}}) and search for 'Zynq'. Select **Zynq7 Processing System** from the list of results and press **Enter** on the keyboard to continue.
  
 Doing this adds a Zynq processor to the block design. A Zynq chip contains both FPGA fabric and a hardware processor. This block represents the processor, as well as other hardware components not part of the FPGA. Doing this adds a Zynq processor to the block design. A Zynq chip contains both FPGA fabric and a hardware processor. This block represents the processor, as well as other hardware components not part of the FPGA.
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 === 4.4 === === 4.4 ===
-Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. For example, the Zynq block can be used to generate new clocks of different frequencies. Select the Zynq block by clicking on it and then clicking the //Customize Block// ({{vivado:getting-started-with-ipi:v2019.2:buttons:customize-block.png|}}) button, or by double-clicking on the Zynq block.+Additional changes can be made to the Zynq block's configuration, depending on the requirements of the project. For example, the Zynq block can be used to generate new clocks of different frequencies. Select the Zynq block by clicking on it and then clicking the //Customize Block// ({{vivado:getting-started-with-ipi:v2019.2:button-customize-block.png|}}) button, or by double-clicking on the Zynq block.
  
 The **Zynq Configuration** drop-down below walks through each of the screens in the Zynq's Re-Customize IP dialog. The **Zynq Configuration** drop-down below walks through each of the screens in the Zynq's Re-Customize IP dialog.
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 === 4.4.1 === === 4.4.1 ===
-The page that opens when the Zynq block is re-customized is called **Zynq Block Design**. This page displays the hardware used by the Zynq chip. Note the **I/O Peripherals** block, the check-marks display what peripherals are currently enabled. All of the information shown in this screen is available in lists in the other pages.+The page that opens when the Zynq block is re-customized is called the //Zynq Block Design//. This page displays the hardware used by the Zynq chip. Note the **I/O Peripherals** block, the check-marks display what peripherals are currently enabled. All of the information shown in this screen is available in lists in the other pages.
 </WRAP> </WRAP>
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-{{ vivado:getting_started_with_zynq:zynq-config:zynq-block-design.png?800 |}}+{{ vivado:getting-started-with-ipi:v2019.2:zynq-config-1.png?800 |}}
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 === 4.4.2 === === 4.4.2 ===
-The **PS-PL Configuration** page allows the user to customize how the processor will communicate with the FPGA. There are several settings of particular note here.+The //PS-PL Configuration// page allows the user to customize how the processor will communicate with the FPGA. There are several settings of particular note here.
   * The UART baud rate settings found in the **General** drop-down are used to change the baud rate that the Zynq communicates with a computer serial port at.   * The UART baud rate settings found in the **General** drop-down are used to change the baud rate that the Zynq communicates with a computer serial port at.
   * **GP/HP Slave AXI Interfaces** (General Purpose / High Performance) are used when an AXI peripheral requires control over a memory interface, this can be seen in Digilent's HDMI and Audio DMA demo projects.   * **GP/HP Slave AXI Interfaces** (General Purpose / High Performance) are used when an AXI peripheral requires control over a memory interface, this can be seen in Digilent's HDMI and Audio DMA demo projects.
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 </WRAP> </WRAP>
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-{{ vivado:getting_started_with_zynq:zynq-config:ps-pl-configuration.png?800 |}}+{{ vivado:getting-started-with-ipi:v2019.2:zynq-config-2.png?800 |}}
 </WRAP> </WRAP>
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 === 4.4.3 === === 4.4.3 ===
-The **Peripheral I/O Pins** page allows the user to enable or disable a large number of different hardware peripherals that cannot be controlled directly from the FPGA. As an example, enabling GPIO MIO allows the user to control LED 4 (LD4/MIO7) on the Zybo board.+The //Peripheral I/O Pins// page allows the user to enable or disable a large number of different hardware peripherals that cannot be controlled directly from the FPGA. As an example, enabling GPIO MIO allows the user to control LED 4 (LD4/MIO7) on the Zybo board.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ vivado:getting_started_with_zynq:zynq-config:peripheral-io-pins.png?800 |}}+{{ vivado:getting-started-with-ipi:v2019.2:zynq-config-3.png?800 |}}
 </WRAP> </WRAP>
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 === 4.4.4 === === 4.4.4 ===
-The **MIO Configuration** page shares much of its information with Peripheral I/O Pins, and allows the user to view this in a list, rather than the graphical table format.+The //MIO Configuration// page shares much of its information with Peripheral I/O Pins, and allows the user to view this in a list, rather than the graphical table format.
 </WRAP> </WRAP>
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-{{ vivado:getting_started_with_zynq:zynq-config:mio-configuration.png?800 |}}+{{ vivado:getting-started-with-ipi:v2019.2:zynq-config-4.png?800 |}}
 </WRAP> </WRAP>
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 === 4.4.5 === === 4.4.5 ===
-The **Clock Configuration** page contains important settings that allow the user to provide additional clocks at different speeds to the FPGA, as well as tweaking the clock frequencies of several IO Peripherals. Take note of the **PL Fabric Clocks** drop-down, checking a box for one of FCLK_CLK1-3 will provide an additional clock output from the Zynq block, at or near the provided **Requested Frequency**.+The //Clock Configuration// page contains important settings that allow the user to provide additional clocks at different speeds to the FPGA, as well as tweaking the clock frequencies of several IO Peripherals. Take note of the **PL Fabric Clocks** drop-down, checking a box for one of FCLK_CLK1-3 will provide an additional clock output from the Zynq block, at or near the provided **Requested Frequency**.
 </WRAP> </WRAP>
 <WRAP column half> <WRAP column half>
-{{ vivado:getting_started_with_zynq:zynq-config:clock-configuration.png?800 |}}+{{ vivado:getting-started-with-ipi:v2019.2:zynq-config-5.png?800 |}}
 </WRAP> </WRAP>
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 === 4.4.6 === === 4.4.6 ===
-The **DDR Configuration** page contains a large number of settings about the DDR chip connected to the Zynq chip. This page alone is the reason to use the board preset brought in from Digilent's board file. Changing these settings is //not recommended//.+The //DDR Configuration// page contains a large number of settings related to the DDR chip connected to the Zynq chip. This page alone is a good reason to use the board preset brought in from Digilent's board files. Changing these settings is //not recommended//.
 </WRAP> </WRAP>
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-{{ vivado:getting_started_with_zynq:zynq-config:ddr-configuration.png?800 |}}+{{ vivado:getting-started-with-ipi:v2019.2:zynq-config-6.png?800 |}}
 </WRAP> </WRAP>
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 === 4.4.7 === === 4.4.7 ===
-The **Interrupts** page is another extremely useful one. To use any interrupts with the FPGA, the **Fabric Interrupts** checkbox must be checked. Many AXI IP cores can be configured to generate an interrupt on some trigger, for instance AXI GPIO cores can be set up to trigger an interrupt whenever an input changes. Checking the **IRQ_F2P** box in the **PL-PS Interrupt Ports** drop-down creates a new input port on the Zynq block which can be connected to up to sixteen individual interrupt pins via a Concat (concatenation) IP core. To use interrupts, the 'xscugic' driver for the generic interrupt controller found in the Zynq hardware must be used.+The //Interrupts// page is another extremely useful one. To use any interrupts with the FPGA, the **Fabric Interrupts** checkbox must be checked. Many AXI IP cores can be configured to generate an interrupt on some trigger, for instance AXI GPIO cores can be set up to trigger an interrupt whenever an input changes. Checking the **IRQ_F2P** box in the **PL-PS Interrupt Ports** drop-down creates a new input port on the Zynq block which can be connected to up to sixteen individual interrupt pins via a Concat (concatenation) IP core. To use interrupts, the 'xscugic' driver for the generic interrupt controller found in the Zynq hardware must be used.
  
 Additionally, interrupts generated by hardware peripherals connected using the Peripheral I/O Pins or MIO Configuration pages can be provided to the FPGA using the fields in the **PS-PL Interrupt Ports** drop-down. Additionally, interrupts generated by hardware peripherals connected using the Peripheral I/O Pins or MIO Configuration pages can be provided to the FPGA using the fields in the **PS-PL Interrupt Ports** drop-down.
 </WRAP> </WRAP>
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-{{ vivado:getting_started_with_zynq:zynq-config:interrupts.png?800 |}}+{{ vivado:getting-started-with-ipi:v2019.2:zynq-config-7.png?800 |}}
 </WRAP> </WRAP>
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 In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select **/processing_system7_0/FCLK_CLK0** from the drop-down list. In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select **/processing_system7_0/FCLK_CLK0** from the drop-down list.
 +
 +**Note:** //Selecting "Auto" as the clock source will often work perfectly for simple designs. The section dropdown is highlighted here for users who continue on to create more complex designs with many clocks.//
  
 Click **OK** to continue. Click **OK** to continue.
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 === 4.2 === === 4.2 ===
-In the Board tab, right click on **System Clock** and select **Connect Board Component**.+In the //Board// tab, right click on **System Clock** and select **Connect Board Component**.
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 === 4.3 === === 4.3 ===
-In the **Connect Board Component** dialog make sure that the **clock_CLK_IN1** checkbox under **Create New IP -> Clocking Wizard** is checked.+In the //Connect Board Component// dialog make sure that the **clock_CLK_IN1** checkbox under **Create New IP -> Clocking Wizard** is checked.
  
 Click **OK** to continue. Click **OK** to continue.
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 === 4.4 === === 4.4 ===
-Double click on the newly created clocking wizard block or select it and click the **Customize IP** button ({{vivado:getting-started-with-ipi:v2019.2:buttons:customize-ip.png|}}).+Double click on the newly created clocking wizard block or select it and click the **Customize IP** button ({{vivado:getting-started-with-ipi:v2019.2:button-customize-ip.png|}}).
  
-In the **Board** tab, make sure that **sys clock** is selected in the CLK_IN1 dropdown, then choose **reset** from the **EXT_RESET_IN** drop-down.+In the //Board// tab, make sure that **sys clock** is selected in the CLK_IN1 dropdown, then choose **reset** from the **EXT_RESET_IN** drop-down.
 </WRAP> </WRAP>
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 === 4.5 === === 4.5 ===
-Select the **Output Clocks** tab. On this page there are several different options for how to configure the clocking wizard. For the purposes of this guide, the reset type needs to be configured, and a single 100MHz clock needs to be generated.+Select the //Output Clocks// tab. On this page there are several different options for how to configure the clocking wizard. For the purposes of this guide, the reset type needs to be configured, and a single 100MHz clock needs to be generated.
  
 Make sure that the **clk_out1** box is checked and that it's Requested Frequency is //100.000// (MHz). Make sure that the **clk_out1** box is checked and that it's Requested Frequency is //100.000// (MHz).
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 Depending on how the specific board's reset button works, select **Active Low** or **Active High** for the **Reset Polarity**. The Basys 3 and Cmod A7 are the only boards that use an active high reset polarity at the time of writing. Depending on how the specific board's reset button works, select **Active Low** or **Active High** for the **Reset Polarity**. The Basys 3 and Cmod A7 are the only boards that use an active high reset polarity at the time of writing.
  
-Click **Finish** to save changes and continue.+Click **OK** to save changes and continue.
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 === 4.6 === === 4.6 ===
-In the Board tab, right click on the **USB UART** and select **Connect Board Component**.+In the //Board// tab, right click on the **USB UART** and select **Connect Board Component**.
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 === 4.7 === === 4.7 ===
-In the **Connect Board Component** dialog, make sure to select the **AXI Uartlite** variant of the IP. +In the //Connect Board Component// dialog, make sure to select the **AXI Uartlite** variant of the IP. 
  
 Click **OK** to continue. Click **OK** to continue.
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 === 4.9 === === 4.9 ===
-Click the **Add IP** button ({{vivado:getting-started-with-ipi:v2019.2:buttons:add-ip.png|}}) and search for 'MicroBlaze'. Select **MicroBlaze** from the list of results and press **Enter** on the keyboard to continue.+Click the **Add IP** button ({{vivado:getting-started-with-ipi:v2019.2:button-add-ip.png|}}) and search for 'MicroBlaze'. Select **MicroBlaze** from the list of results and press **Enter** on the keyboard to continue.
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 === 4.11 === === 4.11 ===
-In order to connect the Uartlite and GPIO peripherals to the MicroBlaze block, click **Run Connection Automation**.+In order to connect the Uartlite and GPIO peripherals to the MicroBlaze block, in the green bar at the top of the window, click **Run Connection Automation**.
 Similarly to the Run Block Automation dialog, the pane to the left of the dialog contains a list of things that can be automated. In this case, the AXI connections for axi_gpio_0 and axi_uartlite_0, are available. Similarly to the Run Block Automation dialog, the pane to the left of the dialog contains a list of things that can be automated. In this case, the AXI connections for axi_gpio_0 and axi_uartlite_0, are available.
  
-Check the box next to **All Automation** to make sure that all of three connections will be made.+Check the box next to **All Automation** to make sure that all of the connections will be made.
  
 The clock source for the AXI connection can be changed by selecting the S_AXI entry in the list, and changing the value in the Clock Connection option. Make sure that this option is set to **Auto** or **/clk_wiz_0/clk_out1** for each of the two AXI connections. The clock source for the AXI connection can be changed by selecting the S_AXI entry in the list, and changing the value in the Clock Connection option. Make sure that this option is set to **Auto** or **/clk_wiz_0/clk_out1** for each of the two AXI connections.
- 
-The reset source for the MicroBlaze's reset clocking wizard can be changed by selecting the ext_reset_in entry in the list, and changing the value in the Select Board Part Interface option. Make sure that this option is //not// set to **Custom**. 
  
 Click **OK** to continue. Click **OK** to continue.
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 Click **OK** to continue. Click **OK** to continue.
 +
 +**Note:** //Some Zynq boards may produce critical warnings at this stage relating to the the PS DDR DQS to CLK delay. These are expected and will not affect the functionality of the project. See the Hardware Errata section of the board's resource center for more information.//
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 === 5.2 === === 5.2 ===
-The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the **Sources** tab in the pane to the left of the **Block Design** pane - this pane likely has the **Board** tab currently selected.+The last thing that needs to be done before generating a bitstream is to create a top module file. This file will take the block design and interpret it into a hardware design language so that the synthesis and implementation tools can work properly. Right click on the block design in the //Sources// tab to the left of the //Diagram// - likely the //Board// tab is currently selected.
  
 In the right-click menu, select **Create HDL Wrapper**. In the confirmation dialog that pops up, make sure that //Let Vivado manage wrapper and auto-update// is selected in the options list. If manual changes need to be made to the wrapper file, the other option here can be selected, but it is not recommended except for advanced users. Click **OK** to have Vivado finish making the wrapper file. In the right-click menu, select **Create HDL Wrapper**. In the confirmation dialog that pops up, make sure that //Let Vivado manage wrapper and auto-update// is selected in the options list. If manual changes need to be made to the wrapper file, the other option here can be selected, but it is not recommended except for advanced users. Click **OK** to have Vivado finish making the wrapper file.
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 === 5.6 === === 5.6 ===
-Once the bitstream is generated, which may take a some time, Vivado will ask what to do next. None of the available options are required for this guide, so click **Cancel**.+Once the bitstream is generated, which may take some time, Vivado will ask what to do next. None of the available options are required for this guide, so click **Cancel**.
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 === 7.4 === === 7.4 ===
-In the popup dialog, navigate to and select the exported XSA file, then click **Open**. +In the popup dialog, navigate to and select the exported XSA file, then click **Open**. 
 + 
 +**Note:** //If the Exported Location was left default when exporting the XSA from Vivado, the file can be found in the directory the Vivado project is located in.//
  
 In the New Application Project wizard, make sure that the exported XSA file is selected, then click **Next**. In the New Application Project wizard, make sure that the exported XSA file is selected, then click **Next**.
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 === 7.8 === === 7.8 ===
-Next, a main source file will be created. Right click on the "src" folder of the application project, click **New -> File**+Next, a main source file will be created. In the application project (under the "_system" and project dropdowns), right click on the "src" folder, then click **New -> File**
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 === 7.11 === === 7.11 ===
-Now that the application project has some code associated with it, build it, either by clicking **Project -> Build All** in the menu bar, or by using the **Ctrl-B** hotkey.+Now that the application project has some code associated with it, build it, either by right-clicking on the application project and selecting **Build Project**, or by using the **Ctrl-B** hotkey.
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 === 8.2 === === 8.2 ===
 In Vitis, right click on the application project in the **Explorer**, then select **Run As -> Launch on Hardware (Single Application Debug)**. In Vitis, right click on the application project in the **Explorer**, then select **Run As -> Launch on Hardware (Single Application Debug)**.
 +
 +**Note:** //While this process also programs the bit file into the FPGA, it can also be done manually through the Xilnx -> Program FPGA option in the menu bar at the top of the window.//
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 === 8.3 === === 8.3 ===
-The application is now running on the board! Printed statements can be viewed in the serial terminal application, and the application can be interacted with by pressing the board's buttons.+The application is now running on the board! Printed statements can be viewed in the serial terminal application, and the application can be interacted with by pressing the board's buttons. The sequence of messages in the screenshot on the right was generated by pressing and releasing BTN0.
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