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vivado:getting-started-with-ipi:2018.2 [2020/06/01 20:53] – [9. Receiving Messages over UART] Arthur Brownvivado:getting-started-with-ipi:2018.2 [2023/04/27 17:11] (current) – [Next Steps] James Colvin
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-====== Getting Started with the Vivado IP Integrator ======+====== Getting Started with Vivado IP Integrator and Xilinx SDK ====== 
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 +For the most up to date version of this guide, please visit [[programmable-logic/guides/getting-started-with-ipi|Getting Started with Vivado and Vitis Baremetal Software Projects]]. 
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 + 
  
 {{:vivado:getting_started_with_zynq:zynq-gsg-action.png?800|}} {{:vivado:getting_started_with_zynq:zynq-gsg-action.png?800|}}
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   * **Xilinx Vivado 2018.2 and Digilent Board Files**   * **Xilinx Vivado 2018.2 and Digilent Board Files**
     * //Other versions of Vivado may work, but functionality is not guaranteed//     * //Other versions of Vivado may work, but functionality is not guaranteed//
-    * //See the [[:vivado:installing-vivado:2018.2|Installing Vivado and Digilent Board Files]] tutorial for more information.//+    * //See the [[programmable-logic:guides:installing-vivado-and-sdk|Installing Vivado and Digilent Board Files]] tutorial for more information.//
   * **Serial Terminal Emulator Program**   * **Serial Terminal Emulator Program**
-    *  //See the [[:learn/programmable-logic/tutorials/tera-term|Using a Serial Terminal Emulator]] tutorial for more information.// +    *  //See the [[programmable-logic:guides:serial-terminals:start|Using a Serial Terminal Emulator]] tutorial for more information.//
  
 +**Note:** //If you are using a version of Vivado that includes Vitis (2019.2 or newer), check out [[/programmable-logic/guides/getting-started-with-ipi]]//
 ===== Introduction ===== ===== Introduction =====
  
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 Click **OK** to continue. Click **OK** to continue.
 +
 +**Note:** //Some Zynq boards may produce critical warnings at this stage relating to PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY parameters. These warnings are ignorable and will not affect the functionality of the project. See the Hardware Errata section of your board's reference manual for more information.//
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 === 9.1 === === 9.1 ===
-In order to receive UART messages, which are sent by the 'xil_printf' statements in the project's C source code, it is recommended to use a serial console application like **Tera Term**. The necessary serial port settings are determined by the configuration of the Zynq block or the AXI Uartlite block's customization settings.The process through which the FPGA board's assigned serial port can be determined heavily depends on the OS the connected computer is running - in Windows, review the Device Manager. Review the [[learn:programmable-logic:tutorials:tera-term|Installing and Using a Serial Terminal Emulator]] tutorial for more information.+In order to receive UART messages, which are sent by the 'xil_printf' statements in the project's C source code, it is recommended to use a serial console application like **Tera Term**. The necessary serial port settings are determined by the configuration of the Zynq block or the AXI Uartlite block's customization settings.The process through which the FPGA board's assigned serial port can be determined heavily depends on the OS the connected computer is running - in Windows, review the Device Manager. Review the [[programmable-logic:guides:serial-terminals:start|Installing and Using a Serial Terminal Emulator]] tutorial for more information.
  
 Typically these settings will be **8 Data Bits**, **No Parity Bit**, **1 Stop Bit**, and a baud rate of **115200** for Zynq and **9600** for MicroBlaze by default. Typically these settings will be **8 Data Bits**, **No Parity Bit**, **1 Stop Bit**, and a baud rate of **115200** for Zynq and **9600** for MicroBlaze by default.
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 ==== Next Steps ==== ==== Next Steps ====
  
-Examples of more complicated IPI designs - including examples of the use of DDR memory in MicroBlaze designs - are linked from the target board's resource center, which can be found in [[:reference:programmable-logic:|this list]].+Examples of more complicated IPI designs - including examples of the use of DDR memory in MicroBlaze designs - are linked from the target board's resource center, which can be found in [[programmable-logic:|this list]].
  
  
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