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vivado:getting-started-with-ipi:2018.2 [2018/08/06 23:39] – [9. Receiving Messages over UART] Arthur Brown | vivado:getting-started-with-ipi:2018.2 [2023/04/27 17:11] (current) – [Next Steps] James Colvin | ||
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- | ====== Getting Started with the Vivado IP Integrator ====== | + | ====== Getting Started with Vivado IP Integrator |
+ | <WRAP center round important 60%> | ||
+ | For the most up to date version of this guide, please visit [[programmable-logic/ | ||
+ | </ | ||
+ | |||
{{: | {{: | ||
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* **Xilinx Vivado 2018.2 and Digilent Board Files** | * **Xilinx Vivado 2018.2 and Digilent Board Files** | ||
* //Other versions of Vivado may work, but functionality is not guaranteed// | * //Other versions of Vivado may work, but functionality is not guaranteed// | ||
- | * //See the [[:vivado: | + | * //See the [[programmable-logic:guides: |
* **Serial Terminal Emulator Program** | * **Serial Terminal Emulator Program** | ||
- | * //See the [[FIXME|Using a Serial Terminal Emulator]] tutorial for more information.// | + | * //See the [[programmable-logic: |
+ | **Note:** //If you are using a version of Vivado that includes Vitis (2019.2 or newer), check out [[/ | ||
===== Introduction ===== | ===== Introduction ===== | ||
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In the Run Connection Automation dialog' | In the Run Connection Automation dialog' | ||
- | In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select **/ | + | In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select **/ |
Click **OK** to continue. | Click **OK** to continue. | ||
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Click **OK** to continue. | Click **OK** to continue. | ||
+ | |||
+ | **Note:** //Some Zynq boards may produce critical warnings at this stage relating to PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY parameters. These warnings are ignorable and will not affect the functionality of the project. See the Hardware Errata section of your board' | ||
</ | </ | ||
<WRAP column half> | <WRAP column half> | ||
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<WRAP column half> | <WRAP column half> | ||
=== 9.1 === | === 9.1 === | ||
- | In order to receive UART messages, which are sent by the ' | + | In order to receive UART messages, which are sent by the ' |
Typically these settings will be **8 Data Bits**, **No Parity Bit**, **1 Stop Bit**, and a baud rate of **115200** for Zynq and **9600** for MicroBlaze by default. | Typically these settings will be **8 Data Bits**, **No Parity Bit**, **1 Stop Bit**, and a baud rate of **115200** for Zynq and **9600** for MicroBlaze by default. | ||
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==== Next Steps ==== | ==== Next Steps ==== | ||
- | Examples of more complicated IPI designs - including examples of the use of DDR memory in MicroBlaze designs - are linked from the target board' | + | Examples of more complicated IPI designs - including examples of the use of DDR memory in MicroBlaze designs - are linked from the target board' |
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- | {{tag> | + | {{tag> |