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vivado:getting-started-with-ipi:2018.2 [2019/03/28 19:43] – [Prerequisites] James Colvinvivado:getting-started-with-ipi:2018.2 [2020/06/01 20:53] – [9. Receiving Messages over UART] Arthur Brown
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 In the Run Connection Automation dialog's list pane, make sure that the S_AXI entry is checked and selected. In the Run Connection Automation dialog's list pane, make sure that the S_AXI entry is checked and selected.
  
-In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select **/processing_system7_0/FCLK_CLK0** from the drop-down list.+In the options pane to the right of the dialog, the clock source to run the AXI bus connecting the GPIO IP to the Zynq block can be selected. Select **/processing_system7_0/FCLK_CLK0** from each drop-down list.
  
 Click **OK** to continue. Click **OK** to continue.
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 <WRAP column half> <WRAP column half>
 === 9.1 === === 9.1 ===
-In order to receive UART messages, which are sent by the 'xil_printf' statements in the project's C source code, it is recommended to use a serial console application like **Tera Term**. The necessary serial port settings are determined by the configuration of the Zynq block or the AXI Uartlite block's customization settings.The process through which the FPGA board's assigned serial port can be determined heavily depends on the OS the connected computer is running - in Windows, review the Device Manager. Review the [[FIXME|Installing and Using a Serial Terminal Emulator]] tutorial for more information.+In order to receive UART messages, which are sent by the 'xil_printf' statements in the project's C source code, it is recommended to use a serial console application like **Tera Term**. The necessary serial port settings are determined by the configuration of the Zynq block or the AXI Uartlite block's customization settings.The process through which the FPGA board's assigned serial port can be determined heavily depends on the OS the connected computer is running - in Windows, review the Device Manager. Review the [[learn:programmable-logic:tutorials:tera-term|Installing and Using a Serial Terminal Emulator]] tutorial for more information.
  
 Typically these settings will be **8 Data Bits**, **No Parity Bit**, **1 Stop Bit**, and a baud rate of **115200** for Zynq and **9600** for MicroBlaze by default. Typically these settings will be **8 Data Bits**, **No Parity Bit**, **1 Stop Bit**, and a baud rate of **115200** for Zynq and **9600** for MicroBlaze by default.