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reference:zmod:zmoddac:zmod_dac_ip_core_user_guide [2019/11/21 00:24]
Arthur Brown Add links to references section
reference:zmod:zmoddac:zmod_dac_ip_core_user_guide [2019/11/21 22:52] (current)
Arthur Brown
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-Each output bit of the calibration stage is connected to an ODDR primitive which formats the output data according to the AD9717 requirements [(Analog Devices, AD9646 Datasheet, Rev C.)]. The two input channels are multiplexed on a 200 MSPS 14 bit parallel bus.+Each output bit of the calibration stage is connected to an ODDR primitive which formats the output data according to the AD9717 requirements [[#​references|Reference 3]]. The two input channels are multiplexed on a 200 MSPS 14 bit parallel bus.
  
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 ==== 4. Configuration State Machine ==== ==== 4. Configuration State Machine ====
  
-The configuration state machine sends a predefined sequence of SPI commands to the Zmod’s AD9717, performing the device’s initialization. Once the sequence is executed, the state machine enters the idle state where it monitors if there is any valid data on the upper level SPI command interface. After executing any requested SPI transfers, the state machine passes the received SPI data (for read commands) and returns to the idle state. The initial configuration command sequence is listed below. After configuring each register, the register data is read back and checked against the expected value in order to determine any SPI transaction error. For more details about configuration registers details please consult [(1)].+The configuration state machine sends a predefined sequence of SPI commands to the Zmod’s AD9717, performing the device’s initialization. Once the sequence is executed, the state machine enters the idle state where it monitors if there is any valid data on the upper level SPI command interface. After executing any requested SPI transfers, the state machine passes the received SPI data (for read commands) and returns to the idle state. The initial configuration command sequence is listed below. After configuring each register, the register data is read back and checked against the expected value in order to determine any SPI transaction error. For more details about configuration registers details please consult [[#​references|Reference ​1]].
   - FIXME**SPI Control register**: Set software reset (Address: 00h; Data: 20h)   - FIXME**SPI Control register**: Set software reset (Address: 00h; Data: 20h)
   - FIXME **SPI Control register**: Release software reset (Address: 00h; Data: 00h)   - FIXME **SPI Control register**: Release software reset (Address: 00h; Data: 00h)