Zmod DAC 1411 Low Level Controller IP Core User Guide

This user guide describes the Digilent Zmod DAC 1411 Low Level Controller Intellectual Property. This IP interfaces directly with the Zmod DAC 1411 initializing the hardware and multiplexing two input channels on a single double data rate (DDR) channel as requested by the AD9717 digital to analog converter (DAC) featured by the Zmod DAC 1411. The Zmod DAC 1411 Low Level Controller is intended to be used as a stand-alone IP in projects that do not require processor interaction (stand alone mode) or it can be used in conjunction with the Digilent Zmod DAC1411 AXI Adapter IP that provides connectivity with the processing system.

• Initializes the hardware on the Zmod ADC 1411.
• Formats the data received on two single data rate (SDR) channels according to the Zmod DAC 1411 requirements.
• Provides the possibility of overwriting the initial DAC configuration by providing an optional upper level interface that allows indirect access to the DAC’s SPI interface.
• Performs offset and gain calibration based on coefficients specified by the user/upper level IPs.

The IP is designed to generate two 100 MHz clock signals for the Zmod DAC 1411’s DAC, one used to qualify the input data, one used as sample clock and to generate output data at 200 MSPS on a 14 bit DDR parallel bus as required by the DAC. The IP core has two SDR input data channels which are synchronous to the system clock input (100 MHz) that the IP core requires.

The following image shows the structure of the IP Core.

The main functionalities are divided as DAC input clock generation, data formatting and calibration (data path) and Zmod DAC 1410 configuration (two items related with configuration functionalities will be detailed separately: the configuration state machine and the SPI controller).

The IP outputs two 100 MHz clocks (DCLKIO, CLKIN). DCLKIO is used by the AD9717 DAC to qualify the input data, while CLKIN is the DAC’s sampling clock. As inputs, the IP requires two 100 MHz clock signals: SysClk and DacClk. DacClk needs to be 90 degrees phase shifted in relation with SysClk and it is used to generate DCLKIO.

The data path consists of two stages. The first stage is responsible with applying the multiplicative and additive calibration coefficients to both channels, compensating for the Zmod DAC 1411 DAC output filter tolerances. The calibration coefficients can be introduced as IP parameters or can be passed through (optional) external ports, depending on whether the core is used in the stand alone mode or it is connected to the processing system through the Zmod DAC 1411 AXI adapter IP core. The user should run the to be determined executable to obtain the calibration parameters if the IP is used in the stand alone mode.

$$ChxODDR=ChxIn*CoefxMult_{LH/HG}+CoefxAdd_{LG/HG}\tag{1}$$

In the previous relation, the IP core’s data input channels are labeled ChxIn, the calibration stage outputs are labeled ChxODDR while CoefxMult_{LH/HG} and CoefxAdd_{LG/HG} represent the gain and offset calibration coefficients.

The following image shows the DAC data formatting.

Each output bit of the calibration stage is connected to an ODDR primitive which formats the output data according to the AD9717 requirements Reference 3. The two input channels are multiplexed on a 200 MSPS 14 bit parallel bus.

The IP core provides the choice of selecting the Zmod DAC 1411 scale options statically or dynamically. For static configuration, the ExtScaleEn needs to be set as “false” and the scale configuration parameters (See Table 3) need to be configured in the IP core GUI. For dynamic scale control, the ExtScaleEn needs to be set as “true” and the external scale control ports will become available.

The configuration state machine sends a predefined sequence of SPI commands to the Zmod’s AD9717, performing the device’s initialization. Once the sequence is executed, the state machine enters the idle state where it monitors if there is any valid data on the upper level SPI command interface. After executing any requested SPI transfers, the state machine passes the received SPI data (for read commands) and returns to the idle state. The initial configuration command sequence is listed below. After configuring each register, the register data is read back and checked against the expected value in order to determine any SPI transaction error. For more details about configuration registers details please consult Reference 1.

1. SPI Control register: Set software reset (Address: 00h; Data: 20h)
2. SPI Control register: Release software reset (Address: 00h; Data: 00h)
3. Data Control Register: Configuration selected: 2’s complement, IDATA latched on DCLKIO rising edge, I first of pair on data input pads, data clock input enable, data clock output disable (Address: 02h; Data: B4h)
4. CLKMODE Register: Clear the reacquire bit (Address: 14h; Data: 00h)
5. CLKMODE Register: Set (toggle) the require bit (Address: 14h; Data: 00h)
6. CLKMODE Register: Clear the reacquire bit (Address: 14h; Data: 00h)

The SPI controller is designed to carry out basic register access over the AD9717’s SPI interface. Only single byte data transfers are currently supported. More details about the AD9717’s SPI interface can be found in [Reference 3]. The SPI controller’s ports are described below.

The IP operates in a two clock domain. The system clock (SysClk) clocks all logic except the output clock generation blocks. All output clocks being derived from the 100 MHz input DacClk. The IP does not constrain any of the input clocks, therefore it needs to be constrained in the top-level design either manually or by relying on the auto-derived constraints, if using clock modifying blocks. For more information see [4].

The table below shows the IP core parameter descriptions.

The IP through its customizable parameters (ExtScaleConfigEn , ExtCalibEn, ExtCmdInterfaceEn) enables the user to opt for a more basic design, with minimal external ports or a more configurable but also more complex design with several ports that enable dynamic configuration of several hardware features. When using the IP Core with the Zmod DAC 1411 AXI adapter, the hardware configuration features are expected to be controlled by the processing system, so all interfaces should be enabled and connected to the upper layer IP Core.

The following documents provide additional information on the subjects discussed:

1. Xilinx Inc., UG471: 7 Series FPGAs SelectIO Resources, v1.4, May 13, 2014.
2. Xilinx Inc., UG472: 7 Series FPGAs Clocking Resources, v1.6, October 2, 2012
3. Analog Devices, AD9646 Datasheet, Rev C.
4. Xilinx Inc., UG903: Using Constraints, v2014.3, October 31, 2014