Vivado Version 2014.4 and Earlier Board File Installation

Board Files: here


This guide will help you obtain Vivado Board Files for the Nexys 4, Nexys 4 DDR, Basys 3, Arty, Nexys Video, and Zybo FPGA Boards.

What you need before proceeding with this guide

  • Xilinx Vivado 2014.4 or earlier.

Follow this Wiki guide on how to install and activate Vivado on your PC. Installing Vivado

What are Board Files and why do you need them

After installing Vivado, the default installation directory on your drive will contain a folder called board_parts. If Vivado is installed in the C drive ( usually recommended ), then the board_parts folder can be found here: C:\Xilinx\Vivado\201X.X\data\boards.

By default this folder contains XML files for different FPGA boards manufactured by Xilinx.

XML files define different interfaces on the board. Interfaces such as Slide Switches, Push Buttons, LEDs, USB-UART, DDR Memory, Ethernet etc.

Digilent has created XML files for the Artix 7 FPGA boards:

  • Basys 3
  • Nexys 4
  • Nexys 4 DDR
  • Arty
  • Nexys Video
  • Zybo

In the AXI GPIO IP customization window, you will be able to assign different interfaces that are available on your selected board to a specific GPIO IP block.


Download and extract this Zip file:
You can also check out the repository for the board files on github located here

This zip file will contain a folder called board_parts. Save this in your user documents folder. We will copy this board_parts folder, navigate to the board_parts folder inside the Vivado Installation directory, and merge them both.

  • Copy the contents of the old/board_parts folder
  • Navigate to the board_parts folder in the Vivado Installation directory (C:\Xilinx\Vivado\201X.X\data\boards\board_parts)
  • Paste the contents into the board_parts folder (Merge the artix7 folders)
  • Restart Vivado

The newly added files will each contain a sub-folder for the current board revision. This sub-folder contains the respective XML files for each FPGA board.

The sub-folder for the nexys4_ddr will contain an additional file called mig.prj which is the Xilinx Memory Interface Generator description file for customizing the DDR2 component on the Nexys 4 DDR.

You are now ready to start a new IP Integrator based Vivado project for the Digilent Nexys 4, Nexys 4 DDR and Basys 3 FPGA Boards.