Virtex-II Pro

Store Reference Manual Technical Support
Virtex-II Pro
Development System
Custom header
A custom Header
is super convenient
Alt Design Resources
XDC
github link
Vivado Design Resources
Alt Documentation
Reference manual
link
Schematic
link
Key Specifications
Logic Cells
30,816
BRAM
2,448Kb
DDR
Up to 2GB of DDR SDRAM
Ethernet
On-board 10/100 Ethernet PHY
Clocks
100MHz system clock, 75MHz SATA
Connectivity and Onboard I/O
Pmod Connectors
3
Switches
16
Buttons
5
User LED
16
7-Seg Display
4-Digit
VGA
12-bit
USB
HID Host (KB/Mouse/Mass Storage)
Electrical
Power
4.5-5.5V
Logic Level
3.3V
Physical
Width
x in
Length
y in
Features
  • On-chip analog-to-digital converter
Connectivity and On-board I/O
RS-232
RS-232 DB9 serial port
PS/2
Two PS-2 serial ports
Audio
AC-97 audio CODEC with audio
amplifier and speaker/headphone
output and line level output
Microphone
Microphone and line
level audio input
Video
On-board XSGA output, up to
1200 x 1600 at 70Hz refresh
Switches
4
Push-buttons
5
LEDs
4 LEDs
User LED
4
User RGB LED
4
Design Resources
Master UCF
Documentation
Primary IC
Virtex-II Pro (XC2VP30)
Schematic
Base System Builder Guide
User Guide

The Virtex-II Pro (V2-Pro) development system can be used at virtually any level of the engineering curricula, from introductory courses through advanced research projects. Based on the Virtex-II Pro FPGA, the board can function as a digital design trainer, a microprocessor development system, or a host for embedded processor cores and complex digital systems. It is powerful enough to support advanced research projects, but affordable enough to be placed at every workstation. The expansion connectors can accommodate special-purpose circuits and systems for years to come, so the board can remain at the core of an engineering educational program indefinitely (see below for a current list of available expansion boards).

NOTE: EDK version 9.2 Base System Builder does not fully support the V2Pro board. We recommend using EDK Version 9.1 or the newer Version 10.1. The V2Pro is a mature product. 10.1 Service Pack 3 supports this product except for the 512MB DIMM. Future Xilinx EDK versions will not.



Tutorials


Example Projects


Additional Resources


Demo Projects
  • Edge Detection – ZIP
  • Ethernet MAC OneWire – ZIP
  • OneWire – ZIP
  • PS2 – ZIP
  • MicroBlaze uClinux – ZIP
VGA
  • VGA SlideShow (with 256MB RAM) – ZIP
  • 512 MB Dual Rank DDR Memory with VGA controller – ZIP
  • 512 MB Single Rank DDR Memory with VGA controller – ZIP
  • 256 MB Single Rank DDR Memory with VGA controller – ZIP
Built In Projects
  • Built in Self Test (BIST) – ZIP
  • Built In Demo – ZIP

Demonstration Projects

  • Video Capture (with VDEC1) – ZIP
  • XUP-V2Pro Pack – ZIP
  • Using High Speed Serial MGTs with the Aurora IP – ZIP
  • JTAG Hardware CoSIm with System Generator for DSP – ZIP