Virtex-5 OpenSPARC

Store Reference Manual Technical Support
Virtex-5 OpenSPARC
Evaluation Platform (ML509)
Custom header
A custom Header
is super convenient
Alt Design Resources
XDC
github link
Vivado Design Resources
Alt Documentation
Reference manual
link
Schematic
link
Key Specifications
PROMs
2 XCF32P Platform Flash
(32Mbyte each)
SRAM
1 MByte On-board 32-bit ZBT
Flash
32 MByte Intel P30 StrataFlash
DDR2
64-bit wide 256Mbyte
Clocks
One 100MHz oscillator
Ethernet
One 10/100/1000 Ethernet
supporting MII, GMII, RGMII,
and SGMII interfaces
Connectivity and Onboard I/O
Pmod Connectors
3
Switches
16
Buttons
5
User LED
16
7-Seg Display
4-Digit
VGA
12-bit
USB
HID Host (KB/Mouse/Mass Storage)
Electrical
Logic Level
3.3V
Physical
Width
x in
Length
y in
Features
  • JTAG programming interface
Connectivity and On-board I/O
Display
16×2 character LCD
USB
2 USB
Video
Video input, DVI/VGA output
Audio
Stereo AC97 codec with line in,
line out, headphone, microphone,
and SPDIF digital audio jacks
RS-232
RS-232 (Male) port
Switches
8 DIP switches
Push-buttons
5
LEDs
8
Design Resources
Master UCF
Documentation
Primary IC
Virtex-5 (XC5VLX110T)
Schematic
User Guide

The Virtex®-5 OpenSPARC Evaluation Platform is a powerful system for hosting the OpenSPARC T1 open-source microprocessor. Equivalent to the Xilinx® ML509 board and based on the Xilinx XUPV5-LX110T FPGA, this kit brings the throughput of OpenSPARC Chip Multi-Threading to an FPGA.

OpenSPARC T1 is the open-sourced version of the custom designed UltraSPARC T1 microprocesor from Sun Microsystems. To broaden the appeal of this state-of-the-art Chip Multi-threading (CMT) technology to the developers, engineers at Sun Microsystems and Xilinx Inc. have developed a reference design that allows a scaled-down version of the OpenSPARC T1 processor to run on Xilinx Virtex-5 FPGAs. This reference design is an excellent starting point for researchers and entrepreneurs to build and test novel ideas in the areas of computer architecture, logic design, parallel programming, and compiler techniques, among others. For more details on how to download the OpenSPARC design and the reference design, please visit www.opensparc.net/fpga.



Tutorials


Example Projects


Additional Resources


  • Virtex-5 Family Overview – PDF
  • Getting Started Tutorial – PDF