Spartan-3E

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Spartan-3E
Starter Board
Custom header
A custom Header
is super convenient
Alt Design Resources
XDC
github link
Vivado Design Resources
Alt Documentation
Reference manual
link
Schematic
link
Key Specifications
Logic Cells
over 10,000
PROM
4 Mbit Platform Flash configuration
DDR SDRAM
64 MByte, x16 data interface,
100+ MHz
NOR Flash
16 MByte (Intel StrataFlash)
SPI Serial Flash
16 MBits (STMicro)
Ethernet
10/100 PHY
(requires Ethernet MAC in FPGA)
Oscillator
50 MHz clock oscillator
Connectivity and Onboard I/O
Pmod Connectors
3
Switches
16
Buttons
5
User LED
16
7-Seg Display
4-Digit
VGA
12-bit
USB
HID Host (KB/Mouse/Mass Storage)
Electrical
Power
Universal power supply
100-240V, 50/60 Hz
Logic Level
3.3V
Physical
Width
6.0 in
Length
7.0 in
Features
  • Four-output, SPI-based Digital-to-Analog Converter (DAC)
  • Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable gain pre-amplifier
Connectivity and On-board I/O
Pmod Connectors
3 6-pin Pmod Ports
LCD
2-line, 16-character LCD screen
PS/2
1 PS/2 mouse or keyboard port
VGA
1 VGA port
FX2
Hirose FX2 expansion connector
RS-232
2 9-pin RS-232 ports
(DTE- and DCE-style)
DIP
8-pin DIP socket for
auxiliary clock oscillator
Switches
4 slide switches
Buttons
4
LEDs
8 discrete LEDs
Design Resources
Documentation
Primary IC
Spartan-3E (XC3S500E)
User Guide
Schematic

The Spartan-3E Starter Board provides a powerful and highly advanced self-contained development platform for designs targeting the Spartan-3E FPGA from Xilinx. It features a 500K gate Spartan-3E FPGA with a 32-bit RISC processor and DDR interfaces.



Tutorials


Example Projects


Additional Resources

Reference Designs
  • Active Power Meter reference design – ZIP
  • BRAM Configuration reference design – ZIP
  • RS232 example reference design – ZIP
  • VGA controller reference design – ZIP
Reference Components
  • PS2 Mouse Control reference component – ZIP
  • PS2 Mouse Displayer reference component – ZIP
  • RS232 interface reference component*– ZIP
  • Pulse-width modulation reference component – ZIP