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reference:programmable-logic:nexys-video:reference-manual [2017/10/24 22:50]
Arthur Brown
reference:programmable-logic:nexys-video:reference-manual [2018/07/10 09:00] (current)
Elod Gyorgy [4. Ethernet PHY]
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 The on-board PHY implements Layer 1 in the Ethernet stack, interfacing between the physical copper medium and the media access control (MAC). The MAC must be implemented in the FPGA and mapped to the PHY's RGMII interface. Vivado-based designs can use the Xilinx AXI Ethernet Subsystem IP core to implement the MAC and wire it to the processor and the memory subsystem. At the time of writing, the IP core needed to be licensed separately with Xilinx part number EF-DI-TEMAC-PROJ or EF-DI-TEMAC-SITE. A free evaluation of this core is available, however, the design will stop working after running for approximately 8 hours. The on-board PHY implements Layer 1 in the Ethernet stack, interfacing between the physical copper medium and the media access control (MAC). The MAC must be implemented in the FPGA and mapped to the PHY's RGMII interface. Vivado-based designs can use the Xilinx AXI Ethernet Subsystem IP core to implement the MAC and wire it to the processor and the memory subsystem. At the time of writing, the IP core needed to be licensed separately with Xilinx part number EF-DI-TEMAC-PROJ or EF-DI-TEMAC-SITE. A free evaluation of this core is available, however, the design will stop working after running for approximately 8 hours.
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 +The RGMII interface requires a data to clock skew of 1.0-2.6 ns at the receiver: at the FPGA for ETH_RX* and at the PHY for ETH_TX*. The PCB traces do not introduce the required skews. Consequently,​ either the PHY or the MAC IP in the FPGA has to introduce them. The PHY may be configured by moving resistors R88 to R83 (RXDLY) and R79 to R72 (TXDLY). This will have the effect of adding 2 ns.
  
 On an Ethernet network each node needs a unique MAC address. To this end a Microchip 24AA025E48 EEPROM is provided on the Nexys Video. On one hand it is a read-writeable EEPROM that can be accessed via I2C. On the other hand it features a read-only memory section that comes pre-programmed with a unique identifier. This unique identifier can be read and used as a MAC address, avoiding a possible address conflict on the network. The device address of the EEPROM is 1010000b. The out-of-box Ethernet demo uses the unique MAC to allow connecting several Nexys Video boards to the same network. On an Ethernet network each node needs a unique MAC address. To this end a Microchip 24AA025E48 EEPROM is provided on the Nexys Video. On one hand it is a read-writeable EEPROM that can be accessed via I2C. On the other hand it features a read-only memory section that comes pre-programmed with a unique identifier. This unique identifier can be read and used as a MAC address, avoiding a possible address conflict on the network. The device address of the EEPROM is 1010000b. The out-of-box Ethernet demo uses the unique MAC to allow connecting several Nexys Video boards to the same network.