Nexys Video OLED Demo

Under Construction


The OLED Demo project demonstrates a simple usage of the Nexys Video's Organic Light Emitting Diode (OLED) Display.

Button Function
BTNC With the display on, each pixel on the display can
be lit up at once by pressing the center D-Pad button (BTNC).
Press the BTNC to return the display to its original state
BTNU With the display on, you can load pre-defined text onto the
display by pressing the up D-Pad button (BTNU)
CPU_RESET The OLED display can be turned on and off by pressing the right
D-Pad Button (CPU_RESET)
BTND To clear the display, press the down D-Pad button (BTND)


Download and Usage Instructions

First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.

The latest release version for this demo is highlighted in green.

Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Board Variant Release Tag Release Downloads Setup Instructions
Nexys Video OLED/2020.1-1 Release ZIP Downloads See Using the Latest Release, below
Nexys Video v2018.2-1 Release ZIP downloads v2018.2-1 Github README
Nexys Video v2016.4-2 Release ZIP downloads Using Digilent Github Demo Projects (Legacy)

Note for Advanced Users: All demos for the Nexys Video are provided through the Nexys Video repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

Note: This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.

Important: These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.

First, download and extract the '*' file from the demo release page, linked above.

Open a Vivado Project from a Release
Launch Vivado

Select the dropdown corresponding to your operating system, below.


Open Vivado through the start menu or desktop shortcut created during the installation process.


Open a terminal, and change directory (cd) to a folder where log files for your Vivado session can be placed, then run the following commands:

source <install_path>/Vivado/<version>/

In Vivado's welcome screen, use the Open Project button to navigate to and open the XPR file contained in the folder the release was extracted into.

Build a Vivado Project
Generate a Bitstream

In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.

This starts with Synthesis. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click either in the toolbar or in the Flow Navigator. The output of Synthesis is then passed to Implementation.

Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either in the toolbar or in the Flow Navigator. This output is then passed on to the Bitstream Generator.

The Bitstream Generator generates the final output file needed for programming the FPGA. To run Bitstream Generation click either in the toolbar or in the Flow Navigator. With no settings changed, the generator will create a '.bit' file.

Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so click Cancel. The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.

Set up the Nexys Video
Plug the 12V Power Supply into the Nexys Video.

Plug the MicroUSB into the PROG port.

Program a Bitstream onto an FPGA Board

Vivado's Hardware Manager can be opened by clicking on Open Hardware Manager at the bottom of the Flow Navigator pane on the left side of the Vivado window.

The first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to the Open Hardware Target wizard click the link in the green banner near the top of the window. From the drop-down that opens, select .

Once the wizard opens, click Next.

The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the Host Name and Port fields.

Click Next to continue.

This screen gives a list of devices connected to the hardware server. If there is only one connected it will be the only device shown.

Click Next to continue.

The final screen shows a summary of the options selected in the wizard. Verify the information and click Finish. The board is now connected to the hardware server.

To program the device with the bit file generated earlier, either click the link in the green banner at the top of the window or click the button in the Flow Navigator under . From the drop-down that opens, select the device to program (Example: ) and the following window will open:

The Bitstream File field should be automatically filled in with the bit file generated earlier. If not, click the button at the right end of the field and navigate to
<Project Directory>/<Project Name>.runs/impl_1/ and select the bit file (Example: ). Now click Program. This will connect to the board, clear the current configuration, and program it using the new bit file.

At this point, the demo is now running on your board. Refer to the Description and Functionality sections of this document for more information on what it does.


This portion will help you run the demo and observe all its features.

1) Startup and Bringdown

The procedures for safely turning on and off the OLED display are handled by the CPU Reset Button. When the board is first turned on, the display is off, and must be brought up, press the CPU Reset Button to turn it on. Once the display is on, when you are done operating the demo, and want to turn your board off, press the CPU Reset Button again to turn the display off. The status of the display is indicated by LED0, if it is on, the display is on.

2) Toggle the Display

Once the display has been turned on, each LED on the display can be lit up at once by pressing the center D-Pad button. To return the display to its original state, press this button again.

3) Update the Display

With the display on, you can load text onto the display by pressing the up D-Pad button. To clear the display again, press the down D-Pad button. Toggling the entire display while text is loaded will still turn each LED on, then return the display to the splash screen text.


Before turning off or reprogramming your board, shut down the OLED display by pressing the CPU_RESET button.

Additional Resources

All materials related to the use of the Nexys Video can be found on its Resource Center.

For a walkthrough of the process of creating a simple HDL project in Vivado, see Getting Started with Vivado for Hardware-Only Designs. Information on important parts of the GUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum.

{{tag>project nexys-video}}