- Micro USB Connector for JTAG programming and debugging (shared with USB-UART interface)
- Xilinx CPLD XC2C512 for FPGA configuration from parallel flash
64-bit wide buses at 850MHz
36-bit wide buses at 500MHz
(6gbps via GTH transceivers)
parallel flash modules
transceivers and 68 user I/Os)
on-board I2C buses
Express Auxiliary Power Connector
Powered by Xilinx's Virtex-7 XC7V690T FPGA, the NetFPGA-SUME is an ideal platform for high-performance and high-density networking design.
32 GTH serial transceivers have been used to provide access to 8 lanes of end-point PCI-E (Gen3 x8), 4 SFP+ (10Gbps) ports, 2 SATA-III ports (6Gbps), and 18 data-rate-adjustable GTH ports through a HPC-FMC connector and a QTH connector.
Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications.
The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found here. Academic institutes can make a request to the Xilinx University Program for a donation of full Vivado licenses here.