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reference:programmable-logic:genesys-zu:reference-manual [2020/01/10 14:52]
Elod Gyorgy [Software Support] Added IP support table
reference:programmable-logic:genesys-zu:reference-manual [2020/08/17 19:30] (current)
Arthur Brown [10. Expansion Ports]
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 The black matte board you are holding in your hand is a prototyping and evaluation board proudly designed by Digilent. At its heart is a Xilinx Zynq UltraScale+ MPSoC ARM-FPGA hybrid, coupled with upgradeable memory, network and multimedia interfaces, and a wide variety of expansion connectors making it a versatile computing platform. The black matte board you are holding in your hand is a prototyping and evaluation board proudly designed by Digilent. At its heart is a Xilinx Zynq UltraScale+ MPSoC ARM-FPGA hybrid, coupled with upgradeable memory, network and multimedia interfaces, and a wide variety of expansion connectors making it a versatile computing platform.
  
-Available in two variants3EG and 5EVdifferentiated by the MPSoC model and some peripherals. ​If the fan sticker says 5EV, on top of 3EG you get slightly faster DDR4, more FPGA, video codec and GTH transceivers allowing HDMI Source, Sink and SFP+ 10G.+There are two variants ​of the Genesys ZU mentioned in this Reference Manual: ​3EG and 5EV. (**The 5EV is not yet released.)** These two variants are differentiated by the MPSoC model and some peripherals. ​As compared to the 3EG, with the 5EV you get slightly faster DDR4, more FPGA, video codecand GTH transceivers allowing HDMI Source, Sink and SFP+ 10G.
  
 Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it straight up boots Linux from the microSD card. Connect the USB micro B cable to a PC and open a terminal (115200-8-N-1) to the first COM port out of the two that appear. Login and password are both "​root"​. The red button labeled "​POR"​ always resets the MPSoC and starts the boot process again. ​ Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it straight up boots Linux from the microSD card. Connect the USB micro B cable to a PC and open a terminal (115200-8-N-1) to the first COM port out of the two that appear. Login and password are both "​root"​. The red button labeled "​POR"​ always resets the MPSoC and starts the boot process again. ​
  
-Want to dive deep into development?​ Head over to our [[https://​github.com/​Digilent|GitHub page]] and use the repos there as a starting point. Build your own boot image on the SD card and boot it like the OOB demo. Not enough? Connecting the JTAG-HS1/​HS2 cable to header J28 will allow for on-the-fly programming and debug using Xilinx Vivado and SDK.+Want to dive deep into development?​ Head over to our [[https://​github.com/​Digilent|GitHub page]] and use the repos there as a starting point. Check out our [[reference:​programmable-logic:​genesys-zu:​getting-started|Getting Started Guide]] for a step-by-step. Build your own boot image on the SD card and boot it like the OOB demo. Not enough? Connecting the JTAG-HS1/​HS2 cable to header J28 will allow for on-the-fly programming and debug using Xilinx Vivado and SDK.
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 The Digilent Genesys ZU is a stand-alone Zynq UltraScale+ MPSoC prototyping and development board. It is an advanced computing platform with powerful multimedia and network connectivity interfaces. The excellent mix of on-board peripherals,​ upgrade-friendly DDR4, Mini PCIe and microSD slots, multi-camera and high-speed expansion connectors are bound to support a wide number of use-cases. Furthermore,​ the Genesys ZU is available in two variants with different MPSoC options and additional features for even more flexibility. Differences are <wrap hi>​highlighted*</​wrap>​ throughout this document. The Digilent Genesys ZU is a stand-alone Zynq UltraScale+ MPSoC prototyping and development board. It is an advanced computing platform with powerful multimedia and network connectivity interfaces. The excellent mix of on-board peripherals,​ upgrade-friendly DDR4, Mini PCIe and microSD slots, multi-camera and high-speed expansion connectors are bound to support a wide number of use-cases. Furthermore,​ the Genesys ZU is available in two variants with different MPSoC options and additional features for even more flexibility. Differences are <wrap hi>​highlighted*</​wrap>​ throughout this document.
  
-The Xilinx Zynq UltraScale+ MPSoC at the heart of the Genesys ZU is a big leap from the Zynq-7000 series. Faster and more processor cores, upgraded memory interface, integrated gigabit transceivers bring support for DDR4, USB Type-C 3.1, PCIe, SATA, DisplayPort,​ <wrap hi>​SFP+*</​wrap>​ and <wrap hi>​HDMI*</​wrap>​. The Genesys ZU is primarily targeted towards Linux-based applications that allows easy access to Wi-Fi, cellular radio (WWAN), SSD, USB SuperSpeed and 4K video. The bundled microSD card includes an out-of-box demo that boots a Linux image built in Petalinux and includes some test scripts for some of the peripherals.+The Xilinx Zynq UltraScale+ MPSoC at the heart of the Genesys ZU is a big leap from the Zynq-7000 series. Faster and more processor cores, upgraded memory interface, integrated gigabit transceivers bring support for DDR4, USB Type-C 3.1, PCIe, SATA, DisplayPort,​ <wrap hi>​SFP+*</​wrap>​ and <wrap hi>​HDMI*</​wrap>​. The Genesys ZU is primarily targeted towards Linux-based applications that allows easy access to Wi-Fi, cellular radio (WWAN), ​<​nowiki>​SSD</​nowiki>​, USB SuperSpeed and 4K video. The bundled microSD card includes an out-of-box demo that boots a Linux image built in Petalinux and includes some test scripts for some of the peripherals.
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 | :::                      | SFP+ 10G Ethernet ​                    ​| ​ ✘                                      |  ✔                                      |  ✘                                 | | :::                      | SFP+ 10G Ethernet ​                    ​| ​ ✘                                      |  ✔                                      |  ✘                                 |
 | Storage ​                 | SD                                    |  104 MB/s                                                                        ||  25 MB/s                           | | Storage ​                 | SD                                    |  104 MB/s                                                                        ||  25 MB/s                           |
-| :::                      | SSD                                   ​|  option - mSATA                                                                  ||  ✘                                 |+| :::                      | <​nowiki>​SSD</​nowiki> ​                 ​|  option - mSATA                                                                  ||  ✘                                 |
 | :::                      | Flash                                 ​| ​ ISSI 256 Mib SNOR                                                               ​|| ​ 128 Mib                           | | :::                      | Flash                                 ​| ​ ISSI 256 Mib SNOR                                                               ​|| ​ 128 Mib                           |
 | Multimedia ​              | DisplayPort ​                          ​| ​ 1.2a Dual-Lane ​                                                                 ||  ✘                                 | | Multimedia ​              | DisplayPort ​                          ​| ​ 1.2a Dual-Lane ​                                                                 ||  ✘                                 |
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 | 7          | Audio jacks                   | 19         | User buttons ​                   |            |                                       | | 7          | Audio jacks                   | 19         | User buttons ​                   |            |                                       |
 | 8          | Boot mode select jumper ​      | 20         | MIPI (Pcam) connectors ​         |            |                                       | | 8          | Boot mode select jumper ​      | 20         | MIPI (Pcam) connectors ​         |            |                                       |
-| 9          | Reset buttons ​                | 21         | Wireless and SSD activity LEDs  |            |                                       |+| 9          | Reset buttons ​                | 21         | Wireless and <​nowiki>​SSD</​nowiki> ​activity LEDs  |            |                                       |
 | 10         | INIT, DONE, ERR and STS Leds  | 22         | MicroSD Card Slot               ​| ​           |                                       | | 10         | INIT, DONE, ERR and STS Leds  | 22         | MicroSD Card Slot               ​| ​           |                                       |
 | 11         | Zmod (SYZYGY) connector ​      | 23         | Mini DisplayPort ​               |            |                                       | | 11         | Zmod (SYZYGY) connector ​      | 23         | Mini DisplayPort ​               |            |                                       |
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 In the kit you will also find a free voucher for the Xilinx MIPI CSI-2 IP cores. Follow the instructions on the voucher slip to activate the license. This is a temporary measure until Vivado 2020.1 hits, which should include a license for these IPs free of charge. See the next table for IP-support status for other peripherals. In the kit you will also find a free voucher for the Xilinx MIPI CSI-2 IP cores. Follow the instructions on the voucher slip to activate the license. This is a temporary measure until Vivado 2020.1 hits, which should include a license for these IPs free of charge. See the next table for IP-support status for other peripherals.
-^ Feature/​Peripheral ​            ​^ IP support ​                                                                                                                                    | Version  ​| + 
-| DDR4 memory controller ​        ​| PS hard-core, WebPACK built-in ​                                                                                                                ​| 2019.1 ​  | +//Table I: IP support status// 
-| MIPI CSI-2/​Pcam ​               | PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​ef-di-mipi-csi-rx.html|MIPI CSI Controller Subsystems],​ bundled voucher ​ | 2019.1 ​  | +^ Feature/​Peripheral ​                    ​^ IP support ​                                                                                                                                     ​^ ​Version  ​^ 
-| DisplayPort controller ​        ​| PS hard-core, WebPACK built-in ​                                                                                                                ​| 2019.1 ​  | +| DDR4 memory controller ​                ​| PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
-| Ethernet 1G                    | PS hard-core, WebPACK built-in ​                                                                                                                ​| 2019.1 ​  | +| MIPI CSI-2/​Pcam ​                       | PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​ef-di-mipi-csi-rx.html|MIPI CSI Controller Subsystems]], bundled voucher ​ | 2019.1 ​  | 
-| USB 2.0/​3.0 ​                   | PS hard-core, WebPACK built-in ​                                                                                                                ​| 2019.1 ​  | +| DisplayPort controller ​                ​| PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
-| On-board Wi-Fi/SPI controller ​ | PS hard-core, WebPACK built-in, open-source Linux [[https://​github.com/​linux4wilc/​driver|driver]] ​                                             | 2019.1 ​  | +| Ethernet 1G                            | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
-| SFP+*                          | PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​ef-di-25gemac.html|10G/​25G Ethernet Subsystem]],​ license required ​       | 2019.1 ​  | +| USB 2.0/​3.0 ​                           | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
-| HDMI 2.0 Source/​Sink* ​         | PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​hdmi.html|HDMI Subsystem]],​ license required ​                            ​| 2019.1 ​  | +| PCIe Root/Mini PCIe                    | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
-| Video PHY Controller* ​         | PL soft-core, WebPACK built-in, requires protocol-implementation like the HDMI Subsystem above, supported by 5EV only                          | 2019.1 ​  |+| SATA/​mSATA ​                            | PS hard-core, WebPACK built-in ​                                                                                                                 ​| 2019.1 ​  | 
 +| On-board Wi-Fi/SPI controller ​         | PS hard-core, WebPACK built-in, open-source Linux [[https://​github.com/​linux4wilc/​driver|driver]] ​                                              ​| 2019.1 ​  | 
 +<wrap hi>SFP+*</​wrap> ​                 ​| PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​ef-di-25gemac.html|10G/​25G Ethernet Subsystem]],​ license required ​        ​| 2019.1 ​  | 
 +<wrap hi>HDMI 2.0 Source/​Sink*</​wrap>  ​| PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​hdmi.html|HDMI Subsystem]],​ license required ​                             | 2019.1 ​  | 
 +<wrap hi>Video PHY Controller*</​wrap>  ​| PL soft-core, WebPACK built-in, requires protocol-implementation like the HDMI Subsystem above, supported by 5EV only                           ​| 2019.1 ​  |
  
 The initial Vivado version supported by Digilent for Genesys ZU-related projects is 2019.1. Digilent currently does not provide hardware platforms or examples for Xilinx'​s Vitis Unified Software Platform, however Vitis support is planned for the near future. The initial Vivado version supported by Digilent for Genesys ZU-related projects is 2019.1. Digilent currently does not provide hardware platforms or examples for Xilinx'​s Vitis Unified Software Platform, however Vitis support is planned for the near future.
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 Sliding the SW5 switch to the OFF position disables the power supplies by pulling //​INPUT_PGD//​ to ground. The capacitor C405 connected to the //EN// terminal of the LM5060 monitoring IC delays the VCC12V0 turn off with approximately 200ms until all power supplies have been safely powered off.  Sliding the SW5 switch to the OFF position disables the power supplies by pulling //​INPUT_PGD//​ to ground. The capacitor C405 connected to the //EN// terminal of the LM5060 monitoring IC delays the VCC12V0 turn off with approximately 200ms until all power supplies have been safely powered off. 
  
 +----
 +=== 1.4. Earthing/​Grounding System ​ ===
 +
 +The bundled power supply has a 3-pin AC power cord and internally shorts the DC negative terminal to the earth/​ground circuit of the power socket. Therefore, the Genesys ZU's ground circuits are at earth potential. In lieu of a metallic case the Genesys ZU has an internal shield ring at the edge of the board encircling it. The metallic pads of screws, feet and stand-offs (except the top right corner and Zmod stand-offs),​ but also the shell of connectors are wired to the shield ring. The shield ring ultimately connects to the Genesys ZU's ground circuit through a 2 mOhm resistor. There are also several capacitor pads (not loaded) around the board between the shield ring and the ground circuit. The screws on the edge of the board (except the top-right corner) can be used to wire an additional earth/​ground connection to the Genesys ZU.
 ---- ----
 ==== 2. MPSoC Boot Process ==== ==== 2. MPSoC Boot Process ====
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   - DONE : it is asserted when the PL configuration is completed;   - DONE : it is asserted when the PL configuration is completed;
  
-For more details about configuration pins see "​Clock,​ Reset, and Configuration Pins" section in [[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug1085-zynq-ultrascale-trm.pdf|Zynq UltraScale+ Device Technical Reference Manual (UG1085)]]. 
 ==== 3. Main Memory ==== ==== 3. Main Memory ====
 Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the PS (Processing System) side using the hard-core memory controller. ​ Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the PS (Processing System) side using the hard-core memory controller. ​
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 The last sector, used to store the MAC addresses, is protected from write and The last sector, used to store the MAC addresses, is protected from write and
-erase. Any attempt to program or erase the last sector will fail.+erase. Any attempt to program or erase the last sector will fail. Consequently,​ blank check operations (like the one in Vivado Hardware Manager) are also expected to fail, even after a full device erase, if the last sector is not ignored.
  
 The ISSI flash features an Advanced Sector/​Block Protection mechanism. Every The ISSI flash features an Advanced Sector/​Block Protection mechanism. Every
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 ---- ----
 === 4.3. mSATA slot === === 4.3. mSATA slot ===
-The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile SSD storage. Both half and full-size modules are supported. Since PCIe and SATA share the same GTR lanes, one has to disable PCIe first to enable SATA.+The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile ​<​nowiki>​SSD</​nowiki> ​storage. Both half and full-size modules are supported. Since PCIe and SATA share the same GTR lanes, one has to disable PCIe first to enable SATA.
  
 ---- ----
-==== 5. Network Connectivity ==== +==== 5. Oscillators/​Clocks ==== 
-=== 5.1. Wi-Fi ===+ 
 +The PS on Genesys ZU has a clock source of 30MHz on pin R16 (PS_REF_CLK),​ coming from IC67 (5P49V6965A244NLGI). 
 + 
 +The PL on Genesys ZU has a clock source of (by default) 25MHz on pin E12 (SYSCLK), coming from the CLK_OUT pin of the Ethernet PHY IC36 (DP83867CRRGZR). This LVCMOS18 I/O standard clock can be used for any purpose in the PL, with certain restrictions:​ 
 +  * It enters the FPGA via HDGC (High-Density I/O Bank Global Clock) pins. These can only directly drive BUFGCE primitives, not MMCM/PLL primitives. See Global Clock Inputs in [[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug572-ultrascale-clocking.pdf|ug572]]. It can still drive MMCM/PLL indirectly, but this will need a CLOCK_DEDICATED_ROUTE FALSE constraint, otherwise Vivado DRC will fail. 
 +  * Is available whenever the PHY is out of reset and is not specifically configured through its registers to disable this clock. By default it is synchronous to the crystal input of the Ethernet PHY (25 MHz). 
 + 
 +<WRAP center round todo 60%> 
 +Add info on GTR and GTH reference clocks 
 +</​WRAP>​ 
 + 
 +---- 
 +==== 6. Reset Sources ==== 
 + 
 +The Genesys ZU provides several different methods of resetting the Zynq Ultrascale+ device, as described in the following sections. 
 + 
 +=== 6.1 Power-on Reset === 
 + 
 +The Zynq Ultrascale+ PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Genesys ZU drives this signal from the PG_ALL signal of the power supplies in order to hold the system in reset until all power supplies are valid. The Genesys ZU also has a red push button, labeled POR, which can toggle the power-on reset of the Zynq Ultrascale+. 
 + 
 +=== 6.2 Programmable Logic Reset === 
 + 
 +A red push button, labeled PROG, toggles the Zynq Ultrascale+'​s PS_PROG_B input. This resets the PL and causes DONE to be de-asserted. The PL will remain unconfigured until it is reprogrammed by the processor or via JTAG.  
 + 
 +=== 6.3 Processor Subsystem Reset === 
 + 
 +The external system reset button, labeled SRST, resets the Zynq Ultrascale+ device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing boot moode jumpers a power-on reset is needed to act on the new setting.  
 + 
 +For more details about configuration pins see "​Clock,​ Reset, and Configuration Pins" section in [[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug1085-zynq-ultrascale-trm.pdf|Zynq UltraScale+ Device Technical Reference Manual (UG1085)]]. 
 + 
 +---- 
 +==== 7. Network Connectivity ==== 
 +=== 7.1. Wi-Fi ===
 A Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the MPSoC on the PS-side over SPI, supporting a maximum theoretical data rate of 48Mbps. The ATWINC1500 can be used in bare-metal applications with the full IP stack included in the firmware loaded from flash. However, it is also supported in Linux in the ATWILC1000-compatible mode, where the firmware is loaded on-the-fly upon boot and the OS IP stack is used. A Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the MPSoC on the PS-side over SPI, supporting a maximum theoretical data rate of 48Mbps. The ATWINC1500 can be used in bare-metal applications with the full IP stack included in the firmware loaded from flash. However, it is also supported in Linux in the ATWILC1000-compatible mode, where the firmware is loaded on-the-fly upon boot and the OS IP stack is used.
  
 ---- ----
-=== 5.2. 1G Ethernet ===+=== 7.2. 1G Ethernet ===
 The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the MPSoC via RGMII for data and MDIO for management. The auxiliary interrupt (ETH_INTN_PWDNN) and reset (ETH_RSTN) signals also connect to MIO Bank 501. The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the MPSoC via RGMII for data and MDIO for management. The auxiliary interrupt (ETH_INTN_PWDNN) and reset (ETH_RSTN) signals also connect to MIO Bank 501.
  
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 ---- ----
-=== 5.3. 10G SFP+ ===+=== 7.3. 10G SFP+ ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 Todo for 5EV. Todo for 5EV.
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 ---- ----
-=== 5.4. WLAN, Bluetooth, WWAN ===+=== 7.4. WLAN, Bluetooth, WWAN ===
 The Mini PCIe socket allows you to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1 and USB 2.0 available in the socket, even dual Wi-Fi/​Bluetooth modules can be used. The primary use case is Linux OS, so modules with Linux drivers available in-kernel are recommended. For WWAN radio modules a SIM slot is present on the bottom side of the board. The Mini PCIe socket allows you to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1 and USB 2.0 available in the socket, even dual Wi-Fi/​Bluetooth modules can be used. The primary use case is Linux OS, so modules with Linux drivers available in-kernel are recommended. For WWAN radio modules a SIM slot is present on the bottom side of the board.
  
 ---- ----
-==== 6. Peripheral Connectivity ==== +==== 8. Peripheral Connectivity ==== 
-=== 6.1. USB Full-Featured Type-C ===+=== 8.1. USB Full-Featured Type-C ===
 USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle J6. The connector has a USB 2.0 pair for backward compatibility,​ one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is established during the configuration process over the CC1 and CC2 pins. Depending on the orientation,​ either pins with suffix 1 or pins with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer. USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle J6. The connector has a USB 2.0 pair for backward compatibility,​ one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is established during the configuration process over the CC1 and CC2 pins. Depending on the orientation,​ either pins with suffix 1 or pins with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer.
  
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 ---- ----
-=== 6.2. USB 2.0 Host ===+=== 8.2. USB 2.0 Host ===
 Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to the PS-side controller of MPSoC over ULPI. Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to the PS-side controller of MPSoC over ULPI.
 The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port. This allows interfacing with Bluetooth modules, for example. The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port. This allows interfacing with Bluetooth modules, for example.
  
 ---- ----
-=== 6.3. USB 2.0 - JTAG/Serial Bridge ===+=== 8.3. USB 2.0 - JTAG/Serial Bridge ===
 The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration,​ but the first one will always connect to the MPSoC and the second one to the Platform MCU. The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration,​ but the first one will always connect to the MPSoC and the second one to the Platform MCU.
 The MPSoC UART interface is wired to the PS-side MIO Bank 500: UART_TXD_IN to MIO18 and UART_RXD_OUT to MIO19. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC (e.g. UART_TXD_IN is the TXD signal of the DTE, meaning it is an output of the DTE and an input of the DCE). The MPSoC UART interface is wired to the PS-side MIO Bank 500: UART_TXD_IN to MIO18 and UART_RXD_OUT to MIO19. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC (e.g. UART_TXD_IN is the TXD signal of the DTE, meaning it is an output of the DTE and an input of the DCE).
Line 513: Line 552:
  
 ---- ----
-==== 7. Multimedia ==== +==== 9. Multimedia ==== 
-=== 7.1. DisplayPort Source ===+=== 9.1. DisplayPort Source ===
 The dual-lane mini DisplayPort connector J27 is wired to a PS-side DisplayPort Controller via two PS-GTR transceiver lanes. Resolutions up to [email protected] are supported at a maximum 5.4Gbps line rate.  The dual-lane mini DisplayPort connector J27 is wired to a PS-side DisplayPort Controller via two PS-GTR transceiver lanes. Resolutions up to [email protected] are supported at a maximum 5.4Gbps line rate. 
  
 ---- ----
-=== 7.2. HDMI Source ===+=== 9.2. HDMI Source ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 TODO for 5EV TODO for 5EV
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 ---- ----
-=== 7.3. HDMI Sink ===+=== 9.3. HDMI Sink ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 TODO for 5EV TODO for 5EV
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 ---- ----
-=== 7.4. Audio Codec ===+=== 9.4. Audio Codec ===
 The Genesys ZU board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC39) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J20-green),​ headphone-out (J19-black),​ line-in (J22-blue), and microphone-in (J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono. The Genesys ZU board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC39) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J20-green),​ headphone-out (J19-black),​ line-in (J22-blue), and microphone-in (J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono.
  
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 ---- ----
-=== 7.5. MIPI/Pcam Ports ===+=== 9.5. MIPI/Pcam Ports ===
 The two MIPI/Pcam ports included on the Genesys ZU are 15-pin, 1 mm pitch, zero insertion force (ZIF) connectors designed specifically for attaching camera sensor modules to host systems. It builds on the Pcam connector standard introduced on the Digilent Zybo Z7, but allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture. Therefore, it supports MIPI DSI applications too, while remaining backward compatible with MIPI CSI-2 Pcam modules, like the Digilent Pcam 5C. The two MIPI/Pcam ports included on the Genesys ZU are 15-pin, 1 mm pitch, zero insertion force (ZIF) connectors designed specifically for attaching camera sensor modules to host systems. It builds on the Pcam connector standard introduced on the Digilent Zybo Z7, but allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture. Therefore, it supports MIPI DSI applications too, while remaining backward compatible with MIPI CSI-2 Pcam modules, like the Digilent Pcam 5C.
  
-The Pcam connector pin-out is rigidly defined and includes a two lane MIPI CSI-2 bus for camera data, an I<​sup>​2</​sup>​C bus for camera configuration,​ two additional general purpose signals, and 3.3 V for powering the camera module, as depicted in Figure ​7.5.1 and Table 7.5.1. Digilent is developing a catalog of Pcam peripheral camera modules with various different types of sensors that all conform to this pin-out. The pin-out was also chosen so that many camera modules designed to work with the Raspberry Pi will also work when connected to the Pcam port. +The Pcam connector pin-out is rigidly defined and includes a two lane MIPI CSI-2 bus for camera data, an I<​sup>​2</​sup>​C bus for camera configuration,​ two additional general purpose signals, and 3.3 V for powering the camera module, as depicted in Figure ​9.5.1 and Table 9.5.1. Digilent is developing a catalog of Pcam peripheral camera modules with various different types of sensors that all conform to this pin-out. The pin-out was also chosen so that many camera modules designed to work with the Raspberry Pi will also work when connected to the Pcam port. 
  
-{{ :​reference:​programmable-logic:​zybo-z7:​zybo-z7-pcam-pins.png?​600 | Figure ​7.5.1. Pcam Pin-out}}+{{ :​reference:​programmable-logic:​zybo-z7:​zybo-z7-pcam-pins.png?​600 | Figure ​9.5.1. Pcam Pin-out}}
 <​html><​center></​html>​ <​html><​center></​html>​
-//​Figure ​7.5.1: Pcam Pin-out//+//​Figure ​9.5.1: Pcam Pin-out//
 <​html></​center></​html>​ <​html></​center></​html>​
  
-//​Table ​7.5.1: Pcam Pin-out//+//​Table ​9.5.1: Pcam Pin-out//
 ^ Pin Number ​ ^ Function ​              ^ Genesys ZU Implementation ​                                      ^ ^ Pin Number ​ ^ Function ​              ^ Genesys ZU Implementation ​                                      ^
 | 1           | GND                    | GND                                                              | | 1           | GND                    | GND                                                              |
Line 592: Line 631:
  
 ---- ----
-==== 8. Expansion Ports ==== +==== 10. Expansion Ports ==== 
-=== 8.1. Mini PCIe / mSATA === +=== 10.1. Mini PCIe / mSATA === 
-J13 socket implements a versatile expansion option for adding SSD, WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocatable stand-offs included with the board. Electrically,​ the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board USB hub and the MPSoC USB1 controller up the chain.+J13 socket implements a versatile expansion option for adding ​<​nowiki>​SSD</​nowiki>​, WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocatable stand-offs included with the board. Electrically,​ the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board USB hub and the MPSoC USB1 controller up the chain.
  
 ---- ----
-=== 8.2. Low-Pin Count FMC Connector ===+=== 10.2. Low-Pin Count FMC Connector ===
 The Genesys ZU includes an FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard. Genesys ZU-based designs can now be easily extended with custom or off-the-shelf high-performance modules. The Genesys ZU includes an FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard. Genesys ZU-based designs can now be easily extended with custom or off-the-shelf high-performance modules.
  
 The actual connector used is a 160-pin Samtec ASP-134603-01,​ the low-pin count, 10mm stacking height variant of the standard. All user defined signals are bonded to the PL-side of the MPSoC to HP banks 64 and 65. <wrap hi>On the 5EV variant the multi-gigabit transceiver lane is also wired to the PL-side GTH transceiver,​ sharing the lane with the SFP+ slot.*</​wrap> ​ The 34 differential pairs are powered by the Genesys ZU VADJ rail adjustable in the 1.2 V - 1.8 V range. The actual connector used is a 160-pin Samtec ASP-134603-01,​ the low-pin count, 10mm stacking height variant of the standard. All user defined signals are bonded to the PL-side of the MPSoC to HP banks 64 and 65. <wrap hi>On the 5EV variant the multi-gigabit transceiver lane is also wired to the PL-side GTH transceiver,​ sharing the lane with the SFP+ slot.*</​wrap> ​ The 34 differential pairs are powered by the Genesys ZU VADJ rail adjustable in the 1.2 V - 1.8 V range.
 +There is also a 12 V rail wired to the FMC connector, which can supply up to 1 A to the mezzanine card.
  
 <WRAP center round important 90%> <WRAP center round important 90%>
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 Each transceiver lane includes a receive pair and a transmit pair. Lane DP0 is wired through the mux to quad 224. The reference clock GBTCLK0 goes to a jitter filter and can be sent to MGTREFCLK0 pins of the same quad. Each transceiver lane includes a receive pair and a transmit pair. Lane DP0 is wired through the mux to quad 224. The reference clock GBTCLK0 goes to a jitter filter and can be sent to MGTREFCLK0 pins of the same quad.
    
-Table 8.2.1 shows how the FMC gigabit signals are mapped to pins and GTH primitives. Refer to the UltraScale Architecture GTH Transceivers User Guide ([[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug576-ultrascale-gth-transceivers.pdf|ug576]]) for more information.</​wrap>​+Table 10.2.1 shows how the FMC gigabit signals are mapped to pins and GTH primitives. Refer to the UltraScale Architecture GTH Transceivers User Guide ([[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug576-ultrascale-gth-transceivers.pdf|ug576]]) for more information.</​wrap>​
  
-//​Table ​8.2.1: FMC Gigabit Signals Mapping//+//​Table ​10.2.1: FMC Gigabit Signals Mapping//
 ^ Quad  ^ Primitive ​            |^ Pin type    ^ Pin    ^ FMC signal ​  ^ ^ Quad  ^ Primitive ​            |^ Pin type    ^ Pin    ^ FMC signal ​  ^
 | 224   | GTHE4_CHANNEL ​ | X0Y7  | MGTHTXP/​N3 ​ | N4/N3  | DP0_C2M_P/​N ​ | | 224   | GTHE4_CHANNEL ​ | X0Y7  | MGTHTXP/​N3 ​ | N4/N3  | DP0_C2M_P/​N ​ |
Line 623: Line 663:
 For FMC designs which use FMC_LA_07_P/​_N and/or FMC_LA15_P/​_N lines with an I/O standard which needs DCI, please make sure you add the DCIRESET primitive to the respective designs. Refer to the UltraScale Architecture SelectIO Resources User Guide ([[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug571-ultrascale-selectio.pdf|ug571]]) chapter "​Special DCI Requirements in Some Banks" for more information. For FMC designs which use FMC_LA_07_P/​_N and/or FMC_LA15_P/​_N lines with an I/O standard which needs DCI, please make sure you add the DCIRESET primitive to the respective designs. Refer to the UltraScale Architecture SelectIO Resources User Guide ([[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug571-ultrascale-selectio.pdf|ug571]]) chapter "​Special DCI Requirements in Some Banks" for more information.
  
-//​Table ​8.2.2: Maximum length mismatch including MPSoC package delay.//+//​Table ​10.2.2: Maximum length mismatch including MPSoC package delay.//
 ^ Signal Group                                    ^  Length matching ​              || ^ Signal Group                                    ^  Length matching ​              ||
 | :::                                             ^ Intra-pair ​       ^ Inter-pair ​ ^ | :::                                             ^ Intra-pair ​       ^ Inter-pair ​ ^
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 ---- ----
-=== 8.3. Zmod ===+=== 10.3. Zmod ===
 The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. The port is compatible with version 1.1 of the SYZYGY specification from Opal Kelly. The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. The port is compatible with version 1.1 of the SYZYGY specification from Opal Kelly.
  
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 The differential pairs were prioritized and wired to HP banks, allowing the maximum data rates supported by the SelectI/O architecture. However, the single-ended pins are wired to an HD bank, limiting the data rate to 250 Mb/s according to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [[https://​www.xilinx.com/​support/​documentation/​data_sheets/​ds925-zynq-ultrascale-plus.pdf|(ds925)]]. The differential pairs were prioritized and wired to HP banks, allowing the maximum data rates supported by the SelectI/O architecture. However, the single-ended pins are wired to an HD bank, limiting the data rate to 250 Mb/s according to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [[https://​www.xilinx.com/​support/​documentation/​data_sheets/​ds925-zynq-ultrascale-plus.pdf|(ds925)]].
 Template constraints for the Zmod port can be found in the Genesys ZU's Master XDC file, available through Digilent'​s [[https://​github.com/​Digilent/​digilent-xdc|digilent-xdc]] repository on Github. Template constraints for the Zmod port can be found in the Genesys ZU's Master XDC file, available through Digilent'​s [[https://​github.com/​Digilent/​digilent-xdc|digilent-xdc]] repository on Github.
 +
 +The two standoffs located on the sides of the Zmod port, on the top side of the Genesys ZU board, are hexagonal, 5 mm tall with M2.5 x 0.45 internal threaded holes. For mounting Zmods on Genesys ZU, two screws with M2.5 x 0.45 thread and 3mm thread length would be needed.
  
 For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]]. For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]].
  
 ---- ----
-== 8.3.1. SYZYGY Pod Compatibility ==+== 10.3.1. SYZYGY Pod Compatibility ==
  
-The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required to determine if the Genesys ZU is compatible with a certain pod is summarized in Table 8.3.1.1.+The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required to determine if the Genesys ZU is compatible with a certain pod is summarized in Table 10.3.1.1.
  
-//​Table ​8.3.1.1: SYZYGY Compatibility//​+//​Table ​10.3.1.1: SYZYGY Compatibility//​
 ^ Parameter ​                 ^ Port A (STD)             ^ ^ Parameter ​                 ^ Port A (STD)             ^
 ^ Port Type                  | Standard ​                | ^ Port Type                  | Standard ​                |
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 ---- ----
-== 8.3.2 ==+== 10.3.2 ==
  
 FIXME //Is there any information on this not encapsulated by the syzygy spec?// FIXME //Is there any information on this not encapsulated by the syzygy spec?//
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 ---- ----
-=== 8.4. Pmod ===+=== 10.4. Pmod ===
  
-Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure ​8.4.1 below. For more information regarding the power supply specifications of the Pmod ports, refer to the [[https://​www.digilentinc.com/​Pmods/​Digilent-Pmod_%20Interface_Specification.pdf|Digilent Pmod™ Interface Specification]],​ "Power Supply"​ section.+Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure ​10.4.1 below. For more information regarding the power supply specifications of the Pmod ports, refer to the [[https://​www.digilentinc.com/​Pmods/​Digilent-Pmod_%20Interface_Specification.pdf|Digilent Pmod™ Interface Specification]],​ "Power Supply"​ section.
  
-{{ :​basys3-pmod_connector.png?​350 | Figure ​8.4.1. Pmod port}}+{{ :​basys3-pmod_connector.png?​350 | Figure ​10.4.1. Pmod port}}
 <​html><​center></​html>​ <​html><​center></​html>​
-//​Figure ​8.4.1: Pmod port//+//​Figure ​10.4.1: Pmod port//
 <​html></​center></​html>​ <​html></​center></​html>​
  
-Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod ports to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information. The vivado-library ​and vivado-hierarchies repositories ​on the [[https://​github.com/​Digilent/​|Digilent Github]] contains pre-made IP cores for many of these Pmods that greatly reduce the work of integrating them into your project. See the Pmod-related tutorials on the Genesys ZU Resource Center for help using them.+Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod ports to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information. The vivado-library ​repository ​on the [[https://​github.com/​Digilent/​|Digilent Github]] contains pre-made IP cores for many of these Pmods that greatly reduce the work of integrating them into your project. This repository'​s ''​hierarchies''​ branch contains additional scripts and sources that can be used to speed up the process of integrating these cores. See the Pmod-related tutorials on the Genesys ZU Resource Center for help using them.
  
 --> PMODS JA, JB, JC, JD # --> PMODS JA, JB, JC, JD #
Line 703: Line 745:
  
 ---- ----
-=== 8.5. Dual Digital/​Analog Pmod ===+=== 10.5. Dual Digital/​Analog Pmod ===
 On the Genesys ZU, one of the Pmod connectors is not like the others. Designated by JA, the Pmod connector is wired to pins that can serve as auxiliary inputs to the system monitor ADC inside the MPSoC. These pins are in a VADJ-powered bank, so the VCC pins are not powered from the 3.3 V rail, like on regular Pmods, but from VADJ. VADJ on the Genesys ZU is in the 1.2 V - 1.8 V range. Pins 1-7, 2-8, 3-9, 4-10 are paired and routed differentially. On the Genesys ZU, one of the Pmod connectors is not like the others. Designated by JA, the Pmod connector is wired to pins that can serve as auxiliary inputs to the system monitor ADC inside the MPSoC. These pins are in a VADJ-powered bank, so the VCC pins are not powered from the 3.3 V rail, like on regular Pmods, but from VADJ. VADJ on the Genesys ZU is in the 1.2 V - 1.8 V range. Pins 1-7, 2-8, 3-9, 4-10 are paired and routed differentially.
 Although these pins can be used in digital mode, the particularities of this connector must be taken into account when connecting Pmod modules to it. Although these pins can be used in digital mode, the particularities of this connector must be taken into account when connecting Pmod modules to it.
  
 ---- ----
-==== 9. Basic I/O ==== +==== 11. Basic I/O ==== 
-The Genesys ZU includes five push-buttons,​ four slide switches, one tri-color LED and four green LEDs connected to the Zynq PL, as shown in Figure ​9.1 below. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output). The five push-buttons are arranged in a plus-sign configuration (center, left, right, up and down buttons, respectively).+The Genesys ZU includes five push-buttons,​ four slide switches, one tri-color LED and four green LEDs connected to the Zynq PL, as shown in Figure ​11.1 below. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output). The five push-buttons are arranged in a plus-sign configuration (center, left, right, up and down buttons, respectively).
  
  
-{{ :​reference:​programmable-logic:​genesys-zu:​genesys_zu_basic_ioi.png?nolink ​|}}+{{ :​reference:​programmable-logic:​genesys-zu:​basic_io_genesys_zu.png?600 |}}
 <​html><​center></​html>​ <​html><​center></​html>​
-//​Figure ​9.1: Genesys ZU PL Basic I/O//+//​Figure ​11.1: Genesys ZU PL Basic I/O//
 <​html></​center></​html>​ <​html></​center></​html>​
 <​html><​left></​html>​ <​html><​left></​html>​
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 ---- ----
-=== 9.1. Push-Buttons ===+=== 11.1. Push-Buttons ===
  
 The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed.
  
 ---- ----
-=== 9.2. Slide Switches ===+=== 11.2. Slide Switches ===
 The slide switches generate constant high or low inputs depending on their position: when the slide is in a low position (i.e. close to the lower board edge), the generated input is low; when the slide is in a high position (i.e. close to the center of the board), the generated input is high. The slide switches generate constant high or low inputs depending on their position: when the slide is in a low position (i.e. close to the lower board edge), the generated input is low; when the slide is in a high position (i.e. close to the center of the board), the generated input is high.
  
 ---- ----
-=== 9.3. Tri-Color LED ===+=== 11.3. Tri-Color LED ===
  
 The tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the input signal corresponding to one of these colors low will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding PL pins need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color. The tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the input signal corresponding to one of these colors low will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding PL pins need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color.
Line 737: Line 779:
  
 ---- ----
-=== 9.4. Green LEDs ===+=== 11.4. Green LEDs ===
 The individual high-efficiency LEDs are anode-connected to the Zynq Ultrascale+ via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their corresponding I/O pin. The individual high-efficiency LEDs are anode-connected to the Zynq Ultrascale+ via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their corresponding I/O pin.
 ---- ----
-==== 10. Platform Management ====+==== 12. Platform Management ====
 Tying all the features of the Genesys ZU together into a computing platform requires an embedded controller independent of the MPSoC. We call it Platform MCU. Part of the platform is the coin battery, the fan, a temperature sensor inside the MPSoC and Power Management Units (PMU). Management is done through dedicated signals or over the main I<​sup>​2</​sup>​C bus. Tying all the features of the Genesys ZU together into a computing platform requires an embedded controller independent of the MPSoC. We call it Platform MCU. Part of the platform is the coin battery, the fan, a temperature sensor inside the MPSoC and Power Management Units (PMU). Management is done through dedicated signals or over the main I<​sup>​2</​sup>​C bus.
-=== 10.1. Main I2C bus ===+=== 12.1. Main I2C bus ===
 Almost all I<​sup>​2</​sup>​C-capable peripherals are accessible through the main I<​sup>​2</​sup>​C bus. Multiple masters have access: Almost all I<​sup>​2</​sup>​C-capable peripherals are accessible through the main I<​sup>​2</​sup>​C bus. Multiple masters have access:
   * Platform MCU in the Auxiliary 3.3 V domain through MUX_SCL and MUX_SDA,   * Platform MCU in the Auxiliary 3.3 V domain through MUX_SCL and MUX_SDA,
Line 754: Line 796:
 {{ :​reference:​programmable-logic:​genesys-zu:​gzu_i2c_diagram.png?​nolink |}} {{ :​reference:​programmable-logic:​genesys-zu:​gzu_i2c_diagram.png?​nolink |}}
 <​html><​center></​html>​ <​html><​center></​html>​
-//​Figure ​10.1.1: Genesys ZU I<​sup>​2</​sup>​C topology//+//​Figure ​12.1.1: Genesys ZU I<​sup>​2</​sup>​C topology//
 <​html></​center></​html>​ <​html></​center></​html>​
  
 ---- ----
-=== 10.2. Platform MCU ===+=== 12.2. Platform MCU ===
 The Platform MCU is implemented by a Microchip ATmega328PB. It is on the auxiliary 3.3V power domain, immediately available after power-up. This power domain is independent of the PMUs which provide main power, giving the Platform MCU control over main power. It also shares the main I<​sup>​2</​sup>​C bus with the MPSoC, giving it access to all the critical peripherals. Other features include MPSoC temperature sensing, fan speed control, and VADJ voltage setting. The Platform MCU is implemented by a Microchip ATmega328PB. It is on the auxiliary 3.3V power domain, immediately available after power-up. This power domain is independent of the PMUs which provide main power, giving the Platform MCU control over main power. It also shares the main I<​sup>​2</​sup>​C bus with the MPSoC, giving it access to all the critical peripherals. Other features include MPSoC temperature sensing, fan speed control, and VADJ voltage setting.
  
Line 765: Line 807:
   * Bootloader where the bootloader resides.   * Bootloader where the bootloader resides.
  
-== 10.2.1. Application Section ==+== 12.2.1. Application Section ==
  
 The Platform MCU has the following interfaces on Genesys ZU: The Platform MCU has the following interfaces on Genesys ZU:
Line 786: Line 828:
 VADJ voltage value based on VADJ_LEVEL1 (AC13) and VADJ_LEVEL0 (AC14) input pins, VADJ voltage value based on VADJ_LEVEL1 (AC13) and VADJ_LEVEL0 (AC14) input pins,
 regardless of whether a syzygy pod and/or FMC mezzanine module is connected. regardless of whether a syzygy pod and/or FMC mezzanine module is connected.
-Table 10.2.1.1 presents the VADJ level encoding.+Table 12.2.1.1 presents the VADJ level encoding.
  
-//​Table ​10.2.1.1: VADJ levels encoding//+//​Table ​12.2.1.1: VADJ levels encoding//
 ^ VADJ_LEVEL1 ​ ^ VADJ_LEVEL0 ​ ^ VADJ level      ^ ^ VADJ_LEVEL1 ​ ^ VADJ_LEVEL0 ​ ^ VADJ level      ^
 |  0           ​| ​ 0           ​| ​ VADJ disabled ​ | |  0           ​| ​ 0           ​| ​ VADJ disabled ​ |
Line 800: Line 842:
 VADJ_AUTO signal value can change during board operation. The Platform MCU will VADJ_AUTO signal value can change during board operation. The Platform MCU will
 detect the pin change and will adjust the VADJ voltage level according to the detect the pin change and will adjust the VADJ voltage level according to the
-actual VADJ_LEVEL1 and VADJ_LEVEL0 pins state.+actual VADJ_LEVEL1 and VADJ_LEVEL0 pins state. The voltage rail will reach its power good threshold in maximum 60 ms after the falling edge of VADJ_AUTO. The power good threshold is set to 100 mV less than the nominal voltage.
  
 To set the desired VADJ level you have to: To set the desired VADJ level you have to:
Line 816: Line 858:
 On Genesys ZU there is a LED labeled with PMCU. This is the status led that is On Genesys ZU there is a LED labeled with PMCU. This is the status led that is
 used by the Platform MCU to display the system fault that has the highest priority. used by the Platform MCU to display the system fault that has the highest priority.
-The blinking pattern for each fault is presented in Table 10.2.1.2.+The blinking pattern for each fault is presented in Table 12.2.1.2.
  
 After Platform MCU startup, if no issues were encountered,​ this LED should blink After Platform MCU startup, if no issues were encountered,​ this LED should blink
Line 823: Line 865:
   * A “short blink” and a “short pause” last for about 200ms each;   * A “short blink” and a “short pause” last for about 200ms each;
  
-//​Table ​10.2.1.2: Fault blink patterns//+//​Table ​12.2.1.2: Fault blink patterns//
 ^  Blink Pattern (Repeated) ​ ^  Issue            ^  Priority ​ ^  Comments ​            ^ ^  Blink Pattern (Repeated) ​ ^  Issue            ^  Priority ​ ^  Comments ​            ^
 |  Long Blink – Long Pause   ​| ​ Fan Speed Fault  |  0         ​| ​ Register 0x04 Bit 0  | |  Long Blink – Long Pause   ​| ​ Fan Speed Fault  |  0         ​| ​ Register 0x04 Bit 0  |
  
 The Platform MCU exposes to the PC a register interface, accessible via UART. The Platform MCU exposes to the PC a register interface, accessible via UART.
-The full register map is shown in Table 10.2.1.3.+The full register map is shown in Table 12.2.1.3.
  
-//​Table ​10.2.1.3: Register map// +//​Table ​12.2.1.3: Register map// 
-^  Offset ​    ​^ ​ Register Name                      ^  Size [bits] ​ ^  R/W  ^  Description ​                                                                                                                                                                                                                                                                                                                                                              ​+^  Offset ​    ​^ ​ Register Name                      ^  Size [bits] ​ ^  R/W  ^  Description ​                                                                                                                                                                                                                                                                                                                                                                ​
-|  0x00       ​| ​ ID Register ​                       |  8            |  R    | It contains a fixed value, used for determining if the Platform MCU is alive and responding over UART (0x00). ​                                                                                                                                                                                                                                                             +|  0x00       ​| ​ ID Register ​                       |  8            |  R    | It contains a fixed value, used for determining if the Platform MCU is alive and responding over UART (0x00). ​                                                                                                                                                                                                                                                               
-|  0x01       ​| ​ Firmware Version ​                  ​| ​ 8            |  R    | It contains the firmware major version on bits 7-4 and the minor version on bits 3-0                                                                                                                                                                                                                                                                                       ​+|  0x01       ​| ​ Firmware Version ​                  ​| ​ 8            |  R    | It contains the firmware major version on bits 7-4 and the minor version on bits 3-0                                                                                                                                                                                                                                                                                         ​
-|  0x02       ​| ​ Scratch Register ​                  ​| ​ 8            |  R/W  | Read/write register used to test both the write and the read register interfaces. ​                                                                                                                                                                                                                                                                                         +|  0x02       ​| ​ Scratch Register ​                  ​| ​ 8            |  R/W  | Read/write register used to test both the write and the read register interfaces. ​                                                                                                                                                                                                                                                                                           
-|  0x03       ​| ​ Measured FPGA Core Temperature ​    ​| ​ 8            |  R    | FPGA Temperature value, as computed by the Platform MCU based on the thermal diode measurement. ​                                                                                                                                                                                                                                                                           +|  0x03       ​| ​ Measured FPGA Core Temperature ​    ​| ​ 8            |  R    | FPGA Temperature value, as computed by the Platform MCU based on the thermal diode measurement. ​                                                                                                                                                                                                                                                                             
-|  0x04       ​| ​ Measured Fan Speed                 ​| ​ 16           ​| ​ R    | FPGA Fan Speed value in rpm, as computed based on the fan feedback pin. Upon read, the low byte is received first. ​                                                                                                                                                                                                                                                        ​+|  0x04       ​| ​ Measured Fan Speed                 ​| ​ 16           ​| ​ R    | FPGA Fan Speed value in rpm, as computed based on the fan feedback pin. Upon read, the low byte is received first. ​                                                                                                                                                                                                                                                          ​
-|  0x06       ​| ​ Fan Speed Fault                    |  8            |  8    | Bits 7-1: Unused \\ Bit 0: ‘1’ if fan speed is outside the expected range; ‘0’ otherwise ​                                                                                                                                                                                                                                                                                  ​+|  0x06       ​| ​ Fan Speed Fault                    |  8            |  8    | Bits 7-1: Unused \\ Bit 0: ‘1’ if fan speed is outside the expected range; ‘0’ otherwise ​                                                                                                                                                                                                                                                                                    ​
-^  0x07-0x0E ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                                                                                                                           +^  0x07-0x0E ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                                                                                                                             
-|  0x0F       ​| ​ Platform MCU Control ​              ​| ​ 8            |  R/W  | Bits 7-2: Unused \\ Bit 1: Fault Status: \\    -  ‘1’ = Clear all faults \\    -  [Default] ‘0’ = Do nothing \\ Once written with ‘1’, this bit returns by itself to ‘0’ after all the faults have been cleared.\\ Bit 0: I2C Communication to PMUs Control: \\     - ‘1’ = I2C Communication to PMUs Disabled \\     - [Default] ‘0’ = I2C Communication to PMUs Enabled ​ | +|  0x0F       ​| ​ Platform MCU Control ​              ​| ​ 8            |  R/W  | Bits 7-2: Unused \\ Bit 1: Fault Status: \\     ​-  ‘1’ = Clear all faults \\     ​-  [Default] ‘0’ = Do nothing \\ Once written with ‘1’, this bit returns by itself to ‘0’ after all the faults have been cleared.\\ Bit 0: I2C Communication to PMUs Control: \\     - ‘1’ = I2C Communication to PMUs Disabled \\     - [Default] ‘0’ = I2C Communication to PMUs Enabled ​ | 
-^  0x10-0x70 ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                                                                                                                           ^+^  0x10-0x70 ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                                                                                                                             ^
  
 When the PC wants to access a Platform MCU register, it needs to respect the following protocol: When the PC wants to access a Platform MCU register, it needs to respect the following protocol:
-  * It needs to send at first the address byte. Bits 7 to 1 of this byte contain the register start address (found in the first column from Table 10.2.1.3). Bit 0 of this byte is logic ‘1’ for read transactions,​ and logic ‘0’ for write transactions.+  * It needs to send at first the address byte. Bits 7 to 1 of this byte contain the register start address (found in the first column from Table 12.2.1.3). Bit 0 of this byte is logic ‘1’ for read transactions,​ and logic ‘0’ for write transactions.
   * It then needs to send a second byte, containing the number of bytes to read/write.   * It then needs to send a second byte, containing the number of bytes to read/write.
   * For write transactions,​ it then needs to send the actual values to be written in the Platform MCU registers. The number of bytes sent in this phase needs to match the value from the previous byte (“the number of bytes to read/​write”),​ otherwise communication with the Platform MCU will hang.   * For write transactions,​ it then needs to send the actual values to be written in the Platform MCU registers. The number of bytes sent in this phase needs to match the value from the previous byte (“the number of bytes to read/​write”),​ otherwise communication with the Platform MCU will hang.
Line 872: Line 914:
  
 ---- ----
-== 10.2.2. Bootloader Section ==+== 12.2.2. Bootloader Section ==
 In the program memory, along with the Firmware Application,​ there is a bootloader that launches the Application at power-up. In the program memory, along with the Firmware Application,​ there is a bootloader that launches the Application at power-up.
  
 ---- ----
-=== 10.3. Fan ===+=== 12.3. Fan ===
 Mounted on the MPSoC heatsink, there is a 12 V fan with a 4-pin header. It can automatically be controlled by the Platform MCU based on the MPSoC temperature or set to the fixed full speed. This option is controlled by JP2 and is user-selectable. Mounted on the MPSoC heatsink, there is a 12 V fan with a 4-pin header. It can automatically be controlled by the Platform MCU based on the MPSoC temperature or set to the fixed full speed. This option is controlled by JP2 and is user-selectable.
  
-//​Table ​10.3.1: Fan jumper positions//+//​Table ​12.3.1: Fan jumper positions//
 ^ Jumper JP2 "AUTO FAN" ​ ^ Fan Speed  ^ ^ Jumper JP2 "AUTO FAN" ​ ^ Fan Speed  ^
 | Set                    | Automatic ​ | | Set                    | Automatic ​ |
Line 885: Line 927:
  
 ---- ----
-=== 10.4. Coin battery ===+=== 12.4. Coin battery ===
 A Seiko TS621E lithium rechargeable battery provides power to the MPSoC Battery Power Domain (BPD) through the VCC_PSBATT pin. It is connected in parallel with a 100 uF capacitor. The BPD includes the real-time clock with a dedicated crystal oscillator and a RAM available for storing a secure configuration key. The capacitor alone can provide power for approx. 15 minutes after main power is turned off. The battery will provide power after that. A Seiko TS621E lithium rechargeable battery provides power to the MPSoC Battery Power Domain (BPD) through the VCC_PSBATT pin. It is connected in parallel with a 100 uF capacitor. The BPD includes the real-time clock with a dedicated crystal oscillator and a RAM available for storing a secure configuration key. The capacitor alone can provide power for approx. 15 minutes after main power is turned off. The battery will provide power after that.
  
Line 897: Line 939:
  
 ---- ----
 +===== Hardware Errata =====
 +Although we strive to provide perfect products, we are not infallible. The Genesys ZU is subject to the limitations below.
 +^ Product Name  ^ Variant ​ ^ Revision ​ ^ S/N                                ^ Problem ​                                                                                                                                      ^ Status ​          ^
 +| Genesys ZU    | -3EG     | B         | DAD9C39-DAD9D32,​ DADA13A, DADA13B ​ | [[reference:​programmable-logic:​genesys-zu:​reference-manual#​fan_assembly_error|Fan assembly error resulting in sub-optimal mechanical hold.]] ​ | Fixed in rev C.  |
 +
 +=== 1. Fan Assembly Error ===
 +Due to an assembly error the heatsink clip of the MPSoC cooling fan has been mounted incorrectly,​ resulting in sub-optimal mechanical hold between the heatsink and the MPSoC package. On the affected production build the two slots on the yellow clip are facing right, where tall components prevent seating the clip.
 +
 +{{ :​reference:​programmable-logic:​genesys-zu:​5759d48d-d837-4f1b-97f1-89fd1533973f.jpg?​600 | Figure 1. Incorrect clip orientation prevents proper seating of the clip}}
 +<​html><​center></​html>​
 +//Figure 1. Incorrect clip orientation prevents proper seating of the clip//
 +<​html></​center></​html>​
 +
 +For optimal mechanical hold the clip’s lip should reach underneath the MPSoC package substrate on both the left and right sides. Since the heatsink is secured by double-sided tape too, the sub-optimal mechanical hold of the clip is expected to cause issues only in time with excessive material aging of the tape under high temperature swings and/or mechanical vibration.
 +The correct orientation of the yellow heatsink clip is with the two slots facing left.
 +
 +== Workaround ==
 +The fan and the yellow clip are user-removable. Disconnect all cables from the Genesys ZU before starting the operation. To remove the fan use a suitable Philips screwdriver to loosen the two screws fixing the fan to the heatsink. Put the fan aside for a moment. Use a narrow flathead screwdriver in one of the clip slots to carefully disengage the lips of the clip from underneath the MPSoC package. The lips are fragile and without due care they can break off easily. Once the lip on both sides of the clip is above the MPSoC package, the clip can be removed. Rotate the clip 180 degrees so that the slots are on the left and re-install it on the MPSoC package. Hook the lip of the clip under the MPSoC package on one side first and press down the other side to fasten the clip.
 +A step-by-step description of the clip (dis)assembly is described here: http://​www.malico.com.tw/​index.php?​option=com_content&​view=article&​id=451&​Itemid=406&​lang=en. After the yellow clip is in place, the fan can be screwed back in the same place as before.
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