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reference:programmable-logic:genesys-zu:reference-manual [2019/12/04 15:17]
Bogdan [10.2 Platform MCU]
reference:programmable-logic:genesys-zu:reference-manual [2020/07/30 13:29] (current)
Elod Gyorgy [4. Storage] Mentioned blank check expected to fail.
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 The black matte board you are holding in your hand is a prototyping and evaluation board proudly designed by Digilent. At its heart is a Xilinx Zynq UltraScale+ MPSoC ARM-FPGA hybrid, coupled with upgradeable memory, network and multimedia interfaces, and a wide variety of expansion connectors making it a versatile computing platform. The black matte board you are holding in your hand is a prototyping and evaluation board proudly designed by Digilent. At its heart is a Xilinx Zynq UltraScale+ MPSoC ARM-FPGA hybrid, coupled with upgradeable memory, network and multimedia interfaces, and a wide variety of expansion connectors making it a versatile computing platform.
  
-Available in two variants3EG and 5EVdifferentiated by the MPSoC model and some peripherals. ​If the fan sticker says 5EV, on top of 3EG you get slightly faster DDR4, more FPGA, video codec and GTH transcievers ​allowing HDMI Source, Sink and SFP+ 10G.+There are two variants ​of the Genesys ZU mentioned in this Reference Manual: ​3EG and 5EV. (**The 5EV is not yet released.)** These two variants are differentiated by the MPSoC model and some peripherals. ​As compared to the 3EG, with the 5EV you get slightly faster DDR4, more FPGA, video codecand GTH transceivers ​allowing HDMI Source, Sink and SFP+ 10G.
  
-Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it straight up boots Linux from the microSD card. Connect the USB micro B cable to a PC and open a terminal (115200-8-N-1) to the first COM port out of the two that appear. Login and password both "​root"​. The red button labeled "​POR"​ always resets the MPSoC and starts the boot process again.+Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it straight up boots Linux from the microSD card. Connect the USB micro B cable to a PC and open a terminal (115200-8-N-1) to the first COM port out of the two that appear. Login and password ​are both "​root"​. The red button labeled "​POR"​ always resets the MPSoC and starts the boot process again. ​
  
-Want to dive deep into development?​ Connecting the JTAG-HS1/​HS2 cable to header J28 will allow for on-the-fly programming and debug.+Want to dive deep into development? Head over to our [[https://​github.com/​Digilent|GitHub page]] and use the repos there as a starting point. Check out our [[reference:​programmable-logic:​genesys-zu:​getting-started|Getting Started Guide]] for a step-by-step. Build your own boot image on the SD card and boot it like the OOB demo. Not enough? Connecting the JTAG-HS1/​HS2 cable to header J28 will allow for on-the-fly programming and debug using Xilinx Vivado and SDK.
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 The Digilent Genesys ZU is a stand-alone Zynq UltraScale+ MPSoC prototyping and development board. It is an advanced computing platform with powerful multimedia and network connectivity interfaces. The excellent mix of on-board peripherals,​ upgrade-friendly DDR4, Mini PCIe and microSD slots, multi-camera and high-speed expansion connectors are bound to support a wide number of use-cases. Furthermore,​ the Genesys ZU is available in two variants with different MPSoC options and additional features for even more flexibility. Differences are <wrap hi>​highlighted*</​wrap>​ throughout this document. The Digilent Genesys ZU is a stand-alone Zynq UltraScale+ MPSoC prototyping and development board. It is an advanced computing platform with powerful multimedia and network connectivity interfaces. The excellent mix of on-board peripherals,​ upgrade-friendly DDR4, Mini PCIe and microSD slots, multi-camera and high-speed expansion connectors are bound to support a wide number of use-cases. Furthermore,​ the Genesys ZU is available in two variants with different MPSoC options and additional features for even more flexibility. Differences are <wrap hi>​highlighted*</​wrap>​ throughout this document.
  
-The Xilinx Zynq UltraScale+ MPSoC at the heart of the Genesys ZU is a big leap from the Zynq-7000 series. Faster and more processor cores, upgraded memory interface, integrated gigabit transceivers bring support for DDR4, USB Type-C 3.1, PCIe, SATA, DisplayPort,​ <wrap hi>​SFP+*</​wrap>​ and <wrap hi>​HDMI*</​wrap>​. The Genesys ZU is primarily targeted towards Linux-based applications that allows easy access to Wi-Fi, cellular radio (WWAN), SSD, USB SuperSpeedand 4K video. The bundled microSD card includes an out-of-box demo that boots a Linux image built in Petalinux and includes some test scripts for some of the peripherals.+The Xilinx Zynq UltraScale+ MPSoC at the heart of the Genesys ZU is a big leap from the Zynq-7000 series. Faster and more processor cores, upgraded memory interface, integrated gigabit transceivers bring support for DDR4, USB Type-C 3.1, PCIe, SATA, DisplayPort,​ <wrap hi>​SFP+*</​wrap>​ and <wrap hi>​HDMI*</​wrap>​. The Genesys ZU is primarily targeted towards Linux-based applications that allows easy access to Wi-Fi, cellular radio (WWAN), ​<​nowiki>​SSD</​nowiki>​, USB SuperSpeed and 4K video. The bundled microSD card includes an out-of-box demo that boots a Linux image built in Petalinux and includes some test scripts for some of the peripherals.
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 }} }}
  
-====== Features ​======+---- 
 +===== Features =====
 ^ Feature group            ^ Sub-feature ​                          ^ <color #​ed1c24>​Genesys ZU -3EG</​color> ​ ^ <color #​ed1c24>​Genesys ZU -5EV</​color> ​ ^ Zedboard ​                          ^ ^ Feature group            ^ Sub-feature ​                          ^ <color #​ed1c24>​Genesys ZU -3EG</​color> ​ ^ <color #​ed1c24>​Genesys ZU -5EV</​color> ​ ^ Zedboard ​                          ^
 | Processor ​               | APU                                   ​| ​ Quad A53                                                                        ||  Dual A9                           | | Processor ​               | APU                                   ​| ​ Quad A53                                                                        ||  Dual A9                           |
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 | :::                      | SFP+ 10G Ethernet ​                    ​| ​ ✘                                      |  ✔                                      |  ✘                                 | | :::                      | SFP+ 10G Ethernet ​                    ​| ​ ✘                                      |  ✔                                      |  ✘                                 |
 | Storage ​                 | SD                                    |  104 MB/s                                                                        ||  25 MB/s                           | | Storage ​                 | SD                                    |  104 MB/s                                                                        ||  25 MB/s                           |
-| :::                      | SSD                                   ​|  option - mSATA                                                                  ||  ✘                                 |+| :::                      | <​nowiki>​SSD</​nowiki> ​                 ​|  option - mSATA                                                                  ||  ✘                                 |
 | :::                      | Flash                                 ​| ​ ISSI 256 Mib SNOR                                                               ​|| ​ 128 Mib                           | | :::                      | Flash                                 ​| ​ ISSI 256 Mib SNOR                                                               ​|| ​ 128 Mib                           |
 | Multimedia ​              | DisplayPort ​                          ​| ​ 1.2a Dual-Lane ​                                                                 ||  ✘                                 | | Multimedia ​              | DisplayPort ​                          ​| ​ 1.2a Dual-Lane ​                                                                 ||  ✘                                 |
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 {{ :​reference:​programmable-logic:​genesys-zu:​genesys-zu-3eg-callout.png?​nolink |}} {{ :​reference:​programmable-logic:​genesys-zu:​genesys-zu-3eg-callout.png?​nolink |}}
-Figure Genesys ZU-3EG callout diagram.+<​html><​center></​html>​ 
 +//Figure ​I: Genesys ZU-3EG callout diagram// 
 +<​html></​center></​html>​ 
 +--> Callout with Description ​ # 
 +^ Callout #  ^ Description ​                  ^ Callout #  ^ Description ​                    ^ Callout #  ^ Description ​                          ^ 
 +| 1          | 6-pin PCIe power connector ​   | 13         | Coin battery retainer ​          | 25         | Type-C USB 3.1                        | 
 +| 2          | External JTAG port            | 14         | Pmod headers ​                   | 26         | Power switch ​                         | 
 +| 3          | USB JTAG/UART port            | 15         | Dual digital/​analog Pmod        | 27         | Zynq Ultrascale+,​ heat sink and fan  | 
 +| 4          | USB 2.0 host connectors ​      | 16         | User buttons ​                   | 28         | System Monitor header ​                | 
 +| 5          | Wi-Fi chip                    | 17         | User switches ​                  | 29         | SIM card slot (on the bottom side)    | 
 +| 6          | 4 GiB DDR4 SODIMM module ​     | 18         | Mini PCIe/mSATA slot            |            |                                       | 
 +| 7          | Audio jacks                   | 19         | User buttons ​                   |            |                                       | 
 +| 8          | Boot mode select jumper ​      | 20         | MIPI (Pcam) connectors ​         |            |                                       | 
 +| 9          | Reset buttons ​                | 21         | Wireless and <​nowiki>​SSD</​nowiki>​ activity LEDs  |            |                                       | 
 +| 10         | INIT, DONE, ERR and STS Leds  | 22         | MicroSD Card Slot               ​| ​           |                                       | 
 +| 11         | Zmod (SYZYGY) connector ​      | 23         | Mini DisplayPort ​               |            |                                       | 
 +| 12         | FMC LPC connector ​            | 24         | 1G Ethernet port                |            |                                       |
  
-^ Callout #  ^ Description ​ ^ Callout #  ^ Description ​ ^ Callout #  ^ Description ​ ^ +<-- 
-| 1          | FIXME        | 7          |              | 13         ​| ​             | +---- 
-| 2          |              | 8          |              | 14         ​| ​             | +===== Software Support ​=====
-| 3          |              | 9          |              | 15         ​| ​             | +
-| 4          |              | 10         ​| ​             | 16         ​| ​             | +
-| 5          |              | 11         ​| ​             | 17         ​| ​             | +
-| 6          |              | 12         ​| ​             | 18         ​| ​             | +
-====== ​Zynq UltraScale+ MPSoC Architecture ​====== +
-<WRAP center round todo 60%> +
-Description from Xilinx +
-</​WRAP>​+
  
-====== Functional Description ======+Zynq UltraScale+ MPSoC platforms are well-suited to be embedded Linux targets, and the Genesys ZU is no exception. Digilent provides a Petalinux project that was used to build the out-of-box image.
  
-===== 1 Power Supplies =====+The Genesys ZU is fully compatible with Xilinx’s high-performance Vivado® Design Suite HL WebPACK™ Edition. This tool set melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications,​ down to a simple bare-metal program that controls some LEDs. It is also possible to treat the MPSoC as a standalone FPGA for those not interested in using the processor in their design. The two MPSoC parts the Genesys ZU is available with, XCZU3EG and XCZU5EV, are [[https://​www.xilinx.com/​products/​design-tools/​vivado/​vivado-webpack.html#​architecture|supported]] under Vivado'​s free WebPACK™ license, which means the software is completely free to use, including the Logic Analyzer and High-level Synthesis (HLS) features. The Logic Analyzer assists with debugging logic that is running in hardware, and the HLS tool allows C code to be directly compiled into HDL.
  
-==== 1.1 Power Input ====+In the kit you will also find a free voucher for the Xilinx MIPI CSI-2 IP cores. Follow the instructions on the voucher slip to activate the license. This is a temporary measure until Vivado 2020.1 hits, which should include a license for these IPs free of charge. See the next table for IP-support status for other peripherals. 
 + 
 +//Table I: IP support status// 
 +^ Feature/​Peripheral ​                    ^ IP support ​                                                                                                                                     ^ Version ​ ^ 
 +| DDR4 memory controller ​                | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
 +| MIPI CSI-2/​Pcam ​                       | PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​ef-di-mipi-csi-rx.html|MIPI CSI Controller Subsystems]],​ bundled voucher ​ | 2019.1 ​  | 
 +| DisplayPort controller ​                | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
 +| Ethernet 1G                            | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
 +| USB 2.0/​3.0 ​                           | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
 +| PCIe Root/Mini PCIe                    | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
 +| SATA/​mSATA ​                            | PS hard-core, WebPACK built-in ​                                                                                                                 | 2019.1 ​  | 
 +| On-board Wi-Fi/SPI controller ​         | PS hard-core, WebPACK built-in, open-source Linux [[https://​github.com/​linux4wilc/​driver|driver]] ​                                              | 2019.1 ​  | 
 +| <wrap hi>​SFP+*</​wrap> ​                 | PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​ef-di-25gemac.html|10G/​25G Ethernet Subsystem]],​ license required ​        | 2019.1 ​  | 
 +| <wrap hi>HDMI 2.0 Source/​Sink*</​wrap> ​ | PL soft-core, [[https://​www.xilinx.com/​products/​intellectual-property/​hdmi.html|HDMI Subsystem]],​ license required ​                             | 2019.1 ​  | 
 +| <wrap hi>Video PHY Controller*</​wrap> ​ | PL soft-core, WebPACK built-in, requires protocol-implementation like the HDMI Subsystem above, supported by 5EV only                           | 2019.1 ​  | 
 + 
 +The initial Vivado version supported by Digilent for Genesys ZU-related projects is 2019.1. Digilent currently does not provide hardware platforms or examples for Xilinx'​s Vitis Unified Software Platform, however Vitis support is planned for the near future. 
 + 
 +Design resources, example projects, and tutorials are available for download at the [[start|Genesys ZU Resource Center]]. 
 + 
 +---- 
 +===== Zynq UltraScale+ MPSoC Architecture ===== 
 +Zynq UltraScale+ MPSoC is the Xilinx second-generation Zynq platform, combining a powerful processing system (PS) and user-programmable logic (PL) into the same device. The Zynq UltraScale+ Processing System core acts as a logic connection between the PS and the Programmable Logic (PL) while assisting you to integrate customized and integrated IP cores with the processing system using the Vivado IP integrator. As you may see in the picture below, the processing system features the Arm flagship Cortex -A53 64-bit quad-core running up to 1.5GHz and Cortex-R5 dual-core real-time processor along with other interfaces such as: DDR Memory Controller, High-Connectivity,​ General Connectivity,​ System Functions etc.  
 +The Zynq UltraScale+ MPSoC Processing System wrapper instantiates the processing system section of the Zynq UltraScale+ MPSoC for the programmable logic and external board logic. The wrapper includes unaltered connectivity with the ones presented above. ​  
 + 
 +{{ :​reference:​programmable-logic:​genesys-zu:​3eg_ps_pl.png?​600 |}} 
 +<​html><​center></​html>​ 
 +//Figure II: Zynq UltraScale+ EG// 
 +<​html></​center></​html>​ 
 + 
 +The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors. The interfaces between the processing system and programmable 
 +logic mainly consist of three main groups: the extended multiplexed I/O (EMIO), programmable logic I/O, and the AXI I/O groups. Besides those, there are up to 78 Multiplexed I/O (MIO) ports available from the processing system. The 78 MIO signals are divided into three banks, and each bank includes 26 device pins. Each bank (500, 501, and 502) has its own power pins for the hardware interface. 
 + 
 + 
 +--> MIO 0-25 : Bank 500 # 
 + 
 +| **MIO 500 3.3 V** |  **Peripherals** ​ |||||||||| 
 +| Pin           | QSPI | Mini PCIe / SATA | DDR4 SODIMM | MIO Buttons ​ | WI-FI | UART     | MIO LED | I2C MUX | USB 3.0 | 8-bit I/O Expander | 
 +| 0             | QSPI_SCLK0OUT |                  |             ​| ​             |                  |          |      |                    | 
 +            | QSPI_D1 ​      ​| ​                 |             ​| ​             |                  |          |      |                    | 
 +| 2             | QSPI_D2 ​      ​| ​                 |             ​| ​             |                  |          |      |                    | 
 +| 3             | QSPI_D3 ​      ​| ​                 |             ​| ​             |                  |          |         ​| ​                   | 
 +| 4             | QSPI_D0 ​      ​| ​                 |             ​| ​             |                  |          |         ​| ​                   | 
 +| 5             | QSPI_SS_OUTN ​ |                  |             ​| ​             |                  |          |         ​| ​                   | 
 +| 6(N/​C) ​       |               ​| ​                 |             ​| ​             |                  |             ​| ​        ​| ​                   |  
 +| 7             ​| ​              | PCIE_PERSTN ​     |             ​| ​             |                  |             ​| ​        ​| ​                   | 
 +| 8             ​| ​              ​| ​                 | DDR_SCL ​    ​| ​             |                  |             ​| ​        ​| ​                   | 
 +| 9             ​| ​              ​| ​                 | DDR_SDA ​    ​| ​             |                  |             ​| ​        ​| ​                   | 
 +| 10            |               ​| ​                 |             | BTN1         ​| ​                 |             ​| ​        ​| ​                   | 
 +| 11            |               ​| ​                 |             | BTN0         ​| ​                 |             ​| ​        ​| ​                   | 
 +| 12            |               ​| ​                 |             ​| ​             | WIFI_PORTEX_SCK ​ |             ​| ​   | |  | WIFI_PORTEX_SCK ​   | 
 +| 13            |               ​| ​                 |             ​| ​             |                  |             ​| ​   | |  | PORTEXP_RESETN ​    | 
 +| 14            |               ​| ​                 |             ​| ​             |                  |             ​| ​   | |  | PORTEX_SSN ​        | 
 +| 15            |               ​| ​                 |             ​| ​             | WIFI_SSN ​        ​| ​            ​| ​        ​| ​                   | 
 +| 16            |               ​| ​                 |             ​| ​             | WIFI_PORTEX_MISO |             ​| ​   | |  |  WIFI_PORTEX_MISO ​ | 
 +| 17            |               ​| ​                 |             ​| ​             | WIFI_PORTEX_MOSI |             ​| ​   | |  |  WIFI_PORTEX_MOSI ​ | 
 +| 18            |               ​| ​                 |             ​| ​             |                  | UART_TXD_IN |         | | 
 +| 19            |               ​| ​                 |             ​| ​             |                  | UART_RXD_OUT| ​        | | 
 +| 20            |               | PCIE_WAKEN ​      ​| ​            ​| ​             |                  |             ​| ​        | | 
 +| 21            |               ​| ​                 |             ​| ​             |                  |             | LD0     | | 
 +| 22            |               ​| ​                 |             ​| ​             |                  |             ​| ​        | MUX_SCL_LS| 
 +| 23            |               ​| ​                 |             ​| ​             |                  |             ​| ​        | MUX_SDA_LS| 
 +| 24            |               ​| ​                 |             ​| ​             |                  |             ​| ​        | | USB30_INTN | 
 +| 25            |               ​| ​                 |             ​| ​             |                  |             ​| ​   | |  | PORTEXP_INTN | 
 + 
 +**Note:** The WI-FI signals are shared by the same bus that goes through the I/O expander. 
 +<-- 
 + 
 +--> MIO 26-51 : Bank 501 # 
 + 
 +|  **MIO 501 1.8V** ​ |  **Peripherals** ​ || 
 +| Pin                | Ethernet ​      | SD              | 
 +| 26                 | ETH_TX_CLK ​    ​| ​                ​| ​  
 +| 27                 | ETH_TX_D0 ​     |                 ​| ​   
 +| 28                 | ETH_TX_D1 ​     |                 ​| ​        
 +| 29                 | ETH_TX_D2 ​     |                 ​| ​       
 +| 30                 | ETH_TX_D3 ​     |                 ​| ​       
 +| 31                 | ETH_TX_CTL ​    ​| ​                ​| ​       
 +| 32                 | ETH_RX_CLK ​    ​| ​                ​| ​       
 +| 33                 | ETH_RX_D0 ​     |                 ​| ​       
 +| 34                 | ETH_RX_D1 ​     |                 ​| ​      
 +| 35                 | ETH_RX_D2 ​     |                 ​| ​   
 +| 36                 | ETH_RX_D3 ​     |                 ​| ​        
 +| 37                 | ETH_RX_CTL ​    ​| ​                ​| ​       
 +| 38                 | ETH_INTN_PWDNN |                 ​| ​      
 +| 39                 ​| ​               | SDIO_SEL ​       |      
 +| 40                 ​| ​               | SDIO_DIR_CMD ​   |      
 +| 41                 ​| ​               | SDIO_DIR_DAT0 ​  ​| ​       
 +| 42                 ​| ​               | SDIO_DIR_DAT1_3 |    
 +| 43                 ​| ​               | SDIO_POW_EN ​    ​| ​          
 +| 44                 ​|ETH_RSTN ​       |                 ​| ​          
 +| 45                 ​| ​               | SDIO_CDN ​       |         
 +| 46                 ​| ​               | SDIO_R_DAT0 ​    ​| ​        
 +| 47                 ​| ​               | SDIO_R_DAT1 ​    ​| ​         
 +| 48                 ​| ​               | SDIO_R_DAT2 ​    ​| ​        
 +| 49                 ​| ​               | SDIO_R_DAT3 ​    ​| ​        
 +| 50                 ​| ​               | SDIO_R_CMD ​     |                  
 +| 51                 ​| ​               | SDIO_R_SCLK ​    |  
 + 
 +<-- 
 + 
 +--> MIO 52-77 : Bank 502 # 
 + 
 +|  **MIO 502 1.8V** ​ |  **Peripherals** ​          || 
 +| Pin                | USB 2.0        | Ethernet ​               | 
 +| 52                 | USB20_CLK ​     |                         ​| ​   
 +| 53                 | USB20_DIR ​     |                         ​| ​     
 +| 54                 | USB20_DATA2 ​   |                         ​| ​       
 +| 55                 | USB20_NXT ​     |                         ​| ​      
 +| 56                 | USB20_DATA0 ​   |                         ​| ​       
 +| 57                 | USB20_DATA1 ​   |                         ​| ​     
 +| 58                 | USB20_STP ​     |                         ​| ​  
 +| 59                 | USB20_DATA3 ​   |                         ​| ​      
 +| 60                 | USB20_DATA4 ​   |                         ​| ​     
 +| 61                 | USB20_DATA5 ​   |                         ​| ​     
 +| 62                 | USB20_DATA6 ​   |                         ​| ​      
 +| 63                 | USB20_DATA7 ​   |                         ​| ​      
 +| 64                 | USB20H_CLK ​    ​| ​         |     
 +| 65                 | USB20H_DIR ​    ​| ​         |      
 +| 66                 | USB20H_DATA2 ​  ​| ​         |     
 +| 67                 | USB20H_NXT ​    ​| ​         |      
 +| 68                 | USB20H_DATA0 ​  ​| ​         |     
 +| 69                 | USB20H_DATA1 ​  ​| ​         |        
 +| 70                 | USB20H_STP ​    ​| ​         |    
 +| 71                 | USB20H_DATA3 ​  ​| ​         |         
 +| 72                 | USB20H_DATA4 ​  ​| ​         |         
 +| 73                 | USB20H_DATA5 ​  ​| ​         |        
 +| 74                 | USB20H_DATA6 ​  ​| ​         |        
 +| 75                 | USB20H_DATA7 ​  ​| ​         |      
 +| 76                 ​| ​               | ETH_MDC ​ |  
 +| 77                 ​| ​               | ETH_MDIO |  
 + 
 +<-- 
 + 
 +---- 
 +===== Functional Description ===== 
 + 
 +==== 1. Power Supplies ​==== 
 + 
 +=== 1.1. Power Input ===
  
 The Genesys ZU power distribution network was designed to meet the specific requirements of Xilinx Zynq UltraScale+ MPSoCs and of the supported peripheral devices. Power to the board is provided via a 2x3 PCIe ATX power connector. Xilinx evaluation boards use a pinout that is not compatible with ATX, therefore mixing power supplies is not possible. The bundled supply is 12V 60W-100W, depending on variant. The Genesys ZU power distribution network was designed to meet the specific requirements of Xilinx Zynq UltraScale+ MPSoCs and of the supported peripheral devices. Power to the board is provided via a 2x3 PCIe ATX power connector. Xilinx evaluation boards use a pinout that is not compatible with ATX, therefore mixing power supplies is not possible. The bundled supply is 12V 60W-100W, depending on variant.
 The board power supplies are turned on or off with the SW5 slide switch. The board power supplies are turned on or off with the SW5 slide switch.
  
-==== 1.2 Power Specifications ​====+---- 
 +=== 1.2Power Specifications ===
  
-Figure 1.1 gives an overview of the Genesys ZU power distribution network. ​+Figure 1.2.1 gives an overview of the Genesys ZU power distribution network. ​
  
 \\ \\
  
-{{ :​reference:​programmable-logic:​genesys-zu:​pdn_bloc.png?​1000 | Figure 1.1. Genesys ZU power distribution network and supply sequencing}} +{{ :​reference:​programmable-logic:​genesys-zu:​pdn_bloc.png?​1000 | Figure 1.2.1. Genesys ZU power distribution network and supply sequencing}} 
-//Figure 1.1. Genesys ZU power distribution network and supply sequencing//​+<​html><​center></​html>​ 
 +//Figure 1.2.1: Genesys ZU power distribution network and supply sequencing//​ 
 +<​html></​center></​html>​
  
 \\ \\
Line 96: Line 247:
 During normal operation the MOSFETs provide a low impedance path and the VCC12V0 net is correctly biased with 12V. This voltage serves both as output rail for the FMC port and power input for downstream voltages. During normal operation the MOSFETs provide a low impedance path and the VCC12V0 net is correctly biased with 12V. This voltage serves both as output rail for the FMC port and power input for downstream voltages.
  
-Table 1.1 describes the list of power supply rails implemented on Genesys ZU. This table can be used to estimate the available power budget for a given project. ​ +Table 1.2.1 describes the list of power supply rails implemented on Genesys ZU. This table can be used to estimate the available power budget for a given project. ​
- +
-\\+
  
-//Table 1.1. Genesys ZU power rails//+//Table 1.2.1: Genesys ZU power rails//
 ^ **Voltage Rail** ​                ^ **Generated from** ​ | **Min/​Typ/​Max Voltage** ​                                      | **Max current** ​ | **Used for**                                                                                                                                                          | ^ **Voltage Rail** ​                ^ **Generated from** ​ | **Min/​Typ/​Max Voltage** ​                                      | **Max current** ​ | **Used for**                                                                                                                                                          |
 | VCC12V0 ​                         | 12V power input     | 12V+-5% ​                                                      | 8.5A             | FMC, power input for other rails                                                                                                                                      | | VCC12V0 ​                         | 12V power input     | 12V+-5% ​                                                      | 8.5A             | FMC, power input for other rails                                                                                                                                      |
 | VCC5V0_STABLE ​                   | VCC12V0 ​            | 5V+-5% ​                                                       | 0.306A ​          | IC81+IC80 , VCC3V3_STABLE ​                                                                                                                                            | | VCC5V0_STABLE ​                   | VCC12V0 ​            | 5V+-5% ​                                                       | 0.306A ​          | IC81+IC80 , VCC3V3_STABLE ​                                                                                                                                            |
-| VCC5V0 ​                          | VCC12V0 ​            | 5V+-5% ​                                                       | 3.49A            ​| SYZYGY, RGB LED, Audio, USB-s, HDMI Rx AUX                                                                                                                            |+| VCC5V0 ​                          | VCC12V0 ​            | 5V+-5% ​                                                       | 4A               | SYZYGY, RGB LED, Audio, USB-s, HDMI Rx AUX                                                                                                                            |
 | VCC3V3_STABLE ​                   | VCC5V0_STABLE ​      | 3.16V / 3.3V / 3.465V ​                                        | 0.224A ​          | Platform MCU, Supply I2C pull-ups, FMC, SFP, HDMI Clock, PCIe REFCLK ​                                                                                                 | | VCC3V3_STABLE ​                   | VCC5V0_STABLE ​      | 3.16V / 3.3V / 3.465V ​                                        | 0.224A ​          | Platform MCU, Supply I2C pull-ups, FMC, SFP, HDMI Clock, PCIe REFCLK ​                                                                                                 |
 | VCC3V3 ​                          | VCC12V0 ​            | 3.154V / 3.3V / 3.4V                                          | 7.64A            | DDR4 VDDSPD (I2C interface), PCAMs, LEDs, SFP, HDMI, FMC, FPGA Internals, SYZYGY, PMODs, PCIe, SD Card, WI-FI, USB 3.0, USB 2.0 Hub, USB Config, Display Port, Flash  | | VCC3V3 ​                          | VCC12V0 ​            | 3.154V / 3.3V / 3.4V                                          | 7.64A            | DDR4 VDDSPD (I2C interface), PCAMs, LEDs, SFP, HDMI, FMC, FPGA Internals, SYZYGY, PMODs, PCIe, SD Card, WI-FI, USB 3.0, USB 2.0 Hub, USB Config, Display Port, Flash  |
 | VADJ                             | VCC12V0 ​            | Selectable - 1.2V / 1.5V / 1.8V +- 5%                         | 2.4A             | FMC, SYZYGY, FPGA                                                                                                                                                     | | VADJ                             | VCC12V0 ​            | Selectable - 1.2V / 1.5V / 1.8V +- 5%                         | 2.4A             | FMC, SYZYGY, FPGA                                                                                                                                                     |
 | VCC2V5 ​                          | VCC12V0 ​            | 2.375V / 2.5V / 2.625V ​                                       | 2.1A             | DDR4 VPP, MGT Oscillators,​ Ethernet ​                                                                                                                                  | | VCC2V5 ​                          | VCC12V0 ​            | 2.375V / 2.5V / 2.625V ​                                       | 2.1A             | DDR4 VPP, MGT Oscillators,​ Ethernet ​                                                                                                                                  |
-| VCC1V8_AUX ​                      | VCC12V0 ​            | 1.746V / 1.8V / 1.854V ​                                       | 1.1A             | FPGA Internals, Ethernet, DisplayPort,​ Audio, USB 3.0, USB 2.0, USB Prog, SD Card                                                                                     |+| VCC1V8_AUX ​                      | VCC12V0 ​            | 1.746V / 1.8V / 1.854V ​                                       | 1.59A            ​| FPGA Internals, Ethernet, DisplayPort,​ Audio, USB 3.0, USB 2.0, USB Prog, SD Card                                                                                     |
 | VCC1V8_MGT ​                      | VCC2V7_LDOIN ​       | 1.746V / 1.8V / 1.854V ​                                       | 0.09A            | FPGA Internals ​                                                                                                                                                       | | VCC1V8_MGT ​                      | VCC2V7_LDOIN ​       | 1.746V / 1.8V / 1.854V ​                                       | 0.09A            | FPGA Internals ​                                                                                                                                                       |
 | VCC1V5_PCI ​                      | VCC12V0 ​            | 1.5V=-5% ​                                                     | 0.5A             | PCIe port                                                                                                                                                             | | VCC1V5_PCI ​                      | VCC12V0 ​            | 1.5V=-5% ​                                                     | 0.5A             | PCIe port                                                                                                                                                             |
Line 123: Line 272:
 | VREF0V6 ​                         | VCC1V2_PSDDR ​       | 0.6V (0.49xVCC1V2_PSDDR... ...0.51xVCC1V2_PSDDR) ​             | 0.01A            | DDR4 reference voltage ​                                                                                                                                               | | VREF0V6 ​                         | VCC1V2_PSDDR ​       | 0.6V (0.49xVCC1V2_PSDDR... ...0.51xVCC1V2_PSDDR) ​             | 0.01A            | DDR4 reference voltage ​                                                                                                                                               |
  
-==== 1.3 Power Sequencing ​==== +---- 
-The board is powered up by sliding the SW5 switch to the ON position. The voltage supplies start-up sequence is defined by implementing a power good daisy chain that selectively enables groups of voltages that should start together. All supplies use a soft start mechanism to reduce the surge currents during turn on. The start-up sequence is suggested in Figure 1.1 and can be described in the following steps:+=== 1.3Power Sequencing === 
 +The board is powered up by sliding the SW5 switch to the ON position. The voltage supplies start-up sequence is defined by implementing a power good daisy chain that selectively enables groups of voltages that should start together. All supplies use a soft start mechanism to reduce the surge currents during turn on. The start-up sequence is suggested in Figure 1.2.1 and can be described in the following steps:
  
   - When the ramping VCC12V0 exceeds the turn-ON threshold of IC78, the VCC5V0_STABLE rail starts up. This triggers the VCC3V3_STABLE supply and powers the IC81 internal logic. The VCC3V3_STABLE rail powers the platform MCU. Its valid state is marked by the green **<color #​22b14c>​Aux power ON</​color>​** LED (LD19). ​   - When the ramping VCC12V0 exceeds the turn-ON threshold of IC78, the VCC5V0_STABLE rail starts up. This triggers the VCC3V3_STABLE supply and powers the IC81 internal logic. The VCC3V3_STABLE rail powers the platform MCU. Its valid state is marked by the green **<color #​22b14c>​Aux power ON</​color>​** LED (LD19). ​
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   - If VCC5V0 reaches its power-good threshold, the //​PGOOD0=En1//​ signal is asserted. This enables the VCC0V85_INT,​ <wrap hi>​VCC0V9_MGTAVCC*</​wrap>,​ VCC2V7_LDOIN and <wrap hi>​VCC0V9_VCU*</​wrap>​ voltages. The power-good signals of all these supplies are joined in a wired AND configuration and activate //PGOOD1// when all rails have reached their nominal voltages. ​   - If VCC5V0 reaches its power-good threshold, the //​PGOOD0=En1//​ signal is asserted. This enables the VCC0V85_INT,​ <wrap hi>​VCC0V9_MGTAVCC*</​wrap>,​ VCC2V7_LDOIN and <wrap hi>​VCC0V9_VCU*</​wrap>​ voltages. The power-good signals of all these supplies are joined in a wired AND configuration and activate //PGOOD1// when all rails have reached their nominal voltages. ​
   - When all voltages from the first starting group have crossed their power-good thresholds, the //​PGOOD1=En2//​ signal is asserted. This enables the VCC1V8_AUX and VCC0V85_PSMGTRAVCC voltages of the second group.   - When all voltages from the first starting group have crossed their power-good thresholds, the //​PGOOD1=En2//​ signal is asserted. This enables the VCC1V8_AUX and VCC0V85_PSMGTRAVCC voltages of the second group.
-  - A similar trigger mechanism applies to the third (//​PGOOD2=En3//​) and the fourth (//​PGOOD3=En4//​) voltage groups as illustrated in Figure 1.1. The fourth group also includes the dedicated DDR4 power supply with all its output voltages.+  - A similar trigger mechanism applies to the third (//​PGOOD2=En3//​) and the fourth (//​PGOOD3=En4//​) voltage groups as illustrated in Figure 1.2.1. The fourth group also includes the dedicated DDR4 power supply with all its output voltages.
   - If all voltages from the fourth group have succesfully reached their designed values, their power-good (//​PG_ALL//​) lights up the green **<color #​22b14c>​Main Power ON</​color>​** LED (LD20). At this point the board is fully functional. ​     - If all voltages from the fourth group have succesfully reached their designed values, their power-good (//​PG_ALL//​) lights up the green **<color #​22b14c>​Main Power ON</​color>​** LED (LD20). At this point the board is fully functional. ​  
  
-**Note:** the VADJ rail is controlled separately by the platform MCU that must first set VADJ depending on the peripherals using thos voltage. VADJ is in the fourth start-up group but it is conditioned by a valid //​EN_VADJ_CTRL//​ signal generated by the platform MCU.                                                        ​+**Note:** the VADJ rail is controlled separately by the platform MCU that must first set VADJ depending on the peripherals using those voltage. VADJ is in the fourth start-up group but it is conditioned by a valid //​EN_VADJ_CTRL//​ signal generated by the platform MCU.                                                        ​
  
 \\ \\
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 Sliding the SW5 switch to the OFF position disables the power supplies by pulling //​INPUT_PGD//​ to ground. The capacitor C405 connected to the //EN// terminal of the LM5060 monitoring IC delays the VCC12V0 turn off with approximately 200ms until all power supplies have been safely powered off.  Sliding the SW5 switch to the OFF position disables the power supplies by pulling //​INPUT_PGD//​ to ground. The capacitor C405 connected to the //EN// terminal of the LM5060 monitoring IC delays the VCC12V0 turn off with approximately 200ms until all power supplies have been safely powered off. 
  
 +----
 +=== 1.4. Earthing/​Grounding System ​ ===
  
-===== 2 MPSoC Boot Process ===== +The bundled power supply has a 3-pin AC power cord and internally shorts the DC negative terminal to the earth/​ground circuit of the power socket. Therefore, the Genesys ZU's ground circuits are at earth potential. In lieu of a metallic case the Genesys ZU has an internal shield ring at the edge of the board encircling it. The metallic pads of screws, feet and stand-offs (except the top right corner and Zmod stand-offs),​ but also the shell of connectors are wired to the shield ring. The shield ring ultimately connects to the Genesys ZU's ground circuit through a 2 mOhm resistor. There are also several capacitor pads (not loaded) around the board between the shield ring and the ground circuit. The screws on the edge of the board (except the top-right corner) can be used to wire an additional earth/​ground connection to the Genesys ZU. 
-<WRAP center ​round todo 60%+---- 
-Short overview of boot process, link to Xilinx for the restList boot modes available on the Genesys ZU. Describe the 4 status LEDs +==== 2MPSoC Boot Process ==== 
-</WRAP>+{{ :​reference:​programmable-logic:​genesys-zu:​gzu-config.png?​1000 |}} 
 +<html><​center></​html
 +//Figure 2.1: Genesys ZU Boot Diagram// 
 +<​html></​center>​</html>
  
-==== 2.1 JTAG Boot Mode ==== +=== 2.1JTAG Boot Mode === 
-==== 2.2 microSD Boot Mode ==== +JTAG is the most important component of the debug features for software and PL development. 
-==== 2.3 Quad SPI Boot Mode ==== +The JTAG architecture has three Test Access Port (TAP) controllers:​ 
-==== 2.4 USB Boot Mode ==== +  - PS TAP (main PS controller with IDCODE) 
-It is the only boot mode apart from JTAG where the MPSoC takes a slave role. It shows up as a DFU (Device Firmware Upgrade) USB device to the PC, waiting for a configuration.+  - PL TAP (used for PL configuration and boundary scan) 
 +  - DAP (used for ARM debugging, Real time processing unit (RPU) and Application Processing Unit (APU)) 
 + 
 +Taking into account this architecture,​ when placed in JTAG boot mode, the processor (APU) will wait until software is loaded by a host computer using the Xilinx tools. After software has been loaded, it is possible to either let the software begin executing, or step through it line by line using Xilinx SDK. 
 + 
 +It is also possible to directly configure the PL over JTAG, independent of the processor. This can be done using the Vivado Hardware Server. 
 + 
 +The Genesys ZU is configured to boot in Cascaded JTAG mode, which allows the PS to be accessed via the same JTAG port as the PL. 
 + 
 +You need a JTAG programmer to connect into the JTAG chain of the Genesys ZU. There is an on-board USB-JTAG controller for which Vivado support is expected in version 2020.1. Until built-in Vivado support is available a Digilent JTAG-HS1 or JTAG-HS2 programming cable will be bundled with the kit. This cable connects to the 6-pin header J28 and is already supported by Vivado. 
 + 
 +Connecting both the on-board programmer and the bundled programming cable to the PC might cause conflict in Vivado Hardware Server with not the right cable being opened and no targets being found. The solution is launching Hardware Server manually before any connection attempt is made, or after killing any automatically launched instances of hw_server.exe. Launching Hardware Server manually can be done from the Vivado Tcl Shell using the command below. 
 +<​code>​ 
 +Vivado% hw_server -e "set jtag-port-filter 210205,​210249"​ 
 +WARNING: [Common 17-259] Unknown Tcl command '​hw_server -e set jtag-port-filter 210205,​210249'​ sending command to the OS shell for execution. It is recommended to use '​exec'​ to send the command to the OS shell. 
 + 
 +****** Xilinx hw_server v2019.1 
 +  **** Build date : May 24 2019 at 15:13:31 
 +    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 + 
 +INFO: hw_server application started 
 +INFO: Use Ctrl-C to exit hw_server application 
 + 
 +INFO: To connect to this hw_server instance use url: TCP:<​hostname>:​3121 
 +</​code>​ 
 + 
 +Vivado Hardware Server is launched in the shell and will be listening until the shell is closed. All other Xilinx tools will automatically connect to this instance of the Hardware Server. 
 + 
 +For more details about JTAG see "JTAG Functional Description"​ section in [[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug1085-zynq-ultrascale-trm.pdf|Zynq UltraScale+ Device Technical Reference Manual (UG1085)]]. 
 +---- 
 +=== 2.2microSD Boot Mode === 
 +The Genesys ZU supports booting from a microSD card inserted into connector J9. The SD supported version is 3.0. This boot mode suport FAT 16/32 file systems for reading the boot images. Image search for multi-boot is supported. For SD boot mode, the boot image file should be at the root of first partition of the SD card (not inside any directory). The following procedure will allow you to boot the Zynq UltraScale+ from microSD with a standard Zynq UltraScale+ Boot Image created with the Xilinx tools: 
 +  - Format the microSD card with a FAT32 file system. 
 +  - Copy the Zynq UltraScale+ Boot Image created with Xilinx SDK to the microSD card. 
 +  - Rename the Zynq UltraScale+ Boot Image on the microSD card to BOOT.bin. 
 +  - Eject the microSD card from your computer and insert it into connector J9 on the Genesys ZU. 
 +  - Attach a power source to the Genesys ZU. 
 +  - Place a single jumper on JP3, shorting the pins labeled “SD”. 
 +  - Turn the board on. The board will now boot the image on the microSD card. 
 + 
 +For more details about SD boot mode see "SD Boot Mode" section in [[https://​www.xilinx.com/​content/​dam/​xilinx/​support/​documentation/​user_guides/​ug1137-zynq-ultrascale-mpsoc-swdev.pdf|Zynq UltraScale+ MPSoC Software Developer Guide (UG1137]]). 
 + 
 +---- 
 +=== 2.3Quad SPI Boot Mode === 
 +The Genesys ZU has an on-board 256Mbit Quad-SPI Flash from ISSI that the Zynq UltraScale+ can boot from. Documentation available from Xilinx describes how to use Xilinx SDK to program a Zynq UltraScale+ Boot Image into a Flash device attached to the Zynq UltraScale+. Once the Quad SPI Flash has been loaded with a Zynq UltraScale+ Boot Image, the following steps can be followed to boot from it: 
 +  - Attach a power source to the Genesys ZU. 
 +  - Place a single jumper on JP3, shorting the two center pins (labeled “QSPI”). 
 +  - Turn the board on. The board will now boot the image stored in the Quad SPI flash. 
 + 
 +For more details about Quad SPI boot mode see "​QSPI24 and QSPI32 Boot Modes" section in [[https://​www.xilinx.com/​content/​dam/​xilinx/​support/​documentation/​user_guides/​ug1137-zynq-ultrascale-mpsoc-swdev.pdf|Zynq UltraScale+ MPSoC Software Developer Guide (UG1137]]). 
 + 
 +---- 
 +=== 2.4USB Boot Mode === 
 +It is the only boot mode apart from JTAG where the MPSoC takes a slave role. It shows up as a DFU (Device Firmware Upgrade) USB device to the PC, waiting for a configuration. ​Using this boot mode you will be able to load the newly created image on Zynq UltraScale+ via the USB Port. For more details see the "Boot Sequence for USB Boot Mode" mode in [[https://​www.xilinx.com/​support/​documentation/​sw_manuals/​xilinx2019_1/​ug1209-embedded-design-tutorial.pdf|Zynq UltraScale+ MPSoC: Embedded Design Tutorial (UG1209)]]. 
 + 
 +---- 
 +=== 2.5. Status LEDs === 
 +The Genesys ZU has four status LEDs: 
 +  - ERR : it is asserted for accidental loss of power, a hardware error or an exception in the Platform Management Unit (PMU); 
 +  - STS : it is asserted in secure lockdown state; 
 +  - INIT : indicates the PL is initialized after the power-on reset (POR); 
 +  - DONE : it is asserted when the PL configuration is completed;
  
-===== 3 Main Memory ​=====+==== 3Main Memory ====
 Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the PS (Processing System) side using the hard-core memory controller. ​ Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the PS (Processing System) side using the hard-core memory controller. ​
 The bundled module is a 4GiB Kingston HyperX HX424S14IB/​4. Although the module supports DDR4-2400 CL14-14-14 timing, data rate is limited by the MPSoC and the board. The 5EV board variant supports <wrap hi>​DDR4-2133*</​wrap>,​ while the 3EG supports DDR4-1866. The bundled module is a 4GiB Kingston HyperX HX424S14IB/​4. Although the module supports DDR4-2400 CL14-14-14 timing, data rate is limited by the MPSoC and the board. The 5EV board variant supports <wrap hi>​DDR4-2133*</​wrap>,​ while the 3EG supports DDR4-1866.
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 Although the bundled module is not ECC-capable,​ the Genesys ZU is. Just pair it with an ECC module and enable the feature in the Vivado MPSoC PS Configuration Wizard. Although the bundled module is not ECC-capable,​ the Genesys ZU is. Just pair it with an ECC module and enable the feature in the Vivado MPSoC PS Configuration Wizard.
  
-==== 3.1 Implementation ​==== +=== 3.1Implementation === 
-There is a single SODIMM slot on the top side of the Genesys ZU just north of the MPSoC. It is wired to the PS-side memory controller and supports any SODIMM module complying with the memory controller'​s restrictions. These are detailed in the Zynq UltraScale+ Device ​TRM (UG1085), but common modules of 1R/2R, x8/x16, 64b/72b are supported.+There is a single SODIMM slot on the top side of the Genesys ZU just north of the MPSoC. It is wired to the PS-side memory controller and supports any SODIMM module complying with the memory controller'​s restrictions. These are detailed in the [[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug1085-zynq-ultrascale-trm.pdf|Zynq UltraScale+ Device ​Technical Reference Manual ​(UG1085)]], but common modules of 1R/2R, x8/x16, 64b/72b are supported.
  
 The serial presence detect (SPD) interface is wired to MIO8 (DDR_SCL) and MIO9 (DDR_SDA), accessible through the I2C1 controller. ​ The serial presence detect (SPD) interface is wired to MIO8 (DDR_SCL) and MIO9 (DDR_SDA), accessible through the I2C1 controller. ​
  
-For better routing some byte swaps were performed detailed in Table. No nibble or bit swaps were needed.+For better routing some byte swaps were performed detailed in Table 3.1.1. No nibble or bit swaps were needed. 
 + 
 +//Table 3.1.1: DDR4 interface byte swaps.//
 ^ System ​ | 7  | 6  | 5  | 4  | 3  | 2  | 1  | 0  | 8  | ^ System ​ | 7  | 6  | 5  | 4  | 3  | 2  | 1  | 0  | 8  |
 ^ Slot    | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  | ^ Slot    | 0  | 1  | 2  | 3  | 4  | 5  | 6  | 7  | 8  |
-Table DDR4 interface byte swaps. 
  
 ECC byte (lane 8) is equivalent to any of the data bytes from the perspective of the DRAM components. The controller and SODIMM connector have dedicated ECC pins (CBx), which are not used on non-ECC systems. Therefore the ECC lane (CBx) cannot be swapped with other lanes. However, byte and bit swaps in data lanes are transparent to the ECC feature since any swap performed upon write is reversed back upon read. ECC byte (lane 8) is equivalent to any of the data bytes from the perspective of the DRAM components. The controller and SODIMM connector have dedicated ECC pins (CBx), which are not used on non-ECC systems. Therefore the ECC lane (CBx) cannot be swapped with other lanes. However, byte and bit swaps in data lanes are transparent to the ECC feature since any swap performed upon write is reversed back upon read.
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 CRC is calculated both by the controller and the DRAM to avoid data corruption in the the write data burst. It can detect single bit, double bit, odd count and one multi-bit UI vertical column errors. Upon error detection, DRAM will assert the ALERT_n line. The controller should retry the write upon error. CRC is calculated both by the controller and the DRAM to avoid data corruption in the the write data burst. It can detect single bit, double bit, odd count and one multi-bit UI vertical column errors. Upon error detection, DRAM will assert the ALERT_n line. The controller should retry the write upon error.
  
-It should be enabled in systems that expect a high amount of signal integrity issues and where high reliability is desired. It trades data bandwidth ​for reliability. CRC support is optional in SODIMM modules. Even if the module supports it, implementation is not easy. For CRC to work the controller must know what pin swaps were performed on the memory interface. In case of SODIMM modules, there are some restricted pin swaps possible and must be documented in the SPD EEPROM. The controller is expected to read these, combine it with pin swaps on the system board and assign the bits to CRC inputs accordingly. According to AR# 68788 this can be achieved through the DDRC.DQMAP registers, not well documented. +It should be enabled in systems that expect a high amount of signal integrity issues and where high reliability is desired. It trades data rate for reliability. CRC support is optional in SODIMM modules. Even if the module supports it, implementation is not easy. For CRC to work the controller must know what pin swaps were performed on the memory interface. In case of SODIMM modules, there are some restricted pin swaps possible and must be documented in the SPD EEPROM. The controller is expected to read these, combine it with pin swaps on the system board and assign the bits to CRC inputs accordingly. According to [[https://​www.xilinx.com/​support/​answers/​68788.html|AR# 68788]] this can be achieved through the DDRC.DQMAP registers, not well documented.
-===== 4 Storage =====+
  
-==== 4.1 Quad-SPI Flash ==== +---- 
-<WRAP center round todo 60%> +==== 4. Storage ​====
-SFP+ MAC address location, qspi connection figure +
-</​WRAP>​+
  
 +=== 4.1. Quad-SPI Flash ===
 The Genesys ZU features a serial flash memory from ISSI. This memory is used to The Genesys ZU features a serial flash memory from ISSI. This memory is used to
 provide non-volatile code and data storage. It can be used to initialize the provide non-volatile code and data storage. It can be used to initialize the
 PS subsystem as well as configure the PL. PS subsystem as well as configure the PL.
 The key device attributes are: The key device attributes are:
-  * Part number: IS25LP256D +  * Part number: IS25LP256D-JMLE 
-  * Size: 256Mbit / 23Mbyte+  * Size: 256Mbit / 32Mbyte
   * 1-bit, 2-bit and 4-bit bus widths supported   * 1-bit, 2-bit and 4-bit bus widths supported
   * 80MHz Normal Read, Up to 166MHz Fast Read   * 80MHz Normal Read, Up to 166MHz Fast Read
-  * Up to 664MHz ​in quad-spi mode+  * Up to 664Mb/​s ​in quad-spi mode
   * Powered from 3.3V   * Powered from 3.3V
  
 The Flash is also commonly used to store non-configuration data needed by the The Flash is also commonly used to store non-configuration data needed by the
-application. If doing this from a bare-metal application, ​The flash memory can+application. If doing this from a bare-metal application, ​the flash memory can
 be freely accessed using standalone libraries included with a Xilinx SDK BSP be freely accessed using standalone libraries included with a Xilinx SDK BSP
 project. If doing this from a Petalinux generated embedded Linux system, the project. If doing this from a Petalinux generated embedded Linux system, the
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 information. information.
  
-The Flash connects to the Quad-SPI Flash controller of the Zynq UltraScale via+The Flash connects to the Quad-SPI Flash controller of the Zynq UltraScalevia
 pins in MIO Bank 0/500 (specifically MIO[0:5]). pins in MIO Bank 0/500 (specifically MIO[0:5]).
  
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 blocks. A block consists of 8/16 adjacent sectors. blocks. A block consists of 8/16 adjacent sectors.
  
-The memory is divided into uniform 4 KByte sectors or uniform 32/64 Kbyte +Two globally unique MAC address are programmed in the last sector, sector 8191.
-blocks. A block consists of 8/16 adjacent sectors.+
   * MAC for Ethernet PHY is stored at address 0x1FFF000   * MAC for Ethernet PHY is stored at address 0x1FFF000
-  * MAC for SFP+ (5EV only) is stored at address ​....+  * MAC for SFP+ (5EV only) is stored at address ​0x1FFF006
  
 The last sector, used to store the MAC addresses, is protected from write and The last sector, used to store the MAC addresses, is protected from write and
-erase. Any attempt to program or erase the last sector will fail.+erase. Any attempt to program or erase the last sector will fail. Consequently,​ blank check operations (like the one in Vivado Hardware Manager) are also expected to fail, even after a full device erase, if the last sector is not ignored.
  
 The ISSI flash features an Advanced Sector/​Block Protection mechanism. Every The ISSI flash features an Advanced Sector/​Block Protection mechanism. Every
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 factory. If TBPARM is programmed to 0, an attempt to change it back to 1 will factory. If TBPARM is programmed to 0, an attempt to change it back to 1 will
 fail and ignore the program operation. For more details about the Advanced fail and ignore the program operation. For more details about the Advanced
-Sector/​Block Protection mechanism consult the manufacturer'​s datasheet.+Sector/​Block Protection mechanism consult the manufacturer'​s ​[[http://​www.issi.com/​WW/​pdf/​IS25LP(WP)256D.pdf|datasheet]].
  
 To protect the MAC addresses from the last sector, Genesys ZU comes with TBPARM To protect the MAC addresses from the last sector, Genesys ZU comes with TBPARM
 programmed to 0 and the PPB bits for the last sector programmed to 0. programmed to 0 and the PPB bits for the last sector programmed to 0.
  
 +{{ :​reference:​programmable-logic:​genesys-zu:​gzu-flash.png?​400 |}}
 +<​html><​center></​html>​
 +//Figure 4.1.1: Genesys ZU Quad SPI Flash//
 +<​html></​center></​html>​
  
-==== 4.2 microSD slot ====+---- 
 +=== 4.2microSD slot ===
 The microSD connector J9 located on the top side has a hinge-based mechanism. It is compatible with UHS-I allowing 1.8V signalling and speeds up to SDR104, or 104MB/s. The microSD connector J9 located on the top side has a hinge-based mechanism. It is compatible with UHS-I allowing 1.8V signalling and speeds up to SDR104, or 104MB/s.
 +To enable UHS-I support and speeds up to SDR104, see the following Answer Records from Xilinx: [[https://​www.xilinx.com/​support/​answers/​69978.html|]] and [[https://​www.xilinx.com/​support/​answers/​70062.html|]].
  
-==== 4.3 mSATA slot ==== +---- 
-The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile SSD storage. Both half and full-size modules are supported. Since PCIe and SATA share the same GTR lanes, one has to disable PCIe first to enable SATA.+=== 4.3mSATA slot === 
 +The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile ​<​nowiki>​SSD</​nowiki> ​storage. Both half and full-size modules are supported. Since PCIe and SATA share the same GTR lanes, one has to disable PCIe first to enable SATA.
  
 +----
 +==== 5. Oscillators/​Clocks ====
  
-===== 5 Network Connectivity ===== +The PS on Genesys ZU has clock source ​of 30MHz on pin R16 (PS_REF_CLK),​ coming ​from IC67 (5P49V6965A244NLGI).
-==== 5.1 Wi-Fi ==== +
-A Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the MPSoC on the PS-side over SPI, supporting ​maximum theoretical bandwidth ​of 48Mbps. The ATWINC1500 can be used in bare-metal applications with the full IP stack included in the firmware loaded ​from flash. However, it is also supported in Linux in the ATWILC1000-compatible mode, where the firmware is loaded on-the-fly upon boot and the OS IP stack is used.+
  
-==== 5.2 1G Ethernet ​====+The PL on Genesys ZU has a clock source of (by default) 25MHz on pin E12 (SYSCLK), coming from the CLK_OUT pin of the Ethernet PHY IC36 (DP83867CRRGZR). This LVCMOS18 I/O standard clock can be used for any purpose in the PL, with certain restrictions:​ 
 +  * It enters the FPGA via HDGC (High-Density I/O Bank Global Clock) pins. These can only directly drive BUFGCE primitives, not MMCM/PLL primitives. See Global Clock Inputs in [[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug572-ultrascale-clocking.pdf|ug572]]. It can still drive MMCM/PLL indirectly, but this will need a CLOCK_DEDICATED_ROUTE FALSE constraint, otherwise Vivado DRC will fail. 
 +  * Is available whenever the PHY is out of reset and is not specifically configured through its registers to disable this clock. By default it is synchronous to the crystal input of the Ethernet PHY (25 MHz). 
 + 
 +<WRAP center round todo 60%> 
 +Add info on GTR and GTH reference clocks 
 +</​WRAP>​ 
 + 
 +---- 
 +==== 6. Reset Sources ==== 
 + 
 +The Genesys ZU provides several different methods of resetting the Zynq Ultrascale+ device, as described in the following sections. 
 + 
 +=== 6.1 Power-on Reset === 
 + 
 +The Zynq Ultrascale+ PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Genesys ZU drives this signal from the PG_ALL signal of the power supplies in order to hold the system in reset until all power supplies are valid. The Genesys ZU also has a red push button, labeled POR, which can toggle the power-on reset of the Zynq Ultrascale+. 
 + 
 +=== 6.2 Programmable Logic Reset === 
 + 
 +A red push button, labeled PROG, toggles the Zynq Ultrascale+'​s PS_PROG_B input. This resets the PL and causes DONE to be de-asserted. The PL will remain unconfigured until it is reprogrammed by the processor or via JTAG.  
 + 
 +=== 6.3 Processor Subsystem Reset === 
 + 
 +The external system reset button, labeled SRST, resets the Zynq Ultrascale+ device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing boot moode jumpers a power-on reset is needed to act on the new setting.  
 + 
 +For more details about configuration pins see "​Clock,​ Reset, and Configuration Pins" section in [[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug1085-zynq-ultrascale-trm.pdf|Zynq UltraScale+ Device Technical Reference Manual (UG1085)]]. 
 + 
 +---- 
 +==== 7. Network Connectivity ==== 
 +=== 7.1. Wi-Fi === 
 +A Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the MPSoC on the PS-side over SPI, supporting a maximum theoretical data rate of 48Mbps. The ATWINC1500 can be used in bare-metal applications with the full IP stack included in the firmware loaded from flash. However, it is also supported in Linux in the ATWILC1000-compatible mode, where the firmware is loaded on-the-fly upon boot and the OS IP stack is used. 
 + 
 +---- 
 +=== 7.2. 1G Ethernet ===
 The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the MPSoC via RGMII for data and MDIO for management. The auxiliary interrupt (ETH_INTN_PWDNN) and reset (ETH_RSTN) signals also connect to MIO Bank 501. The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the MPSoC via RGMII for data and MDIO for management. The auxiliary interrupt (ETH_INTN_PWDNN) and reset (ETH_RSTN) signals also connect to MIO Bank 501.
  
Line 255: Line 509:
 The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The PHY is configured to insert a delay of 2.0ns between RXD/CTL and RXC, and a delay of 1.5ns between TXD/CTL and TXC. The RGMII specification calls for the receive (RXC) and transmit clock (TXC) to be delayed relative to the data signals (RXD[0:3], RXCTL and TXD[0:3], TXCTL). Xilinx PCB guidelines also require this delay to be added. The PHY is configured to insert a delay of 2.0ns between RXD/CTL and RXC, and a delay of 1.5ns between TXD/CTL and TXC.
  
-On an Ethernet network each node needs a unique MAC address. To this end, the last sector of the Quad-SPI flash has been programmed at the factory with a 48-bit globally unique EUI-48/​64™ compatible identifier. ​<WRAP center round todo 60%> +On an Ethernet network each node needs a unique MAC address. To this end, the last sector of the Quad-SPI flash has been programmed at the factory with a 48-bit globally unique EUI-48/​64™ compatible identifier. ​For more details about MAC address ​storage see [[#quad-spi_flash|Quad-SPI Flash]]
-Add note on address ​and how reading is handled in u-boot. Add link to Quad-SPI Flash section. +
-</​WRAP>​ +
- The identifier is also printed on a sticker found on next to the Ethernet jack+
  
-==== 5.10G SFP+ ====+U-Boot has been [[https://​github.com/​Digilent/​Genesys-ZU-OOB-os/​commit/​7eac6c368efd33042e95eb78abac5c16d87020c4|patched]] to read this MAC address and overwrite the existing node in the device tree binary before handing control over to the Linux kernel. 
 + 
 +The identifier is also printed on a sticker found next to the Ethernet jack (J14).  
 + 
 +---- 
 +=== 7.3. 10G SFP+ ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 Todo for 5EV. Todo for 5EV.
 </​WRAP>​ </​WRAP>​
  
-==== 5.WLAN, Bluetooth, WWAN ====+---- 
 +=== 7.4. WLAN, Bluetooth, WWAN ===
 The Mini PCIe socket allows you to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1 and USB 2.0 available in the socket, even dual Wi-Fi/​Bluetooth modules can be used. The primary use case is Linux OS, so modules with Linux drivers available in-kernel are recommended. For WWAN radio modules a SIM slot is present on the bottom side of the board. The Mini PCIe socket allows you to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1 and USB 2.0 available in the socket, even dual Wi-Fi/​Bluetooth modules can be used. The primary use case is Linux OS, so modules with Linux drivers available in-kernel are recommended. For WWAN radio modules a SIM slot is present on the bottom side of the board.
-===== 6 Peripheral Connectivity ​===== + 
-==== 6.1 USB Full-Featured Type-C ​====+---- 
 +==== 8. Peripheral Connectivity ==== 
 +=== 8.1USB Full-Featured Type-C ===
 USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle J6. The connector has a USB 2.0 pair for backward compatibility,​ one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is established during the configuration process over the CC1 and CC2 pins. Depending on the orientation,​ either pins with suffix 1 or pins with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer. USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle J6. The connector has a USB 2.0 pair for backward compatibility,​ one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is established during the configuration process over the CC1 and CC2 pins. Depending on the orientation,​ either pins with suffix 1 or pins with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer.
  
 Unlike the other USB connector types, Type-C does not inherently establish the relationship of host and device ports. This relationship is determined during the same configuration process. Unlike the other USB connector types, Type-C does not inherently establish the relationship of host and device ports. This relationship is determined during the same configuration process.
  
-On the Genesys ZU, data behavior is Dual-Role-Data (DRD), ie. can behave either as a Downstream-Facing Port (DFP) or an Upstream-Facing Port (UFP), depending on the connected partner and MPSoC configuration. Power behavior is Dual-Role-Power (DRP), but even if UFP is negotiated, the board remains self-powered. In DFP role the advertised current capability and limit is 0.9A with the possibility of increasing it to 1.5A. USB Power Delivery is not supported.+On the Genesys ZU, data behavior is Dual-Role-Data (DRD), ie. can behave either as a Downstream-Facing Port (DFP) or an Upstream-Facing Port (UFP), depending on the connected partner and MPSoC configuration. Power behavior is Dual-Role-Power (DRP), but even if UFP is negotiated, the board remains self-powered. In DFP role the advertised current capability and limit is 0.9 A with the possibility of increasing it to 1.5 A. USB Power Delivery is not supported.
  
 Management of the Type-C port is handled by a companion chip, the TI TUSB322I. It handles attachment, cable orientation,​ role detection and current advertisment. It connects to the main I<​sup>​2</​sup>​C bus of the board and can be used to read status and set port roles for Type-C. It responds to address 1000111b on branch 3 of the I<​sup>​2</​sup>​C multiplexer. Management of the Type-C port is handled by a companion chip, the TI TUSB322I. It handles attachment, cable orientation,​ role detection and current advertisment. It connects to the main I<​sup>​2</​sup>​C bus of the board and can be used to read status and set port roles for Type-C. It responds to address 1000111b on branch 3 of the I<​sup>​2</​sup>​C multiplexer.
Line 279: Line 538:
 The USB 2.0 pair is implemented by a Microchip USB3320 PHY interfacing with the PS-side controller of MPSoC over ULPI. The USB 3.1 lane is implemented using a PS-GTR transceiver lane. The USB 2.0 pair is implemented by a Microchip USB3320 PHY interfacing with the PS-side controller of MPSoC over ULPI. The USB 3.1 lane is implemented using a PS-GTR transceiver lane.
  
-In the box you can find a USB Type-C Legacy Adapter reference as CAR3G1-3 in the Type-C specifications. It has a Full-Features ​Type-C plug on one end and a USB 3.1 Standard-A receptacle on the other. Use it to connect non-Type-C USB 2.0 or USB 3.1 devices to the Genesys ZU. +In the box you can find a USB Type-C Legacy Adapter reference as CAR3G1-3 in the Type-C specifications. It has a Full-Featured ​Type-C plug on one end and a USB 3.1 Standard-A receptacle on the other. Use it to connect non-Type-C USB 2.0 or USB 3.1 devices to the Genesys ZU. 
-==== 6.2 USB 2.0 Host ====+ 
 +---- 
 +=== 8.2USB 2.0 Host ===
 Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to the PS-side controller of MPSoC over ULPI. Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to the PS-side controller of MPSoC over ULPI.
-The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port. This allows interfacing Bluetooth modules, for example.+The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port. This allows interfacing ​with Bluetooth modules, for example.
  
-==== 6.3 USB 2.0 - JTAG/Serial Bridge ​====+---- 
 +=== 8.3USB 2.0 - JTAG/Serial Bridge ===
 The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration,​ but the first one will always connect to the MPSoC and the second one to the Platform MCU. The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration,​ but the first one will always connect to the MPSoC and the second one to the Platform MCU.
-The MPSoC UART interface is wired to the PS-side MIO Bank 500: UART_TXD_IN to MIO18 and UART_RXD_OUT to MIO19. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. +The MPSoC UART interface is wired to the PS-side MIO Bank 500: UART_TXD_IN to MIO18 and UART_RXD_OUT to MIO19. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC (e.g. UART_TXD_IN is the TXD signal of the DTE, meaning it is an output of the DTE and an input of the DCE)
-The Digilent USB-JTAG function and the USB-UART functions behave independent of one another. Support for USB-JTAG in Vivado is expected in version 2020.1.+The Digilent USB-JTAG function and the USB-UART functions behave independent of one another. Support for USB-JTAG in Vivado is expected in version 2020.1. Read more in section [[reference-manual#​jtag_boot_mode|JTAG Boot Mode]].
  
-===== 7.Multimedia ​===== +---- 
-==== 7.1 DisplayPort Source ​=====+==== 9. Multimedia ==== 
 +=== 9.1DisplayPort Source ===
 The dual-lane mini DisplayPort connector J27 is wired to a PS-side DisplayPort Controller via two PS-GTR transceiver lanes. Resolutions up to [email protected] are supported at a maximum 5.4Gbps line rate.  The dual-lane mini DisplayPort connector J27 is wired to a PS-side DisplayPort Controller via two PS-GTR transceiver lanes. Resolutions up to [email protected] are supported at a maximum 5.4Gbps line rate. 
-==== 7.2 HDMI Source ​=====+ 
 +---- 
 +=== 9.2HDMI Source ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 TODO for 5EV TODO for 5EV
 </​WRAP>​ </​WRAP>​
-==== 7.3 HDMI Sink =====+ 
 +---- 
 +=== 9.3HDMI Sink ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 TODO for 5EV TODO for 5EV
 </​WRAP>​ </​WRAP>​
-==== 7.4 Audio Codec =====+ 
 +---- 
 +=== 9.4Audio Codec ===
 The Genesys ZU board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC39) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J20-green),​ headphone-out (J19-black),​ line-in (J22-blue), and microphone-in (J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono. The Genesys ZU board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC39) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J20-green),​ headphone-out (J19-black),​ line-in (J22-blue), and microphone-in (J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono.
  
Line 323: Line 592:
 All relevant information can be found in the [[http://​www.analog.com/​media/​en/​technical-documentation/​data-sheets/​ADAU1761.pdf|ADAU1761 datasheet]]. All relevant information can be found in the [[http://​www.analog.com/​media/​en/​technical-documentation/​data-sheets/​ADAU1761.pdf|ADAU1761 datasheet]].
  
-==== 7.5 MIPI/Pcam Ports ===== +---- 
-The two MIPI/Pcam ports included on the Genesys ZU are 15-pin, 1 mm pitch, zero insertion force (ZIF) connector ​designed specifically for attaching camera sensor modules to host systems. It builds on the Pcam connector standard introduced on the Digilent Zybo Z7, but allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture. Therefore, it supports MIPI DSI applications too, while remaining backward compatible with MIPI CSI-2 Pcam modules, like the Digilent Pcam 5C.+=== 9.5MIPI/Pcam Ports === 
 +The two MIPI/Pcam ports included on the Genesys ZU are 15-pin, 1 mm pitch, zero insertion force (ZIF) connectors ​designed specifically for attaching camera sensor modules to host systems. It builds on the Pcam connector standard introduced on the Digilent Zybo Z7, but allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture. Therefore, it supports MIPI DSI applications too, while remaining backward compatible with MIPI CSI-2 Pcam modules, like the Digilent Pcam 5C.
  
-The Pcam connector pin-out is rigidly defined and includes a two lane MIPI CSI-2 bus for camera data, an I<​sup>​2</​sup>​C bus for camera configuration,​ two additional general purpose signals, and 3.3 V for powering the camera module, as depicted in Figure ​15.1 and Table 15.1. Digilent is developing a catalog of Pcam peripheral camera modules with various different types of sensors that all conform to this pin-out. The pin-out was also chosen so that many camera modules designed to work with the Raspberry Pi will also work when connected to the Pcam port.  +The Pcam connector pin-out is rigidly defined and includes a two lane MIPI CSI-2 bus for camera data, an I<​sup>​2</​sup>​C bus for camera configuration,​ two additional general purpose signals, and 3.3 V for powering the camera module, as depicted in Figure ​9.5.1 and Table 9.5.1. Digilent is developing a catalog of Pcam peripheral camera modules with various different types of sensors that all conform to this pin-out. The pin-out was also chosen so that many camera modules designed to work with the Raspberry Pi will also work when connected to the Pcam port. 
- +
-{{ :​reference:​programmable-logic:​zybo-z7:​zybo-z7-pcam-pins.png?​600 | Figure 15.1. Pcam Pin-out}} +
-//Figure 15.1. Pcam Pin-out//+
  
 +{{ :​reference:​programmable-logic:​zybo-z7:​zybo-z7-pcam-pins.png?​600 | Figure 9.5.1. Pcam Pin-out}}
 +<​html><​center></​html>​
 +//Figure 9.5.1: Pcam Pin-out//
 +<​html></​center></​html>​
  
 +//Table 9.5.1: Pcam Pin-out//
 ^ Pin Number ​ ^ Function ​              ^ Genesys ZU Implementation ​                                      ^ ^ Pin Number ​ ^ Function ​              ^ Genesys ZU Implementation ​                                      ^
 | 1           | GND                    | GND                                                              | | 1           | GND                    | GND                                                              |
Line 348: Line 620:
 | 14          | SDA                    | Connects to branch 0 (MIPI A) and branch 1 (MIPI B) of the main I<​sup>​2</​sup>​C bus multiplexer ​                | | 14          | SDA                    | Connects to branch 0 (MIPI A) and branch 1 (MIPI B) of the main I<​sup>​2</​sup>​C bus multiplexer ​                |
 | 15          | 3V3                    | 3.3 V Power rail                                                 | | 15          | 3V3                    | 3.3 V Power rail                                                 |
- 
-//Table 15.1. Pcam Pin-out// 
  
 Pcam modules are connected to the Pcam host port using a flexible flat cable (FFC). To connect the cable to the Genesys ZU follow these instructions:​ Pcam modules are connected to the Pcam host port using a flexible flat cable (FFC). To connect the cable to the Genesys ZU follow these instructions:​
Line 357: Line 627:
   - Insert the FFC with the contacts facing the left edge, away from the center of the Genesys ZU.   - Insert the FFC with the contacts facing the left edge, away from the center of the Genesys ZU.
   - Ensure the FFC is fully inserted. ​   - Ensure the FFC is fully inserted. ​
-  - Gently press down on both sides of the off-white colored tab to latch the FFC into the connector.+  - Gently press down on both sides of the white colored tab to latch the FFC into the connector.
   - The FFC is now connected properly.   - The FFC is now connected properly.
  
-===== 8 Expansion Ports ===== +---- 
-==== 8.1 Mini PCIe / mSATA ==== +==== 10. Expansion Ports ==== 
-J13 socket implements a versatile expansion ​options ​for adding SSD, WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocateable ​stand-offs included with the board. Electrically,​ the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board USB hub and the MPSoC USB1 controller up the chain.+=== 10.1Mini PCIe / mSATA === 
 +J13 socket implements a versatile expansion ​option ​for adding ​<​nowiki>​SSD</​nowiki>​, WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocatable ​stand-offs included with the board. Electrically,​ the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board USB hub and the MPSoC USB1 controller up the chain.
  
-==== 8.2 Low-Pin Count FMC Connector ​==== +---- 
-The Genesys ZU includes ​FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard. ​ Genesys ZU-based designs can now be easily extended with custom or off-the-shelf high-performance modules.+=== 10.2Low-Pin Count FMC Connector === 
 +The Genesys ZU includes ​an FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard. Genesys ZU-based designs can now be easily extended with custom or off-the-shelf high-performance modules.
  
 The actual connector used is a 160-pin Samtec ASP-134603-01,​ the low-pin count, 10mm stacking height variant of the standard. All user defined signals are bonded to the PL-side of the MPSoC to HP banks 64 and 65. <wrap hi>On the 5EV variant the multi-gigabit transceiver lane is also wired to the PL-side GTH transceiver,​ sharing the lane with the SFP+ slot.*</​wrap> ​ The 34 differential pairs are powered by the Genesys ZU VADJ rail adjustable in the 1.2 V - 1.8 V range. The actual connector used is a 160-pin Samtec ASP-134603-01,​ the low-pin count, 10mm stacking height variant of the standard. All user defined signals are bonded to the PL-side of the MPSoC to HP banks 64 and 65. <wrap hi>On the 5EV variant the multi-gigabit transceiver lane is also wired to the PL-side GTH transceiver,​ sharing the lane with the SFP+ slot.*</​wrap> ​ The 34 differential pairs are powered by the Genesys ZU VADJ rail adjustable in the 1.2 V - 1.8 V range.
 +There is also a 12 V rail wired to the FMC connector, which can supply up to 1 A to the mezzanine card.
  
 <WRAP center round important 90%> <WRAP center round important 90%>
Line 381: Line 654:
 Each transceiver lane includes a receive pair and a transmit pair. Lane DP0 is wired through the mux to quad 224. The reference clock GBTCLK0 goes to a jitter filter and can be sent to MGTREFCLK0 pins of the same quad. Each transceiver lane includes a receive pair and a transmit pair. Lane DP0 is wired through the mux to quad 224. The reference clock GBTCLK0 goes to a jitter filter and can be sent to MGTREFCLK0 pins of the same quad.
    
-Table 12 shows how the FMC gigabit signals are mapped to pins and GTH primitives. Refer to the UltraScale Architecture GTH Transceivers User Guide ([[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug576-ultrascale-gth-transceivers.pdf|ug576]]) for more information.</​wrap>​+Table 10.2.1 ​shows how the FMC gigabit signals are mapped to pins and GTH primitives. Refer to the UltraScale Architecture GTH Transceivers User Guide ([[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug576-ultrascale-gth-transceivers.pdf|ug576]]) for more information.</​wrap>​
  
 +//Table 10.2.1: FMC Gigabit Signals Mapping//
 ^ Quad  ^ Primitive ​            |^ Pin type    ^ Pin    ^ FMC signal ​  ^ ^ Quad  ^ Primitive ​            |^ Pin type    ^ Pin    ^ FMC signal ​  ^
 | 224   | GTHE4_CHANNEL ​ | X0Y7  | MGTHTXP/​N3 ​ | N4/N3  | DP0_C2M_P/​N ​ | | 224   | GTHE4_CHANNEL ​ | X0Y7  | MGTHTXP/​N3 ​ | N4/N3  | DP0_C2M_P/​N ​ |
 | :::   | :::            | :::   | MGTHRXP/​N3 ​ | P2/P1  | DP0_M2C_P/​N ​ | | :::   | :::            | :::   | MGTHRXP/​N3 ​ | P2/P1  | DP0_M2C_P/​N ​ |
  
-Table 12.+For FMC designs which use FMC_LA_07_P/​_N and/or FMC_LA15_P/​_N lines with an I/O standard which needs DCI, please make sure you add the DCIRESET primitive to the respective designs. Refer to the UltraScale Architecture SelectIO Resources User Guide ([[https://​www.xilinx.com/​support/​documentation/​user_guides/​ug571-ultrascale-selectio.pdf|ug571]]) chapter "​Special DCI Requirements in Some Banks" for more information.
  
 +//Table 10.2.2: Maximum length mismatch including MPSoC package delay.//
 ^ Signal Group                                    ^  Length matching ​              || ^ Signal Group                                    ^  Length matching ​              ||
 | :::                                             ^ Intra-pair ​       ^ Inter-pair ​ ^ | :::                                             ^ Intra-pair ​       ^ Inter-pair ​ ^
 | LA[00-33], CLK[0-1]_M2C ​                        | 1 mm              | 10 mm       | | LA[00-33], CLK[0-1]_M2C ​                        | 1 mm              | 10 mm       |
 | <wrap hi>​DP0*</​wrap>,​ <wrap hi>​GBTCLK0*</​wrap> ​ | 0.14 mm           | 100 mm      | | <wrap hi>​DP0*</​wrap>,​ <wrap hi>​GBTCLK0*</​wrap> ​ | 0.14 mm           | 100 mm      |
- 
-Table Maximum length mismatch including MPSoC package delay. 
  
 <WRAP center round todo 60%> <WRAP center round todo 60%>
Line 400: Line 673:
 </​WRAP>​ </​WRAP>​
  
-==== 8.3 Zmod ====+---- 
 +=== 10.3Zmod ===
 The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. The port is compatible with version 1.1 of the SYZYGY specification from Opal Kelly. The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. The port is compatible with version 1.1 of the SYZYGY specification from Opal Kelly.
  
Line 409: Line 683:
 </​WRAP>​ </​WRAP>​
  
-Each SYZYGY Standard interface contains 14 single-ended I/O pins (2 of which I<​sup>​2</​sup>​C),​ 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. The Zmod port is wired to PL-side MPSoC banks powered by the VADJ rail, sharing them with FMC signals. Therefore if both an FMC mezzanine card and a Zmod is connected to the Genesys ZU, a common voltage supported by both needs to be chosen for VADJ. +Each SYZYGY Standard interface contains 14 single-ended I/O pins (2 of which I<​sup>​2</​sup>​C),​ 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. The Zmod port is wired to PL-side MPSoC banks powered by the VADJ rail, sharing them with FMC signals. Therefore if both an FMC mezzanine card and a Zmod are connected to the Genesys ZU, a common voltage supported by both needs to be chosen for VADJ. 
-The differential pairs were prioritized and wired to HP banks, allowing the maximum data rates supported by the SelectI/O architecture. However, the single-ended pins are wired to HD banks, limiting the data rate to 250 Mb/s according to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (d925).+The differential pairs were prioritized and wired to HP banks, allowing the maximum data rates supported by the SelectI/O architecture. However, the single-ended pins are wired to an HD bank, limiting the data rate to 250 Mb/s according to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics ​[[https://​www.xilinx.com/​support/​documentation/​data_sheets/​ds925-zynq-ultrascale-plus.pdf|(ds925)]].
 Template constraints for the Zmod port can be found in the Genesys ZU's Master XDC file, available through Digilent'​s [[https://​github.com/​Digilent/​digilent-xdc|digilent-xdc]] repository on Github. Template constraints for the Zmod port can be found in the Genesys ZU's Master XDC file, available through Digilent'​s [[https://​github.com/​Digilent/​digilent-xdc|digilent-xdc]] repository on Github.
 +
 +The two standoffs located on the sides of the Zmod port, on the top side of the Genesys ZU board, are hexagonal, 5 mm tall with M2.5 x 0.45 internal threaded holes. For mounting Zmods on Genesys ZU, two screws with M2.5 x 0.45 thread and 3mm thread length would be needed.
  
 For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]]. For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]].
  
-=== 8.3.1 SYZYGY Pod Compatibility ==+---- 
- +== 10.3.1SYZYGY Pod Compatibility ==
-The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required to determine if the Genesys ZU is compatible with a certain pod is summarized in Table 8.1.1.+
  
-//Table 8.1.1. SYZYGY Compatibility Table//+The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required to determine if the Genesys ZU is compatible with a certain pod is summarized in Table 10.3.1.1.
  
 +//Table 10.3.1.1: SYZYGY Compatibility//​
 ^ Parameter ​                 ^ Port A (STD)             ^ ^ Parameter ​                 ^ Port A (STD)             ^
 ^ Port Type                  | Standard ​                | ^ Port Type                  | Standard ​                |
Line 432: Line 708:
 ^ Length Matching ​           | 10 mm inter-pair, 1mm intra-pair | ^ Length Matching ​           | 10 mm inter-pair, 1mm intra-pair |
  
-=== 8.3.2 Mechanical ===+---- 
 +== 10.3.2 ==
  
 FIXME //Is there any information on this not encapsulated by the syzygy spec?// FIXME //Is there any information on this not encapsulated by the syzygy spec?//
Line 440: Line 717:
 </​WRAP>​ </​WRAP>​
  
 +----
 +=== 10.4. Pmod ===
  
-==== 8.4 Pmod ==== +Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure ​10.4.1 below. For more information regarding ​the power supply specifications ​of the Pmod ports, refer to the [[https://​www.digilentinc.com/​Pmods/​Digilent-Pmod_%20Interface_Specification.pdf|Digilent Pmod™ Interface Specification]],​ "Power Supply"​ section.
- +
-Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure ​bellowThe VCC and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets ​of the onboard regulators or the external power supply.+
  
 +{{ :​basys3-pmod_connector.png?​350 | Figure 10.4.1. Pmod port}}
 <​html><​center></​html>​ <​html><​center></​html>​
-{{:​basys3-pmod_connector.png?​350|Figure 13.1. Pmod connector.}} +//​Figure ​10.4.1: Pmod port//
- +
-//Figure . Pmod port//+
 <​html></​center></​html>​ <​html></​center></​html>​
  
-Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod ports to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information. The vivado-library and vivado-hierarchies repositories on the [[https://​github.com/​Digilent/​|Digilent Github]] contains pre-made IP cores for many of these Pmods that greatly ​reduces ​the work of integrating them into your project. See the Pmod-related tutorials on the Genesys ZU Resource Center for help using them.+Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod ports to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information. The vivado-library and vivado-hierarchies repositories on the [[https://​github.com/​Digilent/​|Digilent Github]] contains pre-made IP cores for many of these Pmods that greatly ​reduce ​the work of integrating them into your project. See the Pmod-related tutorials on the Genesys ZU Resource Center for help using them.
  
 --> PMODS JA, JB, JC, JD # --> PMODS JA, JB, JC, JD #
Line 468: Line 744:
 <-- <--
  
-==== 8.5 Dual Digital/​Analog Pmod ====+---- 
 +=== 10.5Dual Digital/​Analog Pmod ===
 On the Genesys ZU, one of the Pmod connectors is not like the others. Designated by JA, the Pmod connector is wired to pins that can serve as auxiliary inputs to the system monitor ADC inside the MPSoC. These pins are in a VADJ-powered bank, so the VCC pins are not powered from the 3.3 V rail, like on regular Pmods, but from VADJ. VADJ on the Genesys ZU is in the 1.2 V - 1.8 V range. Pins 1-7, 2-8, 3-9, 4-10 are paired and routed differentially. On the Genesys ZU, one of the Pmod connectors is not like the others. Designated by JA, the Pmod connector is wired to pins that can serve as auxiliary inputs to the system monitor ADC inside the MPSoC. These pins are in a VADJ-powered bank, so the VCC pins are not powered from the 3.3 V rail, like on regular Pmods, but from VADJ. VADJ on the Genesys ZU is in the 1.2 V - 1.8 V range. Pins 1-7, 2-8, 3-9, 4-10 are paired and routed differentially.
 Although these pins can be used in digital mode, the particularities of this connector must be taken into account when connecting Pmod modules to it. Although these pins can be used in digital mode, the particularities of this connector must be taken into account when connecting Pmod modules to it.
-===== 9 Basic I/O ===== 
-The Genesys ZU includes five push-buttons,​ four switches and one tri-color LED connected to the Zynq PL, as shown in Figure bellow. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output). 
  
 +----
 +==== 11. Basic I/O ====
 +The Genesys ZU includes five push-buttons,​ four slide switches, one tri-color LED and four green LEDs connected to the Zynq PL, as shown in Figure 11.1 below. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output). The five push-buttons are arranged in a plus-sign configuration (center, left, right, up and down buttons, respectively).
  
-{{ :​reference:​programmable-logic:​genesys-zu:​genesys_zu_basic_ioi.png?nolink ​|}} + 
-//​Figure ​12.1: Genesys ZU Basic I/O//+{{ :​reference:​programmable-logic:​genesys-zu:​basic_io_genesys_zu.png?600 |}} 
 +<​html><​center></​html>​ 
 +//​Figure ​11.1: Genesys ZU PL Basic I/O// 
 +<​html></​center></​html>​
 <​html><​left></​html>​ <​html><​left></​html>​
  
-=== 9.1 Push-Buttons ===+Genesys ZU also has two push-buttons and one green LED connected to the Zynq PS: push-buttons BTN0 and BTN1 are connected to MIO11 and MIO10, respectively,​ and the green LED is connected to MIO21. 
 + 
 +---- 
 +=== 11.1Push-Buttons ===
  
 The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed.
  
-=== 9.2 Tri-Color LED ===+---- 
 +=== 11.2. Slide Switches === 
 +The slide switches generate constant high or low inputs depending on their position: when the slide is in a low position (i.e. close to the lower board edge), the generated input is low; when the slide is in a high position (i.e. close to the center of the board), the generated input is high. 
 + 
 +---- 
 +=== 11.3. Tri-Color LED ===
  
 The tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the input signal corresponding to one of these colors low will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding PL pins need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color. The tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the input signal corresponding to one of these colors low will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding PL pins need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color.
Line 490: Line 779:
  
 ---- ----
-===== 10 Platform Management ​=====+=== 11.4. Green LEDs ==
 +The individual high-efficiency LEDs are anode-connected to the Zynq Ultrascale+ via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their corresponding I/O pin. 
 +---- 
 +==== 12. Platform Management ====
 Tying all the features of the Genesys ZU together into a computing platform requires an embedded controller independent of the MPSoC. We call it Platform MCU. Part of the platform is the coin battery, the fan, a temperature sensor inside the MPSoC and Power Management Units (PMU). Management is done through dedicated signals or over the main I<​sup>​2</​sup>​C bus. Tying all the features of the Genesys ZU together into a computing platform requires an embedded controller independent of the MPSoC. We call it Platform MCU. Part of the platform is the coin battery, the fan, a temperature sensor inside the MPSoC and Power Management Units (PMU). Management is done through dedicated signals or over the main I<​sup>​2</​sup>​C bus.
-==== 10.1 Main I2C bus ====+=== 12.1Main I2C bus ===
 Almost all I<​sup>​2</​sup>​C-capable peripherals are accessible through the main I<​sup>​2</​sup>​C bus. Multiple masters have access: Almost all I<​sup>​2</​sup>​C-capable peripherals are accessible through the main I<​sup>​2</​sup>​C bus. Multiple masters have access:
   * Platform MCU in the Auxiliary 3.3 V domain through MUX_SCL and MUX_SDA,   * Platform MCU in the Auxiliary 3.3 V domain through MUX_SCL and MUX_SDA,
Line 498: Line 790:
   * MPSoC PS-side in the Main 3.3 V domain through MUX_SCL_LS and MUX_SDA_LS in Bank 500,   * MPSoC PS-side in the Main 3.3 V domain through MUX_SCL_LS and MUX_SDA_LS in Bank 500,
   * MPSoC PL-size in the Main 3.3 V domain through MUX_SCL_LS and MUX_SDA_LS in Bank <wrap hi>​46*</​wrap>/​26.   * MPSoC PL-size in the Main 3.3 V domain through MUX_SCL_LS and MUX_SDA_LS in Bank <wrap hi>​46*</​wrap>/​26.
-It follows that any I<​sup>​2</​sup>​C master controller implementation in the MPSoC must be multi-master tolerant and support arbitration.+It follows that any I<​sup>​2</​sup>​C master controller implementation in the MPSoC must be multi-master tolerant and must support arbitration.
  
-The only slave device that can be accessed after power-on is an 8-channel I<​sup>​2</​sup>​C multiplexer,​ a TI TCA9578A, responding to address 1110000b. The rest of the slaves are distributed on the eight channels numbered from 0 to 7. To access a device on a particular channel, address the multiplexer first and write a single byte to it with the bit corresponding to the desired channel set to 1. After the STOP condition, the multiplexer will unite all the enabled channels and the main bus. Now a slave on the enabled channels can be accessed by its respective address. Make sure that there are no address conflicts on enabled channels. For example, having a Pcam 5C connected to each of the two MIPI/Pcam ports, and enabling both channel 0 and 1 simultaneously will cause a conflict. This might be desired, allowing writing the  same data to both Pcams, but reading is problematic and arbitration will happen. The recommended approach is having just one of the channels enabled at any time.+The only slave device that can be accessed after power-on is an 8-channel I<​sup>​2</​sup>​C multiplexer,​ a TI TCA9548A, responding to address 1110000b. The rest of the slaves are distributed on the eight channels numbered from 0 to 7. To access a device on a particular channel, address the multiplexer first and write a single byte to it with the bit corresponding to the desired channel set to 1. After the STOP condition, the multiplexer will unite all the enabled channels and the main bus. Now a slave on the enabled channels can be accessed by its respective address. Make sure that there are no address conflicts on enabled channels. For example, having a Pcam 5C connected to each of the two MIPI/Pcam ports, and enabling both channel 0 and 1 simultaneously will cause a conflict. This might be desired, allowing writing the  same data to both Pcams, but reading is problematic and arbitration will happen. The recommended approach is having just one of the channels enabled at any time.
  
 {{ :​reference:​programmable-logic:​genesys-zu:​gzu_i2c_diagram.png?​nolink |}} {{ :​reference:​programmable-logic:​genesys-zu:​gzu_i2c_diagram.png?​nolink |}}
-Figure Genesys ZU I<​sup>​2</​sup>​C topology.+<​html><​center></​html>​ 
 +//Figure ​12.1.1: ​Genesys ZU I<​sup>​2</​sup>​C topology// 
 +<​html></​center></​html>​
  
- +---- 
- +=== 12.2Platform MCU === 
-==== 10.2 Platform MCU ==== +The Platform MCU is implemented by a Microchip ATmega328PB. It is on the auxiliary 3.3V power domain, immediately available after power-up. This power domain is independent of the PMUs which provide ​main power, giving the Platform MCU control over main power. It also shares the main I<​sup>​2</​sup>​C bus with the MPSoC, giving it access to all the critical peripherals. Other features include MPSoC temperature sensing, fan speed control, and VADJ voltage setting.
-The Platform MCU is implemented by a Microchip ATmega328PB. It is on the auxiliary 3.3V power domain, immediately available after power-up. This power domain is independent of the PMUs providing ​main power, giving the Platform MCU control over main power. It also shares the main I<​sup>​2</​sup>​C bus with the MPSoC, giving it access to all the critical peripherals. Other features include MPSoC temperature sensing, fan speed control, and VADJ voltage setting. +
-<WRAP center round todo 60%> +
-Detail features, error codes, bootloader etc. +
-</​WRAP>​+
  
 The Platform MCU program memory has two sections: The Platform MCU program memory has two sections:
Line 517: Line 807:
   * Bootloader where the bootloader resides.   * Bootloader where the bootloader resides.
  
-=== 10.2.1 Application Section ​===+== 12.2.1Application Section ==
  
 The Platform MCU has the following interfaces on Genesys ZU: The Platform MCU has the following interfaces on Genesys ZU:
Line 532: Line 822:
  
 At board power-up, Platform MCU detects if a SYZYGY peripheral board (“Pod”) is At board power-up, Platform MCU detects if a SYZYGY peripheral board (“Pod”) is
-connected to Genesys ZU and signal ​this to the FPGA. If a SYZYGY Pod was detected, +connected to Genesys ZU and signals ​this to the FPGA. If a SYZYGY Pod was detected, 
-the SYZYGY_DETECTED ​pin (H11) is driven ​HIGH. Otherwise the pin is driven ​LOW.+the SYZYGY_DETECTEDN ​pin (H11) is driven ​LOW. Otherwise the pin is driven ​HIGH.
  
 If VADJ_AUTO pin (G10) from FPGA is LOW, the Platform MCU establishes the correct If VADJ_AUTO pin (G10) from FPGA is LOW, the Platform MCU establishes the correct
 VADJ voltage value based on VADJ_LEVEL1 (AC13) and VADJ_LEVEL0 (AC14) input pins, VADJ voltage value based on VADJ_LEVEL1 (AC13) and VADJ_LEVEL0 (AC14) input pins,
 regardless of whether a syzygy pod and/or FMC mezzanine module is connected. regardless of whether a syzygy pod and/or FMC mezzanine module is connected.
-The following table presents the VADJ level encoding.+Table 12.2.1.1 ​presents the VADJ level encoding. 
 + 
 +//Table 12.2.1.1: VADJ levels encoding//
 ^ VADJ_LEVEL1 ​ ^ VADJ_LEVEL0 ​ ^ VADJ level      ^ ^ VADJ_LEVEL1 ​ ^ VADJ_LEVEL0 ​ ^ VADJ level      ^
 |  0           ​| ​ 0           ​| ​ VADJ disabled ​ | |  0           ​| ​ 0           ​| ​ VADJ disabled ​ |
Line 550: Line 842:
 VADJ_AUTO signal value can change during board operation. The Platform MCU will VADJ_AUTO signal value can change during board operation. The Platform MCU will
 detect the pin change and will adjust the VADJ voltage level according to the detect the pin change and will adjust the VADJ voltage level according to the
-actual VADJ_LEVEL1 and VADJ_LEVEL0 pins state.+actual VADJ_LEVEL1 and VADJ_LEVEL0 pins state. The voltage rail will reach its power good threshold in maximum 60 ms after the falling edge of VADJ_AUTO. The power good threshold is set to 100 mV less than the nominal voltage.
  
-<WRAP center round important ​60%>+To set the desired VADJ level you have to: 
 +  - Drive the VADJ_LEVEL1 and VADJ_LEVEL0 to encode the desired VADJ level. 
 +  - Generate a falling edge condition on VADJ_AUTO. 
 + 
 +<WRAP center round important ​90%>
 In the current implementation,​ the FPGA must detect the correct VADJ level required In the current implementation,​ the FPGA must detect the correct VADJ level required
 by SYZYGY and FMC modules and must set the VADJ_LEVEL1 and VADJ_LEVEL0 signals by SYZYGY and FMC modules and must set the VADJ_LEVEL1 and VADJ_LEVEL0 signals
 accordingly. The VADJ_LEVEL1 and VADJ_LEVEL0 signals will be taken into account by the  accordingly. The VADJ_LEVEL1 and VADJ_LEVEL0 signals will be taken into account by the 
-Platform MCU only if the VADJ_AUTO signal is driven LOW by the FPGA. If VADJ_AUTO is HIGH  +Platform MCU only if the VADJ_AUTO signal is driven LOW by the FPGA. If VADJ_AUTO is HIGH 
-the VADJ is disabled.+the VADJ power rail is disabled.
 </​WRAP>​ </​WRAP>​
  
 On Genesys ZU there is a LED labeled with PMCU. This is the status led that is On Genesys ZU there is a LED labeled with PMCU. This is the status led that is
-used by Platform MCU to display the system fault that has the highest priority. +used by the Platform MCU to display the system fault that has the highest priority. 
-The blinking pattern for each fault is presented in the following table.+The blinking pattern for each fault is presented in Table 12.2.1.2.
  
 After Platform MCU startup, if no issues were encountered,​ this LED should blink After Platform MCU startup, if no issues were encountered,​ this LED should blink
Line 569: Line 865:
   * A “short blink” and a “short pause” last for about 200ms each;   * A “short blink” and a “short pause” last for about 200ms each;
  
 +//Table 12.2.1.2: Fault blink patterns//
 ^  Blink Pattern (Repeated) ​ ^  Issue            ^  Priority ​ ^  Comments ​            ^ ^  Blink Pattern (Repeated) ​ ^  Issue            ^  Priority ​ ^  Comments ​            ^
 |  Long Blink – Long Pause   ​| ​ Fan Speed Fault  |  0         ​| ​ Register 0x04 Bit 0  | |  Long Blink – Long Pause   ​| ​ Fan Speed Fault  |  0         ​| ​ Register 0x04 Bit 0  |
  
 The Platform MCU exposes to the PC a register interface, accessible via UART. The Platform MCU exposes to the PC a register interface, accessible via UART.
-The full register map is shown in the table below+The full register map is shown in Table 12.2.1.3. 
-^  Offset ​    ​^ ​ Register Name                      ^  Size [bits] ​ ^  R/W  ^  Description ​                                                                                                                                                                                                                                                           + 
-|  0x00       ​| ​ ID Register ​                       |  8            |  R    | It contains a fixed value, used for determining if the Platform MCU is alive and responding over UART e.g. 0x12345678                                                                                                                                                 +//Table 12.2.1.3: Register map// 
-|  0x01       ​| ​ Firmware Version ​                  ​| ​ 8            |  R    | It contains the firmware major version on bits 7-4 and the minor version on bits 3-0                                                                                                                                                                                    +^  Offset ​    ​^ ​ Register Name                      ^  Size [bits] ​ ^  R/W  ^  Description ​                                                                                                                                                                                                                                                                                                                                                                ​
-|  0x02       ​| ​ Scratch Register ​                  ​| ​ 8            |  R/W  | Read/write register used to test both the write and the read register interfaces. ​                                                                                                                                                                                      ​+|  0x00       ​| ​ ID Register ​                       |  8            |  R    | It contains a fixed value, used for determining if the Platform MCU is alive and responding over UART (0x00)                                                                                                                                                                                                                                                               
-|  0x03       ​| ​ Measured FPGA Core Temperature ​    ​| ​ 8            |  R    | FPGA Temperature value, as computed by the Platform MCU based on the thermal diode measurement. ​                                                                                                                                                                        ​+|  0x01       ​| ​ Firmware Version ​                  ​| ​ 8            |  R    | It contains the firmware major version on bits 7-4 and the minor version on bits 3-0                                                                                                                                                                                                                                                                                         ​
-|  0x04       ​| ​ Measured Fan Speed                 ​| ​ 16           ​| ​ R    | FPGA Fan Speed value, as computed based on the fan feedback pin.                                                                                                                                                                                                        +|  0x02       ​| ​ Scratch Register ​                  ​| ​ 8            |  R/W  | Read/write register used to test both the write and the read register interfaces. ​                                                                                                                                                                                                                                                                                           
-|  0x06       ​| ​ Fan Speed Fault                    |  8            |  8    | Bits 7-1: Unused \\ Bit 0: ‘1’ if fan speed is outside the expected range; ‘0’ otherwise ​                                                                                                                                                                               +|  0x03       ​| ​ Measured FPGA Core Temperature ​    ​| ​ 8            |  R    | FPGA Temperature value, as computed by the Platform MCU based on the thermal diode measurement. ​                                                                                                                                                                                                                                                                             
-^  0x07-0x0E ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                        ​+|  0x04       ​| ​ Measured Fan Speed                 ​| ​ 16           ​| ​ R    | FPGA Fan Speed value in rpm, as computed based on the fan feedback pin. Upon read, the low byte is received first. ​                                                                                                                                                                                                                                                          
-|  0x0F       ​| ​ Platform MCU Control ​              ​| ​ 8            |  R/W  | Bits 7-2: Unused \\ Bit 1: Fault Status: \\    -  ‘1’ = Clear all faults \\    -  [Default] ‘0’ = Do nothing \\ Bit 0: I2C Communication to PMUs Control: \\     - ‘1’ = I2C Communication to PMUs Disabled \\     - [Default] ‘0’ = I2C Communication to PMUs Enabled ​ | +|  0x06       ​| ​ Fan Speed Fault                    |  8            |  8    | Bits 7-1: Unused \\ Bit 0: ‘1’ if fan speed is outside the expected range; ‘0’ otherwise ​                                                                                                                                                                                                                                                                                    ​
-^  0x10-0x70 ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                        ​^+^  0x07-0x0E ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                                                                                                                             
 +|  0x0F       ​| ​ Platform MCU Control ​              ​| ​ 8            |  R/W  | Bits 7-2: Unused \\ Bit 1: Fault Status: \\     ​-  ‘1’ = Clear all faults \\     ​-  [Default] ‘0’ = Do nothing ​\\ Once written with ‘1’, this bit returns by itself to ‘0’ after all the faults have been cleared.\\ Bit 0: I2C Communication to PMUs Control: \\     - ‘1’ = I2C Communication to PMUs Disabled \\     - [Default] ‘0’ = I2C Communication to PMUs Enabled ​ | 
 +^  0x10-0x70 ​ ^  Reserved for future functionality ​ ^               ​^ ​      ​^ ​                                                                                                                                                                                                                                                                                                                                                                             ^
  
 When the PC wants to access a Platform MCU register, it needs to respect the following protocol: When the PC wants to access a Platform MCU register, it needs to respect the following protocol:
-  * It needs to send at first the address byte. Bits 7 to 1 of this byte contain the register start address (found in the first column from the table below). Bit 0 of this byte is logic ‘1’ for read transactions,​ and logic ‘0’ for write transactions.+  * It needs to send at first the address byte. Bits 7 to 1 of this byte contain the register start address (found in the first column from Table 12.2.1.3). Bit 0 of this byte is logic ‘1’ for read transactions,​ and logic ‘0’ for write transactions.
   * It then needs to send a second byte, containing the number of bytes to read/write.   * It then needs to send a second byte, containing the number of bytes to read/write.
   * For write transactions,​ it then needs to send the actual values to be written in the Platform MCU registers. The number of bytes sent in this phase needs to match the value from the previous byte (“the number of bytes to read/​write”),​ otherwise communication with the Platform MCU will hang.   * For write transactions,​ it then needs to send the actual values to be written in the Platform MCU registers. The number of bytes sent in this phase needs to match the value from the previous byte (“the number of bytes to read/​write”),​ otherwise communication with the Platform MCU will hang.
Line 592: Line 891:
   * For write transactions,​ the maximum length is 256 bytes. After such a transaction,​ wait for a minimum of 100ms before sending a new transaction (read or write) to the Platform MCU.   * For write transactions,​ the maximum length is 256 bytes. After such a transaction,​ wait for a minimum of 100ms before sending a new transaction (read or write) to the Platform MCU.
   * For consecutive write transactions,​ the total maximum length is 256 bytes. After such a transaction,​ wait for a minimum of 100ms before sending a new transaction (read or write) to the Platform MCU.   * For consecutive write transactions,​ the total maximum length is 256 bytes. After such a transaction,​ wait for a minimum of 100ms before sending a new transaction (read or write) to the Platform MCU.
 +  * All bytes to be sent to the PMCU need to have their nibbles converted to ASCII characters prior to being sent; e.g.: 0x0C in hex needs to be converted to “0C” in ASCII.
 +  * All characters received from the PMCU need to be converted from ASCII to hex nibbles after being received; e.g. “0C” received in ASCII format needs to be converted to 0x0C in hex.
  
 Write transaction example. Write transaction example.
 Let’s say the PC wants to clear all system faults. For this, it will send to the Platform MCU: Let’s say the PC wants to clear all system faults. For this, it will send to the Platform MCU:
-  * Byte 0: 0x1E (i.e. Bits 7-1 = 0x0F which is the address of Platform MCU register; Bit 0 = ‘0’ meaning write transaction) +  * Byte 0: 1E (i.e. Bits 7-1 = 0x0F which is the address of Platform MCU register; Bit 0 = ‘0’ meaning write transaction) 
-  * Byte 1: 0x01 (i.e. the PC want to write 1 byte) +  * Byte 1: 01 (i.e. the PC want to write 1 byte) 
-  * Byte 2: 0x02 (value to write to register at address 0x0F - Clear all faults)+  * Byte 2: 02 (value to write to register at address 0x0F - Clear all faults)
  
 Read transaction example. Read transaction example.
 Let’s say the PC wants to read Fan Speed Faults register from the Platform MCU. For this, it will send to the Platform MCU: Let’s say the PC wants to read Fan Speed Faults register from the Platform MCU. For this, it will send to the Platform MCU:
-  * Byte 0: 0x0D (i.e. Bits 7-1 = 0x06 which is the address of Fan Speed Fault register; Bit 0 = '​1'​ meaning read transaction) +  * Byte 0: 0D (i.e. Bits 7-1 = 0x06 which is the address of Fan Speed Fault register; Bit 0 = '​1'​ meaning read transaction) 
-  * Byte 1: 0x01 (i.e. the PC wants to read 1 byte)+  * Byte 1: 01 (i.e. the PC wants to read 1 byte)
 The Platform MCU will then send 1 byte back to the PC, containing the value of the Fan Speed Fault register. ​ The Platform MCU will then send 1 byte back to the PC, containing the value of the Fan Speed Fault register. ​
 +
 +To read a 16-bit register like Measured Fan Speed the PC will send to the Platform MCU:
 +  * Byte 0: 09 (i.e. Bits 7-1 = 0x04 which is the address of Measured Fan Speed register; Bit 0 = '​1'​ meaning read transaction)
 +  * Byte 1: 02 (i.e the PC wants to read 2 bytes)
 +The Platform MCU will then send 2 bytes back to the PC. The first byte that is sent is the least significant one. If one receives 150C one have to swap the first byte with the second one and to convert the value to decimal: 150C -> 0x0C15 -> 3093 RPM.
  
 The UART baudrate should be set to 115200/​8/​E/​1 (115200 baud, 8 data bits, even parity, 1 stop bit). The UART baudrate should be set to 115200/​8/​E/​1 (115200 baud, 8 data bits, even parity, 1 stop bit).
  
-=== 10.2.2 Bootloader Section ​===+---- 
 +== 12.2.2Bootloader Section ==
 In the program memory, along with the Firmware Application,​ there is a bootloader that launches the Application at power-up. In the program memory, along with the Firmware Application,​ there is a bootloader that launches the Application at power-up.
-==== 10.3 Fan ==== + 
-Mounted on the MPSoC heatsink is a 12 V fan with a 4-pin header. It can automatically controlled by the Platform MCU based on the MPSoC temperature or set to the fixed full speed. This option is controlled by JP2 and is user-selectable.+---- 
 +=== 12.3Fan === 
 +Mounted on the MPSoC heatsink, there is a 12 V fan with a 4-pin header. It can automatically ​be controlled by the Platform MCU based on the MPSoC temperature or set to the fixed full speed. This option is controlled by JP2 and is user-selectable. 
 + 
 +//Table 12.3.1: Fan jumper positions//
 ^ Jumper JP2 "AUTO FAN" ​ ^ Fan Speed  ^ ^ Jumper JP2 "AUTO FAN" ​ ^ Fan Speed  ^
 | Set                    | Automatic ​ | | Set                    | Automatic ​ |
 | Not set                | Full       | | Not set                | Full       |
  
-==== 10.4 Coin battery ​====+---- 
 +=== 12.4Coin battery ===
 A Seiko TS621E lithium rechargeable battery provides power to the MPSoC Battery Power Domain (BPD) through the VCC_PSBATT pin. It is connected in parallel with a 100 uF capacitor. The BPD includes the real-time clock with a dedicated crystal oscillator and a RAM available for storing a secure configuration key. The capacitor alone can provide power for approx. 15 minutes after main power is turned off. The battery will provide power after that. A Seiko TS621E lithium rechargeable battery provides power to the MPSoC Battery Power Domain (BPD) through the VCC_PSBATT pin. It is connected in parallel with a 100 uF capacitor. The BPD includes the real-time clock with a dedicated crystal oscillator and a RAM available for storing a secure configuration key. The capacitor alone can provide power for approx. 15 minutes after main power is turned off. The battery will provide power after that.
  
Line 624: Line 936:
 The battery is removable and can be replaced only by a 1.5 V, 6.8 mm rechargeable lithium coin battery. Do not use non-rechargeable batteries! The battery is removable and can be replaced only by a 1.5 V, 6.8 mm rechargeable lithium coin battery. Do not use non-rechargeable batteries!
  
-However, those prepared to void their warranty can physically remove the charging circuit by de-soldering D13 or R400. In this case any battery that meets MPSoC voltage specs can be used.+However, those prepared to void their warranty can physically remove the charging circuit by de-soldering D13 or R400. In this case any battery, even a non-rechargeable one, that meets MPSoC voltage specs can be used. 
 + 
 +---- 
 +===== Hardware Errata ===== 
 +Although we strive to provide perfect products, we are not infallible. The Genesys ZU is subject to the limitations below. 
 +^ Product Name  ^ Variant ​ ^ Revision ​ ^ S/N                                ^ Problem ​                                                                                                                                      ^ Status ​          ^ 
 +| Genesys ZU    | -3EG     | B         | DAD9C39-DAD9D32,​ DADA13A, DADA13B ​ | [[reference:​programmable-logic:​genesys-zu:​reference-manual#​fan_assembly_error|Fan assembly error resulting in sub-optimal mechanical hold.]] ​ | Fixed in rev C.  | 
 + 
 +=== 1. Fan Assembly Error === 
 +Due to an assembly error the heatsink clip of the MPSoC cooling fan has been mounted incorrectly,​ resulting in sub-optimal mechanical hold between the heatsink and the MPSoC package. On the affected production build the two slots on the yellow clip are facing right, where tall components prevent seating the clip. 
 + 
 +{{ :​reference:​programmable-logic:​genesys-zu:​5759d48d-d837-4f1b-97f1-89fd1533973f.jpg?​600 | Figure 1. Incorrect clip orientation prevents proper seating of the clip}} 
 +<​html><​center></​html>​ 
 +//Figure 1. Incorrect clip orientation prevents proper seating of the clip// 
 +<​html></​center></​html>​ 
 + 
 +For optimal mechanical hold the clip’s lip should reach underneath the MPSoC package substrate on both the left and right sides. Since the heatsink is secured by double-sided tape too, the sub-optimal mechanical hold of the clip is expected to cause issues only in time with excessive material aging of the tape under high temperature swings and/or mechanical vibration. 
 +The correct orientation of the yellow heatsink clip is with the two slots facing left. 
 + 
 +== Workaround == 
 +The fan and the yellow clip are user-removable. Disconnect all cables from the Genesys ZU before starting the operation. To remove the fan use a suitable Philips screwdriver to loosen the two screws fixing the fan to the heatsink. Put the fan aside for a moment. Use a narrow flathead screwdriver in one of the clip slots to carefully disengage the lips of the clip from underneath the MPSoC package. The lips are fragile and without due care they can break off easily. Once the lip on both sides of the clip is above the MPSoC package, the clip can be removed. Rotate the clip 180 degrees so that the slots are on the left and re-install it on the MPSoC package. Hook the lip of the clip under the MPSoC package on one side first and press down the other side to fasten the clip. 
 +A step-by-step description of the clip (dis)assembly is described here: http://​www.malico.com.tw/​index.php?​option=com_content&​view=article&​id=451&​Itemid=406&​lang=en. After the yellow clip is in place, the fan can be screwed back in the same place as before. 
 +