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reference:programmable-logic:genesys-zu:reference-manual [2019/12/04 15:17]
Bogdan [10.2 Platform MCU]
reference:programmable-logic:genesys-zu:reference-manual [2019/12/06 15:49] (current)
Elod Gyorgy
Line 7: Line 7:
 Available in two variants, 3EG and 5EV, differentiated by the MPSoC model and some peripherals. If the fan sticker says 5EV, on top of 3EG you get slightly faster DDR4, more FPGA, video codec and GTH transcievers allowing HDMI Source, Sink and SFP+ 10G. Available in two variants, 3EG and 5EV, differentiated by the MPSoC model and some peripherals. If the fan sticker says 5EV, on top of 3EG you get slightly faster DDR4, more FPGA, video codec and GTH transcievers allowing HDMI Source, Sink and SFP+ 10G.
  
-Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it straight up boots Linux from the microSD card. Connect the USB micro B cable to a PC and open a terminal (115200-8-N-1) to the first COM port out of the two that appear. Login and password both "​root"​. The red button labeled "​POR"​ always resets the MPSoC and starts the boot process again.+Used stand-alone with a hearty bundle in the box, powered by the 12V power supply, it straight up boots Linux from the microSD card. Connect the USB micro B cable to a PC and open a terminal (115200-8-N-1) to the first COM port out of the two that appear. Login and password both "​root"​. The red button labeled "​POR"​ always resets the MPSoC and starts the boot process again. ​
  
-Want to dive deep into development?​ Connecting the JTAG-HS1/​HS2 cable to header J28 will allow for on-the-fly programming and debug.+Want to dive deep into development? Head over to our [[https://​github.com/​Digilent|GitHub page]] and use the repos there as a starting point. Build your own boot image on the SD card and boot it like the OOB demo. Not enough? Connecting the JTAG-HS1/​HS2 cable to header J28 will allow for on-the-fly programming and debug using Xilinx Vivado and SDK.
 </​WRAP>​ </​WRAP>​
 <WRAP left> <WRAP left>
Line 24: Line 24:
 }} }}
  
-====== Features ​======+---- 
 +===== Features =====
 ^ Feature group            ^ Sub-feature ​                          ^ <color #​ed1c24>​Genesys ZU -3EG</​color> ​ ^ <color #​ed1c24>​Genesys ZU -5EV</​color> ​ ^ Zedboard ​                          ^ ^ Feature group            ^ Sub-feature ​                          ^ <color #​ed1c24>​Genesys ZU -3EG</​color> ​ ^ <color #​ed1c24>​Genesys ZU -5EV</​color> ​ ^ Zedboard ​                          ^
 | Processor ​               | APU                                   ​| ​ Quad A53                                                                        ||  Dual A9                           | | Processor ​               | APU                                   ​| ​ Quad A53                                                                        ||  Dual A9                           |
Line 55: Line 56:
 {{ :​reference:​programmable-logic:​genesys-zu:​genesys-zu-3eg-callout.png?​nolink |}} {{ :​reference:​programmable-logic:​genesys-zu:​genesys-zu-3eg-callout.png?​nolink |}}
 Figure Genesys ZU-3EG callout diagram. Figure Genesys ZU-3EG callout diagram.
 +--> Callout with Description ​ #
 +^ Callout #  ^ Description ​                  ^ Callout #  ^ Description ​                    ^ Callout #  ^ Description ​                          ^
 +| 1          | 6-pin PCIe power connector ​   | 13         | Coin battery retainer ​          | 25         | Type-C USB 3.1                        |
 +| 2          | External JTAG port            | 14         | Pmod headers ​                   | 26         | Power switch ​                         |
 +| 3          | USB JTAG/UART port            | 15         | Dual digital/​analog Pmod        | 27         | Zynq Ultrascale+,​ heat sink, and fan  |
 +| 4          | USB 2.0 host connectors ​      | 16         | User buttons ​                   | 28         | System Monitor header ​                |
 +| 5          | Wi-Fi chip                    | 17         | User switches ​                  | 29         | SIM card slot (on the bottom side)    |
 +| 6          | 4 GiB DDR4 SODIMM module ​     | 18         | Mini PCIe/mSATA slot            |            |                                       |
 +| 7          | Audio jacks                   | 19         | User buttons ​                   |            |                                       |
 +| 8          | Boot mode select jumper ​      | 20         | MIPI (Pcam) connectors ​         |            |                                       |
 +| 9          | Reset buttons ​                | 21         | Wireless and SSD activity LEDs  |            |                                       |
 +| 10         | INIT, DONE, ERR and STS Leds  | 22         | MicroSD Card Slot               ​| ​           |                                       |
 +| 11         | Zmod (SYZYGY) connector ​      | 23         | Mini DisplayPort ​               |            |                                       |
 +| 12         | FMC LPC connector ​            | 24         | 1G Ethernet port                |            |                                       |
  
-^ Callout #  ^ Description ​ ^ Callout #  ^ Description ​ ^ Callout #  ^ Description ​ ^ +<--
-| 1          | FIXME        | 7          |              | 13         ​| ​             | +
-| 2          |              | 8          |              | 14         ​| ​             | +
-| 3          |              | 9          |              | 15         ​| ​             | +
-| 4          |              | 10         ​| ​             | 16         ​| ​             | +
-| 5          |              | 11         ​| ​             | 17         ​| ​             | +
-| 6          |              | 12         ​| ​             | 18         ​| ​             | +
-====== Zynq UltraScale+ MPSoC Architecture ====== +
-<WRAP center round todo 60%> +
-Description from Xilinx +
-</​WRAP>​+
  
-====== Functional Description ======+---- 
 +===== Zynq UltraScale+ MPSoC Architecture ​===== 
 +Zynq UltraScale+ MPSoC is the Xilinx second-generation Zynq platform, combining a powerful processing system (PS) and user-programmable logic (PL) into the same device. The Zynq UltraScale+ Processing System core acts as a logic connection between the PS and the Programmable Logic (PL) while assisting you to integrate customized and integrated IP cores with the processing system using the Vivado IP integrator. As you may see in the picture bellow, the processing system features the Arm flagship Cortex -A53 64-bit quad-core running up to 1.5GHz and Cortex-R5 dual-core real-time processor along with other interfaces such as: DDR Memory Controller, High-Connectivity,​ General Connectivity,​ System Functions etc.  
 +The Zynq UltraScale+ MPSoC Processing System wrapper instantiates the processing system section of the Zynq UltraScale+ MPSoC for the programmable logic and external board logic. The wrapper includes unaltered connectivity with the ones presented above.  ​
  
-===== 1 Power Supplies =====+{{ :​reference:​programmable-logic:​genesys-zu:​3eg_ps_pl.png?​600 |}} 
 +//Figure ?. Zynq UltraScale+ EG//
  
-==== 1.1 Power Input ====+The PS and PL can be coupled with multiple interfaces and other signals to effectively integrate user-created hardware accelerators and other functions in the PL logic that are accessible to the processors. The interfaces between the processing system and programmable 
 +logic mainly consist of three main groups: the extended multiplexed I/O (EMIO), programmable logic I/O, and the AXI I/O groups. Besides those, there are up to 78 Multiplexed I/O (MIO) ports available from the processing system. The 78 MIO signals are divided into three banks, and each bank includes 26 device pins. Each bank (500, 501, and 502) has its own power pins for the hardware interface. 
 + 
 + 
 +--> MIO 0-25 : Bank 500 # 
 + 
 +| **MIO 500 3.3 V** |  **Peripherals** ​ |||||||||| 
 +| Pin           | QSPI | Mini PCIe / SATA | DDR4 SODIMM | MIO Buttons ​ | WI-FI | UART     | MIO LED | I2C MUX | USB 3.0 | 8-bit I/O Expander | 
 +| 0             | QSPI_SCLK0OUT |                  |             ​| ​             |                  |          |      |                    | 
 +| 1             | QSPI_D1 ​      ​| ​                 |             ​| ​             |                  |          |      |                    | 
 +| 2             | QSPI_D2 ​      ​| ​                 |             ​| ​             |                  |          |      |                    | 
 +| 3             | QSPI_D3 ​      ​| ​                 |             ​| ​             |                  |          |         ​| ​                   | 
 +| 4             | QSPI_D0 ​      ​| ​                 |             ​| ​             |                  |          |         ​| ​                   | 
 +| 5             | QSPI_SS_OUTN ​ |                  |             ​| ​             |                  |          |         ​| ​                   | 
 +| 6(N/​C) ​       |               ​| ​                 |             ​| ​             |                  |             ​| ​        ​| ​                   |  
 +| 7             ​| ​              | PCIE_PERSTN ​     |             ​| ​             |                  |             ​| ​        ​| ​                   | 
 +| 8             ​| ​              ​| ​                 | DDR_SCL ​    ​| ​             |                  |             ​| ​        ​| ​                   | 
 +| 9             ​| ​              ​| ​                 | DDR_SDA ​    ​| ​             |                  |             ​| ​        ​| ​                   | 
 +| 10            |               ​| ​                 |             | BTN1         ​| ​                 |             ​| ​        ​| ​                   | 
 +| 11            |               ​| ​                 |             | BTN0         ​| ​                 |             ​| ​        ​| ​                   | 
 +| 12            |               ​| ​                 |             ​| ​             | WIFI_PORTEX_SCK ​ |             ​| ​   | |  | WIFI_PORTEX_SCK ​   | 
 +| 13            |               ​| ​                 |             ​| ​             |                  |             ​| ​   | |  | PORTEXP_RESETN ​    | 
 +| 14            |               ​| ​                 |             ​| ​             |                  |             ​| ​   | |  | PORTEX_SSN ​        | 
 +| 15            |               ​| ​                 |             ​| ​             | WIFI_SSN ​        ​| ​            ​| ​        ​| ​                   | 
 +| 16            |               ​| ​                 |             ​| ​             | WIFI_PORTEX_MISO |             ​| ​   | |  |  WIFI_PORTEX_MISO ​ | 
 +| 17            |               ​| ​                 |             ​| ​             | WIFI_PORTEX_MOSI |             ​| ​   | |  |  WIFI_PORTEX_MOSI ​ | 
 +| 18            |               ​| ​                 |             ​| ​             |                  | UART_TXD_IN |         | | 
 +| 19            |               ​| ​                 |             ​| ​             |                  | UART_RXD_OUT| ​        | | 
 +| 20            |               | PCIE_WAKEN ​      ​| ​            ​| ​             |                  |             ​| ​        | | 
 +| 21            |               ​| ​                 |             ​| ​             |                  |             | LD0     | | 
 +| 22            |               ​| ​                 |             ​| ​             |                  |             ​| ​        | MUX_SCL_LS| 
 +| 23            |               ​| ​                 |             ​| ​             |                  |             ​| ​        | MUX_SDA_LS| 
 +| 24            |               ​| ​                 |             ​| ​             |                  |             ​| ​        | | USB30_INTN | 
 +| 25            |               ​| ​                 |             ​| ​             |                  |             ​| ​   | |  | PORTEXP_INTN | 
 + 
 +**Note:** The WI-FI signals are shared by the same bus that goes trough the I/O expander. 
 +<-- 
 + 
 +--> MIO 26-51 : Bank 501 # 
 + 
 +|  **MIO 501 1.8V** ​ |  **Peripherals** ​ || 
 +| Pin                | Ethernet ​      | SD              | 
 +| 26                 | ETH_TX_CLK ​    ​| ​                ​| ​  
 +| 27                 | ETH_TX_D0 ​     |                 ​| ​   
 +| 28                 | ETH_TX_D1 ​     |                 ​| ​        
 +| 29                 | ETH_TX_D2 ​     |                 ​| ​       
 +| 30                 | ETH_TX_D3 ​     |                 ​| ​       
 +| 31                 | ETH_TX_CTL ​    ​| ​                ​| ​       
 +| 32                 | ETH_RX_CLK ​    ​| ​                ​| ​       
 +| 33                 | ETH_RX_D0 ​     |                 ​| ​       
 +| 34                 | ETH_RX_D1 ​     |                 ​| ​      
 +| 35                 | ETH_RX_D2 ​     |                 ​| ​   
 +| 36                 | ETH_RX_D3 ​     |                 ​| ​        
 +| 37                 | ETH_RX_CTL ​    ​| ​                ​| ​       
 +| 38                 | ETH_INTN_PWDNN |                 ​| ​      
 +| 39                 ​| ​               | SDIO_SEL ​       |      
 +| 40                 ​| ​               | SDIO_DIR_CMD ​   |      
 +| 41                 ​| ​               | SDIO_DIR_DAT0 ​  ​| ​       
 +| 42                 ​| ​               | SDIO_DIR_DAT1_3 |    
 +| 43                 ​| ​               | SDIO_POW_EN ​    ​| ​          
 +| 44                 ​|ETH_RSTN ​       |                 ​| ​          
 +| 45                 ​| ​               | SDIO_CDN ​       |         
 +| 46                 ​| ​               | SDIO_R_DAT0 ​    ​| ​        
 +| 47                 ​| ​               | SDIO_R_DAT1 ​    ​| ​         
 +| 48                 ​| ​               | SDIO_R_DAT2 ​    ​| ​        
 +| 49                 ​| ​               | SDIO_R_DAT3 ​    ​| ​        
 +| 50                 ​| ​               | SDIO_R_CMD ​     |                  
 +| 51                 ​| ​               | SDIO_R_SCLK ​    |  
 + 
 +<-- 
 + 
 +--> MIO 52-77 : Bank 502 # 
 + 
 +|  **MIO 502 1.8V** ​ |  **Peripherals** ​          || 
 +| Pin                | USB 2.0        | Ethernet ​               | 
 +| 52                 | USB20_CLK ​     |                         ​| ​   
 +| 53                 | USB20_DIR ​     |                         ​| ​     
 +| 54                 | USB20_DATA2 ​   |                         ​| ​       
 +| 55                 | USB20_NXT ​     |                         ​| ​      
 +| 56                 | USB20_DATA0 ​   |                         ​| ​       
 +| 57                 | USB20_DATA1 ​   |                         ​| ​     
 +| 58                 | USB20_STP ​     |                         ​| ​  
 +| 59                 | USB20_DATA3 ​   |                         ​| ​      
 +| 60                 | USB20_DATA4 ​   |                         ​| ​     
 +| 61                 | USB20_DATA5 ​   |                         ​| ​     
 +| 62                 | USB20_DATA6 ​   |                         ​| ​      
 +| 63                 | USB20_DATA7 ​   |                         ​| ​      
 +| 64                 | USB20H_CLK ​    ​| ​         |     
 +| 65                 | USB20H_DIR ​    ​| ​         |      
 +| 66                 | USB20H_DATA2 ​  ​| ​         |     
 +| 67                 | USB20H_NXT ​    ​| ​         |      
 +| 68                 | USB20H_DATA0 ​  ​| ​         |     
 +| 69                 | USB20H_DATA1 ​  ​| ​         |        
 +| 70                 | USB20H_STP ​    ​| ​         |    
 +| 71                 | USB20H_DATA3 ​  ​| ​         |         
 +| 72                 | USB20H_DATA4 ​  ​| ​         |         
 +| 73                 | USB20H_DATA5 ​  ​| ​         |        
 +| 74                 | USB20H_DATA6 ​  ​| ​         |        
 +| 75                 | USB20H_DATA7 ​  ​| ​         |      
 +| 76                 ​| ​               | ETH_MDC ​ |  
 +| 77                 ​| ​               | ETH_MDIO |  
 + 
 +<-- 
 + 
 +---- 
 +===== Functional Description ===== 
 + 
 +==== 1. Power Supplies ==== 
 + 
 +=== 1.1 Power Input ===
  
 The Genesys ZU power distribution network was designed to meet the specific requirements of Xilinx Zynq UltraScale+ MPSoCs and of the supported peripheral devices. Power to the board is provided via a 2x3 PCIe ATX power connector. Xilinx evaluation boards use a pinout that is not compatible with ATX, therefore mixing power supplies is not possible. The bundled supply is 12V 60W-100W, depending on variant. The Genesys ZU power distribution network was designed to meet the specific requirements of Xilinx Zynq UltraScale+ MPSoCs and of the supported peripheral devices. Power to the board is provided via a 2x3 PCIe ATX power connector. Xilinx evaluation boards use a pinout that is not compatible with ATX, therefore mixing power supplies is not possible. The bundled supply is 12V 60W-100W, depending on variant.
 The board power supplies are turned on or off with the SW5 slide switch. The board power supplies are turned on or off with the SW5 slide switch.
  
-==== 1.2 Power Specifications ​====+---- 
 +=== 1.2 Power Specifications ===
  
 Figure 1.1 gives an overview of the Genesys ZU power distribution network. ​ Figure 1.1 gives an overview of the Genesys ZU power distribution network. ​
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 | VREF0V6 ​                         | VCC1V2_PSDDR ​       | 0.6V (0.49xVCC1V2_PSDDR... ...0.51xVCC1V2_PSDDR) ​             | 0.01A            | DDR4 reference voltage ​                                                                                                                                               | | VREF0V6 ​                         | VCC1V2_PSDDR ​       | 0.6V (0.49xVCC1V2_PSDDR... ...0.51xVCC1V2_PSDDR) ​             | 0.01A            | DDR4 reference voltage ​                                                                                                                                               |
  
-==== 1.3 Power Sequencing ​====+---- 
 +=== 1.3 Power Sequencing ===
 The board is powered up by sliding the SW5 switch to the ON position. The voltage supplies start-up sequence is defined by implementing a power good daisy chain that selectively enables groups of voltages that should start together. All supplies use a soft start mechanism to reduce the surge currents during turn on. The start-up sequence is suggested in Figure 1.1 and can be described in the following steps: The board is powered up by sliding the SW5 switch to the ON position. The voltage supplies start-up sequence is defined by implementing a power good daisy chain that selectively enables groups of voltages that should start together. All supplies use a soft start mechanism to reduce the surge currents during turn on. The start-up sequence is suggested in Figure 1.1 and can be described in the following steps:
  
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 Sliding the SW5 switch to the OFF position disables the power supplies by pulling //​INPUT_PGD//​ to ground. The capacitor C405 connected to the //EN// terminal of the LM5060 monitoring IC delays the VCC12V0 turn off with approximately 200ms until all power supplies have been safely powered off.  Sliding the SW5 switch to the OFF position disables the power supplies by pulling //​INPUT_PGD//​ to ground. The capacitor C405 connected to the //EN// terminal of the LM5060 monitoring IC delays the VCC12V0 turn off with approximately 200ms until all power supplies have been safely powered off. 
  
- +---- 
-===== 2 MPSoC Boot Process ​=====+==== 2MPSoC Boot Process ====
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 Short overview of boot process, link to Xilinx for the rest. List boot modes available on the Genesys ZU. Describe the 4 status LEDs Short overview of boot process, link to Xilinx for the rest. List boot modes available on the Genesys ZU. Describe the 4 status LEDs
 </​WRAP>​ </​WRAP>​
  
-==== 2.1 JTAG Boot Mode ==== +=== 2.1 JTAG Boot Mode === 
-==== 2.2 microSD Boot Mode ==== + 
-==== 2.3 Quad SPI Boot Mode ==== +---- 
-==== 2.4 USB Boot Mode ====+=== 2.2 microSD Boot Mode === 
 + 
 +---- 
 +=== 2.3 Quad SPI Boot Mode === 
 + 
 +---- 
 +=== 2.4 USB Boot Mode ===
 It is the only boot mode apart from JTAG where the MPSoC takes a slave role. It shows up as a DFU (Device Firmware Upgrade) USB device to the PC, waiting for a configuration. It is the only boot mode apart from JTAG where the MPSoC takes a slave role. It shows up as a DFU (Device Firmware Upgrade) USB device to the PC, waiting for a configuration.
  
-===== 3 Main Memory ​=====+---- 
 +==== 3Main Memory ====
 Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the PS (Processing System) side using the hard-core memory controller. ​ Main memory is a single-slot populated DDR4 SODIMM, always upgradeable by the user. It is wired to the PS (Processing System) side using the hard-core memory controller. ​
 The bundled module is a 4GiB Kingston HyperX HX424S14IB/​4. Although the module supports DDR4-2400 CL14-14-14 timing, data rate is limited by the MPSoC and the board. The 5EV board variant supports <wrap hi>​DDR4-2133*</​wrap>,​ while the 3EG supports DDR4-1866. The bundled module is a 4GiB Kingston HyperX HX424S14IB/​4. Although the module supports DDR4-2400 CL14-14-14 timing, data rate is limited by the MPSoC and the board. The 5EV board variant supports <wrap hi>​DDR4-2133*</​wrap>,​ while the 3EG supports DDR4-1866.
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 Although the bundled module is not ECC-capable,​ the Genesys ZU is. Just pair it with an ECC module and enable the feature in the Vivado MPSoC PS Configuration Wizard. Although the bundled module is not ECC-capable,​ the Genesys ZU is. Just pair it with an ECC module and enable the feature in the Vivado MPSoC PS Configuration Wizard.
  
-==== 3.1 Implementation ​====+=== 3.1 Implementation ===
 There is a single SODIMM slot on the top side of the Genesys ZU just north of the MPSoC. It is wired to the PS-side memory controller and supports any SODIMM module complying with the memory controller'​s restrictions. These are detailed in the Zynq UltraScale+ Device TRM (UG1085), but common modules of 1R/2R, x8/x16, 64b/72b are supported. There is a single SODIMM slot on the top side of the Genesys ZU just north of the MPSoC. It is wired to the PS-side memory controller and supports any SODIMM module complying with the memory controller'​s restrictions. These are detailed in the Zynq UltraScale+ Device TRM (UG1085), but common modules of 1R/2R, x8/x16, 64b/72b are supported.
  
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 It should be enabled in systems that expect a high amount of signal integrity issues and where high reliability is desired. It trades data bandwidth for reliability. CRC support is optional in SODIMM modules. Even if the module supports it, implementation is not easy. For CRC to work the controller must know what pin swaps were performed on the memory interface. In case of SODIMM modules, there are some restricted pin swaps possible and must be documented in the SPD EEPROM. The controller is expected to read these, combine it with pin swaps on the system board and assign the bits to CRC inputs accordingly. According to AR# 68788 this can be achieved through the DDRC.DQMAP registers, not well documented. It should be enabled in systems that expect a high amount of signal integrity issues and where high reliability is desired. It trades data bandwidth for reliability. CRC support is optional in SODIMM modules. Even if the module supports it, implementation is not easy. For CRC to work the controller must know what pin swaps were performed on the memory interface. In case of SODIMM modules, there are some restricted pin swaps possible and must be documented in the SPD EEPROM. The controller is expected to read these, combine it with pin swaps on the system board and assign the bits to CRC inputs accordingly. According to AR# 68788 this can be achieved through the DDRC.DQMAP registers, not well documented.
-===== 4 Storage ===== 
  
-==== 4.1 Quad-SPI Flash ==== +---- 
-<WRAP center round todo 60%> +==== 4. Storage ​====
-SFP+ MAC address location, qspi connection figure +
-</​WRAP>​+
  
 +=== 4.1 Quad-SPI Flash ===
 The Genesys ZU features a serial flash memory from ISSI. This memory is used to The Genesys ZU features a serial flash memory from ISSI. This memory is used to
 provide non-volatile code and data storage. It can be used to initialize the provide non-volatile code and data storage. It can be used to initialize the
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 The Flash is also commonly used to store non-configuration data needed by the The Flash is also commonly used to store non-configuration data needed by the
-application. If doing this from a bare-metal applicationThe flash memory can+application. If doing this from a bare-metal applicationThe flash memory can
 be freely accessed using standalone libraries included with a Xilinx SDK BSP be freely accessed using standalone libraries included with a Xilinx SDK BSP
 project. If doing this from a Petalinux generated embedded Linux system, the project. If doing this from a Petalinux generated embedded Linux system, the
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 blocks. A block consists of 8/16 adjacent sectors. blocks. A block consists of 8/16 adjacent sectors.
  
-The memory is divided into uniform 4 KByte sectors or uniform 32/64 Kbyte +Two globally unique MAC address are programmed in the last sector, sector 8191.
-blocks. A block consists of 8/16 adjacent sectors.+
   * MAC for Ethernet PHY is stored at address 0x1FFF000   * MAC for Ethernet PHY is stored at address 0x1FFF000
-  * MAC for SFP+ (5EV only) is stored at address ​....+  * MAC for SFP+ (5EV only) is stored at address ​0x1FFF006
  
 The last sector, used to store the MAC addresses, is protected from write and The last sector, used to store the MAC addresses, is protected from write and
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 factory. If TBPARM is programmed to 0, an attempt to change it back to 1 will factory. If TBPARM is programmed to 0, an attempt to change it back to 1 will
 fail and ignore the program operation. For more details about the Advanced fail and ignore the program operation. For more details about the Advanced
-Sector/​Block Protection mechanism consult the manufacturer'​s datasheet.+Sector/​Block Protection mechanism consult the manufacturer'​s ​[[http://​www.issi.com/​WW/​pdf/​IS25LP(WP)256D.pdf|datasheet]].
  
 To protect the MAC addresses from the last sector, Genesys ZU comes with TBPARM To protect the MAC addresses from the last sector, Genesys ZU comes with TBPARM
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-==== 4.2 microSD slot ====+//Figure 4.1.1 Genesys ZU Quad SPI Flash// 
 + 
 +---- 
 +=== 4.2 microSD slot ===
 The microSD connector J9 located on the top side has a hinge-based mechanism. It is compatible with UHS-I allowing 1.8V signalling and speeds up to SDR104, or 104MB/s. The microSD connector J9 located on the top side has a hinge-based mechanism. It is compatible with UHS-I allowing 1.8V signalling and speeds up to SDR104, or 104MB/s.
  
-==== 4.3 mSATA slot ====+---- 
 +=== 4.3 mSATA slot ===
 The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile SSD storage. Both half and full-size modules are supported. Since PCIe and SATA share the same GTR lanes, one has to disable PCIe first to enable SATA. The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile SSD storage. Both half and full-size modules are supported. Since PCIe and SATA share the same GTR lanes, one has to disable PCIe first to enable SATA.
  
- +---- 
-===== 5 Network Connectivity ​===== +==== 5. Network Connectivity ==== 
-==== 5.1 Wi-Fi ====+=== 5.1 Wi-Fi ===
 A Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the MPSoC on the PS-side over SPI, supporting a maximum theoretical bandwidth of 48Mbps. The ATWINC1500 can be used in bare-metal applications with the full IP stack included in the firmware loaded from flash. However, it is also supported in Linux in the ATWILC1000-compatible mode, where the firmware is loaded on-the-fly upon boot and the OS IP stack is used. A Microchip ATWINC1500 module provides 2.4GHz IEEE 802.11 b/g/n wireless network connectivity. It interfaces to the MPSoC on the PS-side over SPI, supporting a maximum theoretical bandwidth of 48Mbps. The ATWINC1500 can be used in bare-metal applications with the full IP stack included in the firmware loaded from flash. However, it is also supported in Linux in the ATWILC1000-compatible mode, where the firmware is loaded on-the-fly upon boot and the OS IP stack is used.
  
-==== 5.2 1G Ethernet ​====+---- 
 +=== 5.2 1G Ethernet ===
 The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the MPSoC via RGMII for data and MDIO for management. The auxiliary interrupt (ETH_INTN_PWDNN) and reset (ETH_RSTN) signals also connect to MIO Bank 501. The Genesys ZU uses a TI DP83867CR PHY to implement a 10/100/1000 Ethernet port for wired connectivity. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the MPSoC via RGMII for data and MDIO for management. The auxiliary interrupt (ETH_INTN_PWDNN) and reset (ETH_RSTN) signals also connect to MIO Bank 501.
  
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  The identifier is also printed on a sticker found on next to the Ethernet jack.   The identifier is also printed on a sticker found on next to the Ethernet jack. 
  
-==== 5.2 10G SFP+ ====+---- 
 +=== 5.2 10G SFP+ ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 Todo for 5EV. Todo for 5EV.
 </​WRAP>​ </​WRAP>​
  
-==== 5.3 WLAN, Bluetooth, WWAN ====+---- 
 +=== 5.3 WLAN, Bluetooth, WWAN ===
 The Mini PCIe socket allows you to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1 and USB 2.0 available in the socket, even dual Wi-Fi/​Bluetooth modules can be used. The primary use case is Linux OS, so modules with Linux drivers available in-kernel are recommended. For WWAN radio modules a SIM slot is present on the bottom side of the board. The Mini PCIe socket allows you to connect any wireless radio module compatible with the PCIe Mini Card standard. With both PCIe x1 and USB 2.0 available in the socket, even dual Wi-Fi/​Bluetooth modules can be used. The primary use case is Linux OS, so modules with Linux drivers available in-kernel are recommended. For WWAN radio modules a SIM slot is present on the bottom side of the board.
-===== 6 Peripheral Connectivity ​===== + 
-==== 6.1 USB Full-Featured Type-C ​====+---- 
 +==== 6Peripheral Connectivity ==== 
 +=== 6.1 USB Full-Featured Type-C ===
 USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle J6. The connector has a USB 2.0 pair for backward compatibility,​ one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is established during the configuration process over the CC1 and CC2 pins. Depending on the orientation,​ either pins with suffix 1 or pins with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer. USB 3.1 Gen1 and USB 2.0 support is handled by the Full-Featured Type-C receptacle J6. The connector has a USB 2.0 pair for backward compatibility,​ one high-speed transceiver lane (two pairs) for USB 3.1, and configuration channel (CC). Since the plug is reversible, the upper and lower rows double the number of pins for each function, designated by suffixes 1 and 2. Plug orientation is established during the configuration process over the CC1 and CC2 pins. Depending on the orientation,​ either pins with suffix 1 or pins with suffix 2 carry actual signals. Multiplexing 1 and 2 for the USB 3.1 lane is done by an on-board hardware multiplexer.
  
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 In the box you can find a USB Type-C Legacy Adapter reference as CAR3G1-3 in the Type-C specifications. It has a Full-Features Type-C plug on one end and a USB 3.1 Standard-A receptacle on the other. Use it to connect non-Type-C USB 2.0 or USB 3.1 devices to the Genesys ZU. In the box you can find a USB Type-C Legacy Adapter reference as CAR3G1-3 in the Type-C specifications. It has a Full-Features Type-C plug on one end and a USB 3.1 Standard-A receptacle on the other. Use it to connect non-Type-C USB 2.0 or USB 3.1 devices to the Genesys ZU.
-==== 6.2 USB 2.0 Host ====+ 
 +---- 
 +=== 6.2 USB 2.0 Host ===
 Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to the PS-side controller of MPSoC over ULPI. Host-only USB 2.0 functionality is implemented by a Microchip USB3320 PHY and a Microchip USB2513B hub. The PHY is wired to the PS-side controller of MPSoC over ULPI.
 The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port. This allows interfacing Bluetooth modules, for example. The hub has three Downstream-Facing Ports. Two of these connect to a dual-stacked Type-A connector, providing 0.5A current per port. The third port is connected to the MiniPCIe slot, an embedded USB port. This allows interfacing Bluetooth modules, for example.
  
-==== 6.3 USB 2.0 - JTAG/Serial Bridge ​====+---- 
 +=== 6.3 USB 2.0 - JTAG/Serial Bridge ===
 The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration,​ but the first one will always connect to the MPSoC and the second one to the Platform MCU. The micro Type-B connector J8 connects to an FTDI FT4232HQ USB bridge. It provides a JTAG interface for programming and debugging, one UART interface connected to the MPSoC and one UART interface connected to the Platform MCU. The UART interfaces are exposed as standard COM ports. Their exact designator is determined upon enumeration,​ but the first one will always connect to the MPSoC and the second one to the Platform MCU.
 The MPSoC UART interface is wired to the PS-side MIO Bank 500: UART_TXD_IN to MIO18 and UART_RXD_OUT to MIO19. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. The MPSoC UART interface is wired to the PS-side MIO Bank 500: UART_TXD_IN to MIO18 and UART_RXD_OUT to MIO19. Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC.
 The Digilent USB-JTAG function and the USB-UART functions behave independent of one another. Support for USB-JTAG in Vivado is expected in version 2020.1. The Digilent USB-JTAG function and the USB-UART functions behave independent of one another. Support for USB-JTAG in Vivado is expected in version 2020.1.
  
-===== 7.Multimedia ​===== +---- 
-==== 7.1 DisplayPort Source ​=====+==== 7. Multimedia ==== 
 +=== 7.1 DisplayPort Source ===
 The dual-lane mini DisplayPort connector J27 is wired to a PS-side DisplayPort Controller via two PS-GTR transceiver lanes. Resolutions up to 4Kx2K@30fps are supported at a maximum 5.4Gbps line rate.  The dual-lane mini DisplayPort connector J27 is wired to a PS-side DisplayPort Controller via two PS-GTR transceiver lanes. Resolutions up to 4Kx2K@30fps are supported at a maximum 5.4Gbps line rate. 
-==== 7.2 HDMI Source ​=====+ 
 +---- 
 +=== 7.2 HDMI Source ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 TODO for 5EV TODO for 5EV
 </​WRAP>​ </​WRAP>​
-==== 7.3 HDMI Sink =====+ 
 +---- 
 +=== 7.3 HDMI Sink ===
 <WRAP center round todo 60%> <WRAP center round todo 60%>
 TODO for 5EV TODO for 5EV
 </​WRAP>​ </​WRAP>​
-==== 7.4 Audio Codec =====+ 
 +---- 
 +=== 7.4 Audio Codec ===
 The Genesys ZU board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC39) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J20-green),​ headphone-out (J19-black),​ line-in (J22-blue), and microphone-in (J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono. The Genesys ZU board includes an Analog Devices ADAU1761 SigmaDSP audio codec (IC39) complementing its multimedia features. Four 1/8” (3.5mm) audio jacks are available for line-out (J20-green),​ headphone-out (J19-black),​ line-in (J22-blue), and microphone-in (J21-pink). Each jack carries two channels of analog audio (stereo), with the exception of the microphone input, which is mono.
  
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 All relevant information can be found in the [[http://​www.analog.com/​media/​en/​technical-documentation/​data-sheets/​ADAU1761.pdf|ADAU1761 datasheet]]. All relevant information can be found in the [[http://​www.analog.com/​media/​en/​technical-documentation/​data-sheets/​ADAU1761.pdf|ADAU1761 datasheet]].
  
-==== 7.5 MIPI/Pcam Ports =====+---- 
 +=== 7.5 MIPI/Pcam Ports ===
 The two MIPI/Pcam ports included on the Genesys ZU are a 15-pin, 1 mm pitch, zero insertion force (ZIF) connector designed specifically for attaching camera sensor modules to host systems. It builds on the Pcam connector standard introduced on the Digilent Zybo Z7, but allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture. Therefore, it supports MIPI DSI applications too, while remaining backward compatible with MIPI CSI-2 Pcam modules, like the Digilent Pcam 5C. The two MIPI/Pcam ports included on the Genesys ZU are a 15-pin, 1 mm pitch, zero insertion force (ZIF) connector designed specifically for attaching camera sensor modules to host systems. It builds on the Pcam connector standard introduced on the Digilent Zybo Z7, but allows for bi-directional D-PHY lanes thanks to direct I/O support in the UltraScale+ architecture. Therefore, it supports MIPI DSI applications too, while remaining backward compatible with MIPI CSI-2 Pcam modules, like the Digilent Pcam 5C.
  
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   - The FFC is now connected properly.   - The FFC is now connected properly.
  
-===== 8 Expansion Ports ===== +---- 
-==== 8.1 Mini PCIe / mSATA ====+==== 8Expansion Ports ==== 
 +=== 8.1 Mini PCIe / mSATA ===
 J13 socket implements a versatile expansion options for adding SSD, WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocateable stand-offs included with the board. Electrically,​ the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board USB hub and the MPSoC USB1 controller up the chain. J13 socket implements a versatile expansion options for adding SSD, WLAN, Bluetooth or WWAN modules to the Genesys ZU. It is compatible with PCI Express Mini card types F1/F2 (Full-Mini) and H1/H2 (Half-Mini) and mSATA card types Mini and Full size. Mechanical compatibility is assured by the relocateable stand-offs included with the board. Electrically,​ the SATA lane and the PCIe x1 lane share the same PS-GTR transceiver lane. Therefore, it is up to the MPSoC configuration to enable either the SATA or the PCIe Root controller and map it to the GTR lane. Mini PCIe modules can also make use of the embedded USB 2.0 port wired to the on-board USB hub and the MPSoC USB1 controller up the chain.
  
-==== 8.2 Low-Pin Count FMC Connector ​====+---- 
 +=== 8.2 Low-Pin Count FMC Connector ===
 The Genesys ZU includes a FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard. ​ Genesys ZU-based designs can now be easily extended with custom or off-the-shelf high-performance modules. The Genesys ZU includes a FPGA Mezzanine Card (FMC) Standard-conforming carrier card connector that enables connecting mezzanine modules compliant with the same standard. ​ Genesys ZU-based designs can now be easily extended with custom or off-the-shelf high-performance modules.
  
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 </​WRAP>​ </​WRAP>​
  
-==== 8.3 Zmod ====+---- 
 +=== 8.3 Zmod ===
 The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. The port is compatible with version 1.1 of the SYZYGY specification from Opal Kelly. The Zmod port uses the SYZYGY Standard interface to communicate with installed SYZYGY pods. The port is compatible with version 1.1 of the SYZYGY specification from Opal Kelly.
  
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 For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]]. For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]].
  
-=== 8.3.1 SYZYGY Pod Compatibility ​===+---- 
 +== 8.3.1 SYZYGY Pod Compatibility ==
  
 The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required to determine if the Genesys ZU is compatible with a certain pod is summarized in Table 8.1.1. The Genesys ZU Zmod port is compatible with a variety of different SYZYGY pods. Information required to determine if the Genesys ZU is compatible with a certain pod is summarized in Table 8.1.1.
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 ^ Length Matching ​           | 10 mm inter-pair, 1mm intra-pair | ^ Length Matching ​           | 10 mm inter-pair, 1mm intra-pair |
  
-=== 8.3.2 Mechanical ===+---- 
 +== 8.3.2 ==
  
 FIXME //Is there any information on this not encapsulated by the syzygy spec?// FIXME //Is there any information on this not encapsulated by the syzygy spec?//
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 </​WRAP>​ </​WRAP>​
  
- +---- 
-==== 8.4 Pmod ====+=== 8.4 Pmod ===
  
 Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure bellow. The VCC and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets of the onboard regulators or the external power supply. Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure bellow. The VCC and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets of the onboard regulators or the external power supply.
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 <-- <--
  
-==== 8.5 Dual Digital/​Analog Pmod ====+---- 
 +=== 8.5 Dual Digital/​Analog Pmod ===
 On the Genesys ZU, one of the Pmod connectors is not like the others. Designated by JA, the Pmod connector is wired to pins that can serve as auxiliary inputs to the system monitor ADC inside the MPSoC. These pins are in a VADJ-powered bank, so the VCC pins are not powered from the 3.3 V rail, like on regular Pmods, but from VADJ. VADJ on the Genesys ZU is in the 1.2 V - 1.8 V range. Pins 1-7, 2-8, 3-9, 4-10 are paired and routed differentially. On the Genesys ZU, one of the Pmod connectors is not like the others. Designated by JA, the Pmod connector is wired to pins that can serve as auxiliary inputs to the system monitor ADC inside the MPSoC. These pins are in a VADJ-powered bank, so the VCC pins are not powered from the 3.3 V rail, like on regular Pmods, but from VADJ. VADJ on the Genesys ZU is in the 1.2 V - 1.8 V range. Pins 1-7, 2-8, 3-9, 4-10 are paired and routed differentially.
 Although these pins can be used in digital mode, the particularities of this connector must be taken into account when connecting Pmod modules to it. Although these pins can be used in digital mode, the particularities of this connector must be taken into account when connecting Pmod modules to it.
-===== 9 Basic I/O =====+ 
 +---- 
 +==== 9Basic I/O ====
 The Genesys ZU includes five push-buttons,​ four switches and one tri-color LED connected to the Zynq PL, as shown in Figure bellow. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output). The Genesys ZU includes five push-buttons,​ four switches and one tri-color LED connected to the Zynq PL, as shown in Figure bellow. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output).
  
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 The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed.
  
 +----
 === 9.2 Tri-Color LED === === 9.2 Tri-Color LED ===
  
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 ---- ----
-===== 10 Platform Management ​=====+==== 10Platform Management ====
 Tying all the features of the Genesys ZU together into a computing platform requires an embedded controller independent of the MPSoC. We call it Platform MCU. Part of the platform is the coin battery, the fan, a temperature sensor inside the MPSoC and Power Management Units (PMU). Management is done through dedicated signals or over the main I<​sup>​2</​sup>​C bus. Tying all the features of the Genesys ZU together into a computing platform requires an embedded controller independent of the MPSoC. We call it Platform MCU. Part of the platform is the coin battery, the fan, a temperature sensor inside the MPSoC and Power Management Units (PMU). Management is done through dedicated signals or over the main I<​sup>​2</​sup>​C bus.
-==== 10.1 Main I2C bus ====+=== 10.1 Main I2C bus ===
 Almost all I<​sup>​2</​sup>​C-capable peripherals are accessible through the main I<​sup>​2</​sup>​C bus. Multiple masters have access: Almost all I<​sup>​2</​sup>​C-capable peripherals are accessible through the main I<​sup>​2</​sup>​C bus. Multiple masters have access:
   * Platform MCU in the Auxiliary 3.3 V domain through MUX_SCL and MUX_SDA,   * Platform MCU in the Auxiliary 3.3 V domain through MUX_SCL and MUX_SDA,
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 Figure Genesys ZU I<​sup>​2</​sup>​C topology. Figure Genesys ZU I<​sup>​2</​sup>​C topology.
  
- +---- 
- +=== 10.2 Platform MCU ===
-==== 10.2 Platform MCU ====+
 The Platform MCU is implemented by a Microchip ATmega328PB. It is on the auxiliary 3.3V power domain, immediately available after power-up. This power domain is independent of the PMUs providing main power, giving the Platform MCU control over main power. It also shares the main I<​sup>​2</​sup>​C bus with the MPSoC, giving it access to all the critical peripherals. Other features include MPSoC temperature sensing, fan speed control, and VADJ voltage setting. The Platform MCU is implemented by a Microchip ATmega328PB. It is on the auxiliary 3.3V power domain, immediately available after power-up. This power domain is independent of the PMUs providing main power, giving the Platform MCU control over main power. It also shares the main I<​sup>​2</​sup>​C bus with the MPSoC, giving it access to all the critical peripherals. Other features include MPSoC temperature sensing, fan speed control, and VADJ voltage setting.
-<WRAP center round todo 60%> 
-Detail features, error codes, bootloader etc. 
-</​WRAP>​ 
  
 The Platform MCU program memory has two sections: The Platform MCU program memory has two sections:
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   * Bootloader where the bootloader resides.   * Bootloader where the bootloader resides.
  
-=== 10.2.1 Application Section ​===+== 10.2.1 Application Section ==
  
 The Platform MCU has the following interfaces on Genesys ZU: The Platform MCU has the following interfaces on Genesys ZU:
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 VADJ voltage value based on VADJ_LEVEL1 (AC13) and VADJ_LEVEL0 (AC14) input pins, VADJ voltage value based on VADJ_LEVEL1 (AC13) and VADJ_LEVEL0 (AC14) input pins,
 regardless of whether a syzygy pod and/or FMC mezzanine module is connected. regardless of whether a syzygy pod and/or FMC mezzanine module is connected.
-The following table presents the VADJ level encoding.+Table 10.2.1.1 ​presents the VADJ level encoding. 
 + 
 +//Table 10.2.1.1 VADJ levels encoding//
 ^ VADJ_LEVEL1 ​ ^ VADJ_LEVEL0 ​ ^ VADJ level      ^ ^ VADJ_LEVEL1 ​ ^ VADJ_LEVEL0 ​ ^ VADJ level      ^
 |  0           ​| ​ 0           ​| ​ VADJ disabled ​ | |  0           ​| ​ 0           ​| ​ VADJ disabled ​ |
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 actual VADJ_LEVEL1 and VADJ_LEVEL0 pins state. actual VADJ_LEVEL1 and VADJ_LEVEL0 pins state.
  
-<WRAP center round important ​60%>+To set the desired VADJ level you have to: 
 +  - Drive the VADJ_LEVEL1 and VADJ_LEVEL0 to encode the desired VADJ level. 
 +  - Generate a falling edge condition on VADJ_AUTO. 
 + 
 +<WRAP center round important ​90%>
 In the current implementation,​ the FPGA must detect the correct VADJ level required In the current implementation,​ the FPGA must detect the correct VADJ level required
 by SYZYGY and FMC modules and must set the VADJ_LEVEL1 and VADJ_LEVEL0 signals by SYZYGY and FMC modules and must set the VADJ_LEVEL1 and VADJ_LEVEL0 signals
 accordingly. The VADJ_LEVEL1 and VADJ_LEVEL0 signals will be taken into account by the  accordingly. The VADJ_LEVEL1 and VADJ_LEVEL0 signals will be taken into account by the 
-Platform MCU only if the VADJ_AUTO signal is driven LOW by the FPGA. If VADJ_AUTO is HIGH  +Platform MCU only if the VADJ_AUTO signal is driven LOW by the FPGA. If VADJ_AUTO is HIGH 
-the VADJ is disabled.+the VADJ power rail is disabled.
 </​WRAP>​ </​WRAP>​
  
 On Genesys ZU there is a LED labeled with PMCU. This is the status led that is On Genesys ZU there is a LED labeled with PMCU. This is the status led that is
 used by Platform MCU to display the system fault that has the highest priority. used by Platform MCU to display the system fault that has the highest priority.
-The blinking pattern for each fault is presented in the following table.+The blinking pattern for each fault is presented in Table 10.2.1.2.
  
 After Platform MCU startup, if no issues were encountered,​ this LED should blink After Platform MCU startup, if no issues were encountered,​ this LED should blink
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   * A “short blink” and a “short pause” last for about 200ms each;   * A “short blink” and a “short pause” last for about 200ms each;
  
 +//Table 10.2.1.2 Fault blink patterns//
 ^  Blink Pattern (Repeated) ​ ^  Issue            ^  Priority ​ ^  Comments ​            ^ ^  Blink Pattern (Repeated) ​ ^  Issue            ^  Priority ​ ^  Comments ​            ^
 |  Long Blink – Long Pause   ​| ​ Fan Speed Fault  |  0         ​| ​ Register 0x04 Bit 0  | |  Long Blink – Long Pause   ​| ​ Fan Speed Fault  |  0         ​| ​ Register 0x04 Bit 0  |
  
 The Platform MCU exposes to the PC a register interface, accessible via UART. The Platform MCU exposes to the PC a register interface, accessible via UART.
-The full register map is shown in the table below.+The full register map is shown in Table 10.2.1.3. 
 + 
 +//Table 10.2.1.3 Register map//
 ^  Offset ​    ​^ ​ Register Name                      ^  Size [bits] ​ ^  R/W  ^  Description ​                                                                                                                                                                                                                                                           ^ ^  Offset ​    ​^ ​ Register Name                      ^  Size [bits] ​ ^  R/W  ^  Description ​                                                                                                                                                                                                                                                           ^
 |  0x00       ​| ​ ID Register ​                       |  8            |  R    | It contains a fixed value, used for determining if the Platform MCU is alive and responding over UART e.g. 0x12345678. ​                                                                                                                                                 | |  0x00       ​| ​ ID Register ​                       |  8            |  R    | It contains a fixed value, used for determining if the Platform MCU is alive and responding over UART e.g. 0x12345678. ​                                                                                                                                                 |
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 When the PC wants to access a Platform MCU register, it needs to respect the following protocol: When the PC wants to access a Platform MCU register, it needs to respect the following protocol:
-  * It needs to send at first the address byte. Bits 7 to 1 of this byte contain the register start address (found in the first column from the table below). Bit 0 of this byte is logic ‘1’ for read transactions,​ and logic ‘0’ for write transactions.+  * It needs to send at first the address byte. Bits 7 to 1 of this byte contain the register start address (found in the first column from Table 10.2.1.3). Bit 0 of this byte is logic ‘1’ for read transactions,​ and logic ‘0’ for write transactions.
   * It then needs to send a second byte, containing the number of bytes to read/write.   * It then needs to send a second byte, containing the number of bytes to read/write.
   * For write transactions,​ it then needs to send the actual values to be written in the Platform MCU registers. The number of bytes sent in this phase needs to match the value from the previous byte (“the number of bytes to read/​write”),​ otherwise communication with the Platform MCU will hang.   * For write transactions,​ it then needs to send the actual values to be written in the Platform MCU registers. The number of bytes sent in this phase needs to match the value from the previous byte (“the number of bytes to read/​write”),​ otherwise communication with the Platform MCU will hang.
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 The UART baudrate should be set to 115200/​8/​E/​1 (115200 baud, 8 data bits, even parity, 1 stop bit). The UART baudrate should be set to 115200/​8/​E/​1 (115200 baud, 8 data bits, even parity, 1 stop bit).
  
-=== 10.2.2 Bootloader Section ​===+---- 
 +== 10.2.2 Bootloader Section ==
 In the program memory, along with the Firmware Application,​ there is a bootloader that launches the Application at power-up. In the program memory, along with the Firmware Application,​ there is a bootloader that launches the Application at power-up.
-==== 10.3 Fan ====+ 
 +---- 
 +=== 10.3 Fan ===
 Mounted on the MPSoC heatsink is a 12 V fan with a 4-pin header. It can automatically controlled by the Platform MCU based on the MPSoC temperature or set to the fixed full speed. This option is controlled by JP2 and is user-selectable. Mounted on the MPSoC heatsink is a 12 V fan with a 4-pin header. It can automatically controlled by the Platform MCU based on the MPSoC temperature or set to the fixed full speed. This option is controlled by JP2 and is user-selectable.
 ^ Jumper JP2 "AUTO FAN" ​ ^ Fan Speed  ^ ^ Jumper JP2 "AUTO FAN" ​ ^ Fan Speed  ^
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 | Not set                | Full       | | Not set                | Full       |
  
-==== 10.4 Coin battery ​====+---- 
 +=== 10.4 Coin battery ===
 A Seiko TS621E lithium rechargeable battery provides power to the MPSoC Battery Power Domain (BPD) through the VCC_PSBATT pin. It is connected in parallel with a 100 uF capacitor. The BPD includes the real-time clock with a dedicated crystal oscillator and a RAM available for storing a secure configuration key. The capacitor alone can provide power for approx. 15 minutes after main power is turned off. The battery will provide power after that. A Seiko TS621E lithium rechargeable battery provides power to the MPSoC Battery Power Domain (BPD) through the VCC_PSBATT pin. It is connected in parallel with a 100 uF capacitor. The BPD includes the real-time clock with a dedicated crystal oscillator and a RAM available for storing a secure configuration key. The capacitor alone can provide power for approx. 15 minutes after main power is turned off. The battery will provide power after that.
  
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 However, those prepared to void their warranty can physically remove the charging circuit by de-soldering D13 or R400. In this case any battery that meets MPSoC voltage specs can be used. However, those prepared to void their warranty can physically remove the charging circuit by de-soldering D13 or R400. In this case any battery that meets MPSoC voltage specs can be used.
 +
 +----