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reference:programmable-logic:eclypse-z7:reference-manual [2020/05/12 01:26]
Arthur Brown
reference:programmable-logic:eclypse-z7:reference-manual [2020/05/12 23:23] (current)
Arthur Brown [8. Zmod Ports]
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 Each SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Each Zmod port has a I/O bank of the Zynq dedicated to it, which is powered by a dedicated adjustable rail, configured by the Platform MCU as the Eclypse is powered on. Template constraints for each Zmod port can be found in the Eclypse Z7's Master XDC file, available through Digilent'​s [[https://​github.com/​Digilent/​digilent-xdc|digilent-xdc]] repository on Github. Each SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Each Zmod port has a I/O bank of the Zynq dedicated to it, which is powered by a dedicated adjustable rail, configured by the Platform MCU as the Eclypse is powered on. Template constraints for each Zmod port can be found in the Eclypse Z7's Master XDC file, available through Digilent'​s [[https://​github.com/​Digilent/​digilent-xdc|digilent-xdc]] repository on Github.
  
-Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[reference:​zmod|Digilent Zmod]].+Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[reference:​zmod:start|Digilent Zmod]].
  
 For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]]. For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]].