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reference:programmable-logic:eclypse-z7:reference-manual [2019/12/04 00:45]
Arthur Brown [Purchasing Options]
reference:programmable-logic:eclypse-z7:reference-manual [2019/12/06 20:57] (current)
Arthur Brown
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 ^ Callout # ^ Description ^ Callout # ^ Description ^ Callout # ^ Description ^ ^ Callout # ^ Description ^ Callout # ^ Description ^ Callout # ^ Description ^
 | 1 | Board Indicator LEDs (LD4)   | 7  | SYZYGY Ports                   | 13 | Reset Buttons (underside of board) | | 1 | Board Indicator LEDs (LD4)   | 7  | SYZYGY Ports                   | 13 | Reset Buttons (underside of board) |
-| 2 | Header for Case Power Switch | 8  | Pmod Ports                     | 14 | MicroSD ​Card Slot                  |+| 2 | Header for Case Power Switch | 8  | Pmod Ports                     | 14 | microSD ​Card Slot                  |
 | 3 | Power Switch ​                | 9  | User Buttons and LEDs          | 15 | USB JTAG/UART Port                 | | 3 | Power Switch ​                | 9  | User Buttons and LEDs          | 15 | USB JTAG/UART Port                 |
 | 4 | FPGA Fan Header ​             | 10 | DDR3L Memory ​                  | 16 | Ethernet Port                      | | 4 | FPGA Fan Header ​             | 10 | DDR3L Memory ​                  | 16 | Ethernet Port                      |
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 --> MIO 16-53 : Bank 501 # --> MIO 16-53 : Bank 501 #
  
-|  **MIO 501 1.8V** ​ |  **Peripherals** ​          ||||+|  **MIO 501 1.8V** ​ | **Peripherals** ​                                              ​|||
 |  Pin               | ENET 0                     | USB 0                   | SD 0     | |  Pin               | ENET 0                     | USB 0                   | SD 0     |
 | 16                 | TXCK                       ​| ​                        ​| ​         | | 16                 | TXCK                       ​| ​                        ​| ​         |
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 ---- ----
 ===== Functional Description ===== ===== Functional Description =====
-==== 1 Power Supplies ====+==== 1Power Supplies ====
  
 The Eclypse Z7 power circuitry was carefully designed to meet the requirements of the Zynq-7000 and all peripherals while providing the flexibility needed to power a variety of different configurations of Zmod/SYZYGY modules. The Eclypse Z7 power circuitry was carefully designed to meet the requirements of the Zynq-7000 and all peripherals while providing the flexibility needed to power a variety of different configurations of Zmod/SYZYGY modules.
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 {{ :​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-power.png?​800 |}} {{ :​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-power.png?​800 |}}
  
-//Figure 1.1 Power circuit overview//+//Figure 1.1Power circuit overview//
 <​html></​center></​html>​ <​html></​center></​html>​
  
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 Two additional indicator LEDs are illuminated when the VIO supplies associated with the two Zmod Ports are powered. LD2 is associated with Zmod Port A and the VADJA rail. LD3 is associated with Zmod Port B and the VADJB rail. Two additional indicator LEDs are illuminated when the VIO supplies associated with the two Zmod Ports are powered. LD2 is associated with Zmod Port A and the VADJA rail. LD3 is associated with Zmod Port B and the VADJB rail.
  
-=== 1.1 Power Input Source ===+=== 1.1Power Input Source ===
 The Eclypse Z7 should be powered via a wall wart supply with barrel jack, via the barrel connector (J11). The supply must use a center-positive 2.1 mm internal-diameter plug and deliver between 11.5V and 12.5V DC. It should also be able to provide at least 5 A (60 Watts) in order to support power hungry Zynq projects and external peripherals. A compatible power supply ships with the Eclypse Z7. The Eclypse Z7 should be powered via a wall wart supply with barrel jack, via the barrel connector (J11). The supply must use a center-positive 2.1 mm internal-diameter plug and deliver between 11.5V and 12.5V DC. It should also be able to provide at least 5 A (60 Watts) in order to support power hungry Zynq projects and external peripherals. A compatible power supply ships with the Eclypse Z7.
  
-//Table 1.1.1Eclypse Z7 Power Input Specifications//​+//Table 1.1.1Eclypse Z7 Power Input Specifications//​
 ^ Connector Type  ^ Connector Label  ^ Schematic Net Name  ^ Min/Rec/Max Voltage (V)  ^ Max Current Consumption ​ | ^ Connector Type  ^ Connector Label  ^ Schematic Net Name  ^ Min/Rec/Max Voltage (V)  ^ Max Current Consumption ​ |
 | Barrel jack  | J11  | VIN12V0 ​ | 11.5/​12/​12.5 ​ | 5 A / 60 W  | | Barrel jack  | J11  | VIN12V0 ​ | 11.5/​12/​12.5 ​ | 5 A / 60 W  |
  
  
-=== 1.2 Power Specifications ===+=== 1.2Power Specifications ===
  
 Table 1.2.1 describes the characteristics of the Eclypse Z7's on-board power rails. It can be used to estimate power consumption for a project, or determine how much current attached peripherals can draw before being limited. Table 1.2.1 describes the characteristics of the Eclypse Z7's on-board power rails. It can be used to estimate power consumption for a project, or determine how much current attached peripherals can draw before being limited.
  
-//Table 1.2.1Eclypse Z7 Power Rail Specifications//​ +//Table 1.2.1Eclypse Z7 Power Rail Specifications//​ 
-^ Net Name  ^ Upstream Net Name ^ Power IC Type ^ Power IC Label ^ Min/Typ/Max Voltage ^ Max. Current ^ Major Devices and Connectors ​| +^ Net Name  ^ Upstream Net Name  ^ Power IC Type  ^ Power IC Label  ^ Min/Typ/Max Voltage ​ ^ Max. Current ​ ^ Major Devices and Connectors ​ ^ 
-| VCC5V0 ​ | VIN12V0 | Buck | IC27 | 5.0V +-5%   ​| 3A | Zmods, USB OTG VBUS, RGB LEDs, Case Fan | +| VCC5V0 ​  ​| VIN12V0 ​ | Buck  | IC27  | 5.0V +-5%    | 3A     ​| Zmods, USB OTG VBUS, RGB LEDs, Case Fan  
-| VCC1V0 ​ | VIN12V0 | Buck | IC27 | 1.0V +-5%   ​| 1A | Zynq, Ethernet, USB OTG, USB JTAG/UART, microSD | +| VCC1V0 ​  ​| VIN12V0 ​ | Buck  | IC27  | 1.0V +-5%    | 1A     ​| Zynq, Ethernet, USB OTG, USB JTAG/UART, microSD ​ 
-| DDR1V35 | VIN12V0 | Buck | IC25 | 1.35V +-5%  | 2A | Zynq, DDR3L | +| DDR1V35 ​ | VIN12V0 ​ | Buck  | IC25  | 1.35V +-5%   ​| 2A     ​| Zynq, DDR3L  
-| DDRVTT ​ | VIN12V0 | LDO  | IC21 | 0.675V +-5% | 0.45A | DDR3L | +| DDRVTT ​  ​| VIN12V0 ​ | LDO   ​| IC21  | 0.675V +-5%  | 0.45A  | DDR3L  
-| VCC3V3 ​ | VIN12V0 | Buck | IC25 | 3.3V +-5%   ​| 3.3A | Zynq, Zmods, Pmods, USB OTG, USB JTAG/UART, microSD | +| VCC3V3 ​  ​| VIN12V0 ​ | Buck  | IC25  | 3.3V +-5%    | 3.3A   ​| Zynq, Zmods, Pmods, USB OTG, USB JTAG/UART, microSD ​ 
-| VCC4V3 ​ | VCC5V0 ​ | LDO  | IC26 | 4.3V +-5%   ​| 0.3A | Pmods | +| VCC4V3 ​  ​| VCC5V0 ​  ​| LDO   ​| IC26  | 4.3V +-5%    | 0.3A   ​| Pmods  
-| VADJA   ​| VIN12V0 | Buck | IC27 | 1.2V to 3.3V; +-5% | 1.8A | FPGA, Zmod Port A | +| VADJA    | VIN12V0 ​ | Buck  | IC27  | 1.2V to 3.3V; +-5%  | 1.8A  | FPGA, Zmod Port A  
-| VADJB   ​| VIN12V0 | Buck | IC27 | 1.2V to 3.3V; +-5% | 1.8A | FPGA, Zmod Port B | +| VADJB    | VIN12V0 ​ | Buck  | IC27  | 1.2V to 3.3V; +-5%  | 1.8A  | FPGA, Zmod Port B  
-| VADJC   ​| VIN12V0 | Buck | IC25 | 2.5 to 5.5V; +- 5% | 0.3A | FPGA Fan |+| VADJC    | VIN12V0 ​ | Buck  | IC25  | 2.5 to 5.5V; +- 5%  | 0.3A  | FPGA Fan  |
  
 The power budget of VCC5V0 is shared by the SYZYGY ports, USB OTG VBUS, RGB LEDs, and Case Fan. As such, the actual maximum current achievable by each peripheral varies with the Eclypse Z7's system configuration. Under worst-case conditions, VCC5V0 is capable of outputting a minimum of 3A of continuous current. In this scenario, 1A is budgeted for each Zmod The power budget of VCC5V0 is shared by the SYZYGY ports, USB OTG VBUS, RGB LEDs, and Case Fan. As such, the actual maximum current achievable by each peripheral varies with the Eclypse Z7's system configuration. Under worst-case conditions, VCC5V0 is capable of outputting a minimum of 3A of continuous current. In this scenario, 1A is budgeted for each Zmod
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 The Platform MCU (PMCU) enumerates the SYZYGY ports and determines the power needs of each Zmod installed in the system. The 5V power budget of the Eclypse is then determined based on the needs of each Zmod, as well as the USB OTG VBUS, RGB LEDs, and Fan. Table 1.2.2 describes the 5V power budget of the Eclypse Z7 in more detail. The Platform MCU (PMCU) enumerates the SYZYGY ports and determines the power needs of each Zmod installed in the system. The 5V power budget of the Eclypse is then determined based on the needs of each Zmod, as well as the USB OTG VBUS, RGB LEDs, and Fan. Table 1.2.2 describes the 5V power budget of the Eclypse Z7 in more detail.
  
-//Table 1.2.2 Eclypse 5V Power Budget// +//Table 1.2.2Eclypse 5V Power Budget// 
-^ Device or Connector ^ Max Current (mA) | +^ Device or Connector ​ ^ Max Current (mA)  ^ 
-| RGB LEDs | 124.8 | +| RGB LEDs  | 124.8  
-| USB OTG VBUS | 500 | +| USB OTG VBUS  | 500  
-| Zmod Port A | 1000 | +| Zmod Port A  | 1000  
-| Zmod Port B | 1000 | +| Zmod Port B  | 1000  
-| Case Fan | 250 |+| Case Fan  | 250  |
  
 The two SYZYGY ports share a budget of 2A from the 3.3V supply. The two Pmod ports share a budget of 0.5A, which is allocated to the SYZYGY ports if no Pmods are installed. The two SYZYGY ports share a budget of 2A from the 3.3V supply. The two Pmod ports share a budget of 0.5A, which is allocated to the SYZYGY ports if no Pmods are installed.
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 Due to the requirements of the custom power sequencer (IC29), Digilent recommends that peripheral modules (Pmods and Zmods) attached to and powered by the Eclypse meet the specifications described in Table 1.2.3. Due to the requirements of the custom power sequencer (IC29), Digilent recommends that peripheral modules (Pmods and Zmods) attached to and powered by the Eclypse meet the specifications described in Table 1.2.3.
  
-//Table 1.2.3Recommended Maximum Additional Capacitance for Add-on Modules// +//Table 1.2.3Recommended Maximum Additional Capacitance for Add-on Modules// 
-^ Port Rail Max Capacitance (µF) |+^ Port Rail Max Capacitance (µF) ^
 | Zmod Port A | VCC5V0 | 500 | | Zmod Port A | VCC5V0 | 500 |
 | Zmod Port A | VCC3V3 | 500 | | Zmod Port A | VCC3V3 | 500 |
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 | Pmod Port B | VCC3V3 | 500 | | Pmod Port B | VCC3V3 | 500 |
  
-=== 1.3 Power Sequencing ===+=== 1.3Power Sequencing ===
 A custom power sequencer (IC29) is used to sequence the power supplies on in the correct order when the power switch is placed in the "​ON"​ position. The power supplies shut down in the opposite order when the power switch is moved to the "​OFF"​ position. The startup sequence is as follows: A custom power sequencer (IC29) is used to sequence the power supplies on in the correct order when the power switch is placed in the "​ON"​ position. The power supplies shut down in the opposite order when the power switch is moved to the "​OFF"​ position. The startup sequence is as follows:
  
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-=== 1.4 FPGA Fan ===+=== 1.4FPGA Fan ===
  
 The FPGA fan is to be connected to the Eclypse Z7 via fan header J8 (labeled "​FPGA"​) and is powered by VADJC, an adjustable rail controlled by the Platform MCU. The FPGA fan's speed can be configured to Automatic (the default factory setting), High, Medium, Low, or Off, by communicating with the PMCU through its I2C interface. This configuration is preserved by the PMCU in an EEPROM when the Eclypse'​s power is cycled. Additional information and configuration settings, including RPM and speed controls, can be accessed through the PMCU's I2C interface. The FPGA fan is to be connected to the Eclypse Z7 via fan header J8 (labeled "​FPGA"​) and is powered by VADJC, an adjustable rail controlled by the Platform MCU. The FPGA fan's speed can be configured to Automatic (the default factory setting), High, Medium, Low, or Off, by communicating with the PMCU through its I2C interface. This configuration is preserved by the PMCU in an EEPROM when the Eclypse'​s power is cycled. Additional information and configuration settings, including RPM and speed controls, can be accessed through the PMCU's I2C interface.
  
-=== 1.5 Case Fan ===+=== 1.5Case Fan ===
  
 In addition to the FPGA fan, the Eclypse Z7 can power a Case Fan, connected to the board via fan header J14 (labeled "​CASE"​). This fan is powered by the 5V rail, and is limited to 250 mA. A compatible fan is included in the [[|Eclypse Z7 Enclosure Kit]] (FIXME). In addition to the FPGA fan, the Eclypse Z7 can power a Case Fan, connected to the board via fan header J14 (labeled "​CASE"​). This fan is powered by the 5V rail, and is limited to 250 mA. A compatible fan is included in the [[|Eclypse Z7 Enclosure Kit]] (FIXME).
  
-=== 1.6 Platform MCU ===+=== 1.6Platform MCU ===
  
 As noted in previous sections, the Eclypse Z7 uses an Atmega328PB microcontroller (IC10), referred to as the Platform MCU (PMCU), to implement the SmartVIO requirements of the SYZYGY standard, as well as to monitor the Zynq die temperature,​ and to control the Eclypse'​s fan. As noted in previous sections, the Eclypse Z7 uses an Atmega328PB microcontroller (IC10), referred to as the Platform MCU (PMCU), to implement the SmartVIO requirements of the SYZYGY standard, as well as to monitor the Zynq die temperature,​ and to control the Eclypse'​s fan.
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 The following tables describe the features of the Platform MCU supported by the Eclypse Z7: The following tables describe the features of the Platform MCU supported by the Eclypse Z7:
  
-//Table 1.6.1 Platform MCU Connectivity Map// +//Table 1.6.1Platform MCU Connectivity Map// 
-^ PMCU Interface ^ Connection ^ +^ PMCU Interface ​ ^ Connection ​ 
-| TEMPERATURE A | Zynq Die Temperature | +| TEMPERATURE A  | Zynq Die Temperature ​ 
-| PORT_A, VADJ_A | Zmod A | +| PORT_A, VADJ_A ​ | Zmod A  
-| PORT_B, VADJ_B | Zmod B | +| PORT_B, VADJ_B ​ | Zmod B  
-| FAN_1 | FPGA Fan | +| FAN_1  | FPGA Fan  
-| FAN_2 | Case Fan |+| FAN_2  | Case Fan  |
  
-//Table 1.6.2 Supported Platform MCU Optional Features//​ +//Table 1.6.2Supported Platform MCU Optional Features//​ 
-^ Optional Features ^ Supported ^ +^ Optional Features ​ ^ Supported ​ 
-| DDRVCCSEL Control | No | +| DDRVCCSEL Control ​ | No  
-| INIT_B Control | No | +| INIT_B Control ​ | No  
-| USB Hub Support | No |+| USB Hub Support ​ | No  |
  
-//Table 1.6.3 Supported Platform MCU Fan COntrol Features//​ +//Table 1.6.3Supported Platform MCU Fan COntrol Features//​ 
-^ Feature ^ FAN_1 (FPGA Fan) ^ FAN_2 (Case Fan) ^ +^ Feature ​ ^ FAN_1 (FPGA Fan)  ^ FAN_2 (Case Fan)  
-| Enable / Disable | Yes | No | +| Enable / Disable ​ | Yes  | No  
-| Fixed Speed Control | Yes | No | +| Fixed Speed Control ​ | Yes  | No  
-| Automatic Speed Control | Yes | No | +| Automatic Speed Control ​ | Yes  | No  
-| RPM Measurement | Yes (if supported by installed fan)[(The optional FPGA fan included with the Eclypse Z7 supports RPM measurement)] | Yes (if supported by installed fan)[(The case fan included in the Eclypse Z7 Enclosure Kit does not support RPM measurement)] |+| RPM Measurement ​ | Yes (if supported by installed fan)[(The optional FPGA fan included with the Eclypse Z7 supports RPM measurement)] ​ | Yes (if supported by installed fan)[(The case fan included in the Eclypse Z7 Enclosure Kit does not support RPM measurement)] ​ |
  
 ~~REFNOTES~~ ~~REFNOTES~~
  
 ---- ----
-==== 2 Zynq Configuration ====+==== 2Zynq Configuration ====
  
 Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7020 are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application. Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7020 are designed around the processor, which acts as a master to the programmable logic fabric and all other on-chip peripherals in the processing system. This causes the Zynq boot process to be more similar to that of a microcontroller than an FPGA. This process involves the processor loading and executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for configuring the programmable logic (optional), and a user application.
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 {{ :​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-config.png?​800 |}} {{ :​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-config.png?​800 |}}
  
-//Figure 2.1Eclypse Z7 configuration pins.//+//Figure 2.1Eclypse Z7 configuration pins.//
 <​html></​center></​html>​ <​html></​center></​html>​
  
 The three boot modes are described in the following sections. The three boot modes are described in the following sections.
  
-=== 2.1 microSD Boot Mode ===+=== 2.1microSD Boot Mode ===
  
 The Eclypse Z7 supports booting from a microSD card inserted into connector J4 (labeled "SD CARD"​). The following procedure will allow you to boot the Zynq from microSD with a standard Zynq Boot Image created with the Xilinx tools: The Eclypse Z7 supports booting from a microSD card inserted into connector J4 (labeled "SD CARD"​). The following procedure will allow you to boot the Zynq from microSD with a standard Zynq Boot Image created with the Xilinx tools:
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   - Turn the board on by flipping the power switch to the ON position. The board will now boot the image on the microSD card.   - Turn the board on by flipping the power switch to the ON position. The board will now boot the image on the microSD card.
  
-=== 2.2 Quad SPI Boot Mode ===+=== 2.2Quad SPI Boot Mode ===
  
 The Eclypse Z7 has an onboard 16 MB Quad-SPI Flash that the Zynq can boot from. Documentation available from Xilinx describes how to use Xilinx SDK to program a Zynq Boot Image into a Flash device attached to the Zynq. Once the Quad SPI Flash has been loaded with a Zynq Boot Image, the following steps can be followed to boot from it: The Eclypse Z7 has an onboard 16 MB Quad-SPI Flash that the Zynq can boot from. Documentation available from Xilinx describes how to use Xilinx SDK to program a Zynq Boot Image into a Flash device attached to the Zynq. Once the Quad SPI Flash has been loaded with a Zynq Boot Image, the following steps can be followed to boot from it:
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   - Turn the board on by flipping the power switch to the ON position. The board will now boot the image stored in the Quad SPI flash.   - Turn the board on by flipping the power switch to the ON position. The board will now boot the image stored in the Quad SPI flash.
  
-=== 2.3 JTAG Boot Mode ===+=== 2.3JTAG Boot Mode ===
 When placed in JTAG boot mode, with the two leftmost pins of JP5 shorted (labeled "​JTAG"​),​ the processor will wait until software is loaded by a host computer using the Xilinx tools. After software has been loaded, it is possible to either let the software begin executing, or step through it line by line using Xilinx SDK.  When placed in JTAG boot mode, with the two leftmost pins of JP5 shorted (labeled "​JTAG"​),​ the processor will wait until software is loaded by a host computer using the Xilinx tools. After software has been loaded, it is possible to either let the software begin executing, or step through it line by line using Xilinx SDK. 
  
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 ---- ----
-==== 3 DDR3L Memory ====+==== 3DDR3L Memory ====
 The Eclypse Z7 includes two Micron MT41K256M16TW-107 DDR3L memory components creating a single rank, 32-bit wide interface and a total of 1 GiB (Gibi-byte, or 1,​073,​741,​824 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation. The Eclypse Z7 includes two Micron MT41K256M16TW-107 DDR3L memory components creating a single rank, 32-bit wide interface and a total of 1 GiB (Gibi-byte, or 1,​073,​741,​824 bytes) of capacity. The DDR3L is connected to the hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation.
  
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 For more details on memory controller operation, refer to the Xilinx [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]]. For more details on memory controller operation, refer to the Xilinx [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].
 ---- ----
-==== 4 Quad-SPI Flash ====+==== 4Quad-SPI Flash ====
  
 The Eclypse Z7 features a Spansion S25FL128S 4-bit Quad-SPI serial NOR flash. The key device attributes are:  The Eclypse Z7 features a Spansion S25FL128S 4-bit Quad-SPI serial NOR flash. The key device attributes are: 
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 The OTP region also includes a factory-programmed read-only 128-bit random number. The very lowest address range [0x00;0x0F] can be read to access the random number. See the Spansion S25FL128S datasheet for information on this random number and accessing the OTP region. The OTP region also includes a factory-programmed read-only 128-bit random number. The very lowest address range [0x00;0x0F] can be read to access the random number. See the Spansion S25FL128S datasheet for information on this random number and accessing the OTP region.
 ---- ----
-==== 5 Oscillators/​Clocks ====+==== 5Oscillators/​Clocks ====
  
 The Eclypse Z7 provides a 33.3333 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 33.3333 MHz input allows the processor to operate at a maximum frequency of 667 MHz and the DDR3 memory controller to operate at a maximum clock rate of 533 MHz (1066 MT/s). The Eclypse Z7 board files, available on the [[start|Eclypse Z7 Resource Center]], will automatically configure the Zynq processing system IP core in Vivado to work with all PS attached devices, including the 33.3333 MHz input oscillator. ​ The Eclypse Z7 provides a 33.3333 MHz clock to the Zynq PS_CLK input, which is used to generate the clocks for each of the PS subsystems. The 33.3333 MHz input allows the processor to operate at a maximum frequency of 667 MHz and the DDR3 memory controller to operate at a maximum clock rate of 533 MHz (1066 MT/s). The Eclypse Z7 board files, available on the [[start|Eclypse Z7 Resource Center]], will automatically configure the Zynq processing system IP core in Vivado to work with all PS attached devices, including the 33.3333 MHz input oscillator. ​
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 {{:​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-clocks.png?​600|}} {{:​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-clocks.png?​600|}}
  
-//Figure 5.1Eclypse Z7 clocking.//+//Figure 5.1Eclypse Z7 clocking.//
 <​html></​center></​html>​ <​html></​center></​html>​
  
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 ---- ----
-==== 6 Reset Sources ====+==== 6Reset Sources ====
 The Eclypse Z7 provides several different methods of resetting the Zynq-7000 device, as described in the following sections: The Eclypse Z7 provides several different methods of resetting the Zynq-7000 device, as described in the following sections:
  
-=== Power-on Reset ===+=== 6.1. Power-on Reset ===
 The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Eclypse Z7 drives this signal from the VCC4V3 supply, the final non-adjustable supply to be brought up in the power-on sequence, in order to hold the system in reset until all power supplies are valid. A push-button,​ labeled BTNP, can be used to toggle the power-on reset signal. BTNP is located on the underside of the Eclypse Z7, below the SD card slot. The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip. This signal resets every register in the device capable of being reset. The Eclypse Z7 drives this signal from the VCC4V3 supply, the final non-adjustable supply to be brought up in the power-on sequence, in order to hold the system in reset until all power supplies are valid. A push-button,​ labeled BTNP, can be used to toggle the power-on reset signal. BTNP is located on the underside of the Eclypse Z7, below the SD card slot.
  
-==== 6.2 Processor Subsystem Reset ====+==== 6.2Processor Subsystem Reset ====
  
 The external system reset button, labeled BTNR, resets the Zynq device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing the boot mode jumper a power cycle is needed to act on the new setting. BTNR is located on the underside of the Eclypse Z7, below the SD card slot. The external system reset button, labeled BTNR, resets the Zynq device without disturbing the debug environment. For example, the previous break points set by the user remain valid after system reset. Due to security concerns, system reset erases all memory content within the PS, including the On-Chip-Memory (OCM). The PL is also cleared during a system reset. System reset does not cause the boot mode strapping pins to be re-sampled. After changing the boot mode jumper a power cycle is needed to act on the new setting. BTNR is located on the underside of the Eclypse Z7, below the SD card slot.
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 ---- ----
-==== 7 USB-UART Bridge (Serial Port) ====+==== 7USB-UART Bridge (Serial Port) ====
  
 The Eclypse Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that lets PC applications communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux when the Eclypse Z7 is attached. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller. The Eclypse Z7 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J6) that lets PC applications communicate with the board using standard COM port commands (or the tty interface in Linux). Drivers are automatically installed in Windows and newer versions of Linux when the Eclypse Z7 is attached. Serial port data is exchanged with the Zynq using a two-wire serial port (TXD/RXD). After the drivers are installed, I/O commands can be used from the PC directed to the COM port to produce serial data traffic on the Zynq pins. The port is tied to PS (MIO) pins and can be used in combination with the UART 0 controller.
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 {{:​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-uart.png?​nolink&​500|}} {{:​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-uart.png?​nolink&​500|}}
  
-//Figure 7.1UART Connections//​+//Figure 7.1UART Connections//​
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 ---- ----
-==== 8 Zmod Ports ====+==== 8Zmod Ports ====
  
 The Eclypse Z7 features two Zmod ports, which use SYZYGY Standard interfaces to communicate with installed SYZYGY pods. Both ports are compatible with version 1.1 of the SYZYGY specification from Opal Kelly. The Eclypse Z7 features two Zmod ports, which use SYZYGY Standard interfaces to communicate with installed SYZYGY pods. Both ports are compatible with version 1.1 of the SYZYGY specification from Opal Kelly.
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 For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]]. For more information on the SYZYGY standard, see [[https://​syzygyfpga.io/​|syzygyfpga.io]].
  
-=== 8.1 SYZYGY Pod Compatibility ===+=== 8.1SYZYGY Pod Compatibility ===
  
 The Eclypse'​s Zmod ports are compatible with a variety of different SYZYGY pods. Information required to determine if the Eclypse is compatible with a certain pod is summarized in Table 8.1.1. The Eclypse'​s Zmod ports are compatible with a variety of different SYZYGY pods. Information required to determine if the Eclypse is compatible with a certain pod is summarized in Table 8.1.1.
  
-//Table 8.1.1SYZYGY Compatibility Table//+//Table 8.1.1SYZYGY Compatibility Table//
  
-^Parameter^Port A (STD)^Port B (STD)| + Parameter ​  Port A (STD)   Port B (STD)  ^ 
-^Port Type|Standard|Standard| + Port Type   Standard ​  Standard ​ 
-^:::​|Double-Width Capable|| + :::   Double-Width Capable ​ || 
-^Total 5V Supply Current|3.0 A (shared with USB VBUS output, Case Fan, and RGB LEDs)|| + Total 5V Supply Current ​  3.0 A (shared with USB VBUS output, Case Fan, and RGB LEDs)  || 
-^Total 3.3V Supply Current| 2.0 A Shared|| + Total 3.3V Supply Current ​  2.0 A Shared ​ || 
-^VIO Supply Voltage Range|1.2V to 3.3V|1.2V to 3.3V| + VIO Supply Voltage Range   1.2V to 3.3V   1.2V to 3.3V  
-^Total VIO Supply Current|1.8A (VIO Group 1)|1.8A (VIO Group 2)| + Total VIO Supply Current ​  1.8A (VIO Group 1)   1.8A (VIO Group 2)  
-^Port Groups|Group 1: A|Group 2: B| + Port Groups ​  Group 1: A   Group 2: B  
-^I/O Count|28 total (8 DP)|28 total (8 DP)| + I/O Count   28 total (8 DP)   28 total (8 DP)  
-^Length Matching|73.7 mm +- 0.2 mm (including Zynq package delay)| + Length Matching ​  73.7 mm +- 0.2 mm (including Zynq package delay) ​ ||
- +
-=== 8.2 Mechanical === +
- +
-FIXME //Is there any information on this not encapsulated by the syzygy spec?//+
  
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-==== 9 microSD Slot ====+==== 9microSD Slot ====
  
 The Eclypse Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 9.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported. The Eclypse Z7 provides a microSD slot (J4) for non-volatile external memory storage as well as booting the Zynq. The slot is wired to Bank 1/501 MIO[40-45], and also includes a card detect signal attached to MIO 47. On the PS side, peripheral SDIO 0 is mapped out to these pins and controls communication with the SD card. The pinout can be seen in Table 9.1. The peripheral controller supports 1-bit and 4-bit SD transfer modes, but does not support SPI mode. Based on the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]], SDIO host mode is the only mode supported.
  
-//Table 9.1. MicroSD ​pinout//+//Table 9.1: microSD ​pinout//
  
-**Signal Name**  ​**Description**  ​**Zynq Pin**  ​**SD Slot Pin**  ​|+**Signal Name**  ​**Description**  ​**Zynq Pin**  ​**SD Slot Pin**  ​^
 | **SD_D0** ​       | Data[0] ​         | MIO42         | 7                | | **SD_D0** ​       | Data[0] ​         | MIO42         | 7                |
 | **SD_D1** ​       | Data[1] ​         | MIO43         | 8                | | **SD_D1** ​       | Data[1] ​         | MIO43         | 8                |
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 {{reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-micro-sd.png?​600|}} {{reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-micro-sd.png?​600|}}
  
-//Figure 9.1microSD slot signals//+//Figure 9.1microSD slot signals//
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-==== 10 USB Micro-AB Device/​Host/​OTG Port ====+==== 10USB Micro-AB Device/​Host/​OTG Port ====
  
 The Eclypse Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The usb0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface can act as an host, embedded host, or a peripheral device, through the USB Micro AB connector(J5). The USB mode is controlled from software by manipulating the USB0 peripheral controller in the Zynq PS. The Eclypse Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The usb0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface can act as an host, embedded host, or a peripheral device, through the USB Micro AB connector(J5). The USB mode is controlled from software by manipulating the USB0 peripheral controller in the Zynq PS.
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 /* FIXME Overcurrent and other abnormal conditions on VBUS can be detected by checking the status of the USBOTG_OC signal, mapped to the PS GPIO peripheral through MIO49. This signal is driven by the <​html><​span style="​text-decoration:​ overline;"></​html>​FLAG<​html></​span></​html>​ pin of the ON Semiconductor NCP380 current limiting switch used to source VBUS. */ /* FIXME Overcurrent and other abnormal conditions on VBUS can be detected by checking the status of the USBOTG_OC signal, mapped to the PS GPIO peripheral through MIO49. This signal is driven by the <​html><​span style="​text-decoration:​ overline;"></​html>​FLAG<​html></​span></​html>​ pin of the ON Semiconductor NCP380 current limiting switch used to source VBUS. */
  
-//Table 10.1 USB Mode Jumper Positions//​ +//Table 10.1USB Mode Jumper Positions//​ 
-^Mode^JP1 Shorted^JP2 Shorted^ +^ Mode  ^ JP1 Shorted ​ ^ JP2 Shorted ​ 
-|Embedded Host|No|Yes| +| Embedded Host  | No  | Yes  
-|General Purpose Host|Yes|Yes| +| General Purpose Host  | Yes  | Yes  
-|Peripheral Device|No|No|+| Peripheral Device ​ | No  | No  |
  
 ---- ----
-==== 11 Ethernet ====+==== 11Ethernet ====
  
 The Eclypse Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to PS pins to be accessed through the MIO GPIO peripheral via MIO48 and MIO9 respectively. The connection diagram can be seen on Figure 11.1. The Eclypse Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to PS pins to be accessed through the MIO GPIO peripheral via MIO48 and MIO9 respectively. The connection diagram can be seen on Figure 11.1.
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 {{ :​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-ethernet.png?​600 |}} {{ :​reference:​programmable-logic:​eclypse-z7:​reference-manual:​eclypse-ethernet.png?​600 |}}
  
-//Figure 11.1Ethernet PHY signals//+//Figure 11.1Ethernet PHY signals//
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 Two status indicator LEDs are located on the RJ-45 connector (J3) that indicate traffic (J3/LD2, right side of connector) and valid link state (J3/LD1, left side of connector). Table 11.1 shows the default behavior. Two status indicator LEDs are located on the RJ-45 connector (J3) that indicate traffic (J3/LD2, right side of connector) and valid link state (J3/LD1, left side of connector). Table 11.1 shows the default behavior.
  
-//Table 11.1Ethernet status LEDs//+//Table 11.1Ethernet status LEDs//
  
-|  ​**Function**  ​|  ​**Designator**  ​|  ​**State** ​               ​|  ​**Description** ​                           | +**Function**  ​**Designator**  ​**State** ​                ^ **Description** ​                            ^ 
- LINK          |  J3/​LD1 ​         | Steady on                 | Link 10/​100/​1000 ​                           | +| LINK          | J3/​LD1 ​         | Steady on                 | Link 10/​100/​1000 ​                           | 
-| :::            | :::              | Blinking 0.4s ON, 2s OFF  | Link, Energy Efficient Ethernet (EEE) mode  | +| :::           ​| :::             ​| Blinking 0.4s ON, 2s OFF  | Link, Energy Efficient Ethernet (EEE) mode  | 
- ACT           ​| ​ J3/​LD2 ​         | Blinking ​                 | Transmitting or Receiving ​                  |+| ACT           | J3/​LD2 ​         | Blinking ​                 | Transmitting or Receiving ​                  |
  
 The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Eclypse Z7 Vivado board files. The Zynq incorporates two independent Gigabit Ethernet Controllers. They implement a 10/100/1000 half/full duplex Ethernet MAC. Of these two, GEM 0 can be mapped to the MIO pins where the PHY interfaces. Since the MIO bank is powered from 1.8V, the RGMII interface uses 1.8V HSTL Class 1 drivers. For this I/O standard an external reference of 0.9V is provided in bank 501 (PS_MIO_VREF). Mapping out the correct pins and configuring the interface is handled by the Eclypse Z7 Vivado board files.
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 ---- ----
  
-==== 12 Basic I/O ====+==== 12Basic I/O ====
 The Eclypse Z7 includes two push-buttons and two tri-color LEDs connected to the Zynq PL, as shown in Figure 12.1. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output). The Eclypse Z7 includes two push-buttons and two tri-color LEDs connected to the Zynq PL, as shown in Figure 12.1. These I/Os are connected to the Zynq via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if a pin assigned to a push-button was inadvertently defined as an output).
  
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-=== 12.1 Push-Buttons ===+=== 12.1Push-Buttons ===
  
 The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The push-buttons are "​momentary"​ switches that normally generate a low output when they are at rest, and a high output only when they are pressed.
  
-=== 12.2 Tri-Color LEDs ===+=== 12.2Tri-Color LEDs ===
  
 Each tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the input signal corresponding to one of these colors low will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding PL pins need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color. Each tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs: one red, one blue, and one green. Driving the input signal corresponding to one of these colors low will illuminate the internal LED. The input signals are driven by the Zynq PL through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding PL pins need to be driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if the red and blue signals are driven high and green is driven low, the tri-color LED will emit a purple color.
  
-**Note:** //Digilent strongly recommends the use of pulse-width modulation (PWM) when driving the tri-colo LEDs. Driving any of the signals to a steady logic '​1'​ will result in the LED being illuminated at an uncomfortably bright level. This can be avoided by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the tri-color LED. Individually adjusting the duty cycle of each color between 0% and 50% causes the different colors to be illuminated at different intensities,​ allowing virtually any color to be displayed.//​+**Note**//Digilent strongly recommends the use of pulse-width modulation (PWM) when driving the tri-colo LEDs. Driving any of the signals to a steady logic '​1'​ will result in the LED being illuminated at an uncomfortably bright level. This can be avoided by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the tri-color LED. Individually adjusting the duty cycle of each color between 0% and 50% causes the different colors to be illuminated at different intensities,​ allowing virtually any color to be displayed.//​
  
 ---- ----
-==== 13 Pmod Ports ====+==== 13Pmod Ports ====
  
 Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 13.1. The VCC and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets of the on-board regulators or the external power supply (as described in the [[#​power_supplies|Power supplies]] section). ​ Pmod ports are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 13.1. The VCC and Ground pins can deliver up to 1A of current, but care must be taken not to exceed any of the power budgets of the on-board regulators or the external power supply (as described in the [[#​power_supplies|Power supplies]] section). ​
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 {{:​basys3-pmod_connector.png?​350|Figure 13.1. Pmod connector.}} {{:​basys3-pmod_connector.png?​350|Figure 13.1. Pmod connector.}}
  
-//Figure 13.1Pmod port//+//Figure 13.1Pmod port//
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