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reference:programmable-logic:cora-z7:reference-manual [2018/06/14 22:49]
Arthur Brown [Purchasing Options and Board Variants]
reference:programmable-logic:cora-z7:reference-manual [2018/11/01 18:37] (current)
Arthur Brown Add DQS_TO_CLK errata
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 +====== Hardware errata ======
 +Although we strive to provide perfect products, we are not infallible. The Cora Z7 is subject to the limitations below.
 +^ Product Name  ^ Variant ​ ^ Revision ​ ^ Problem ​                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ^ Status ​       ^
 +| Cora Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >​2017.4:​\\ [PSU-1] ​ Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal,​ but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Cora Z7 was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration,​ 0 is used as an initial value instead of the negative preset delays. After calibration,​ if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Cora Z7 boards shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://​www.xilinx.com/​support/​answers/​53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given. ​ | will not fix  |
  
 {{tag>rm doc cora-z7}} {{tag>rm doc cora-z7}}