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reference:programmable-logic:cora-z7:reference-manual [2018/05/17 19:09]
Arthur Brown created
reference:programmable-logic:cora-z7:reference-manual [2018/06/14 22:49] (current)
Arthur Brown [Purchasing Options and Board Variants]
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 The Cora Z7’s wide array of hardware interfaces, from a 1Gbps Ethernet PHY to analog-to-digital converters and general-purpose input/​output pins, make it an ideal platform for the development of a vast variety of embedded applications. The small form factor and mounting holes make the Cora Z7 ready to be used as one component of a larger solution. The on-board SD Card slot, Ethernet, and Power solution allow the Cora Z7 to operate independently of a host computer. The Cora Z7’s wide array of hardware interfaces, from a 1Gbps Ethernet PHY to analog-to-digital converters and general-purpose input/​output pins, make it an ideal platform for the development of a vast variety of embedded applications. The small form factor and mounting holes make the Cora Z7 ready to be used as one component of a larger solution. The on-board SD Card slot, Ethernet, and Power solution allow the Cora Z7 to operate independently of a host computer.
  
-FIXME Digilent Image Gallery+{{Digilent Image Gallery ​ 
 +| image = {{ :​reference:​programmable-logic:​cora-z7:​cora-obl-600.png?​direct |}} 
 +| image = {{ :​reference:​programmable-logic:​cora-z7:​cora-top-600.png?​direct |}} 
 +| image = {{ :​reference:​programmable-logic:​cora-z7:​cora-bottom-600.png?​direct |}} 
 +| image = {{ :​reference:​programmable-logic:​cora-z7:​cora-inuse-600.png?​direct |}} 
 +}}
  
 ---- ----
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   * **ZYNQ Processor**   * **ZYNQ Processor**
     * 667MHz dual-core (*single-core) Cortex-A9 processor     * 667MHz dual-core (*single-core) Cortex-A9 processor
 +    * FPGA Programmable logic equivalent to Artix-7 FPGA
 +      * 4,400 Programmable logic slices (*3,600)
 +      * 80 DSP slices (*60)
 +      * 270 KB of block RAM (*225 KB)
     * DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports     * DDR3 memory controller with 8 DMA channels and 4 High Performance AXI3 Slave ports
     * High-bandwidth peripheral controllers:​ 1G Ethernet, USB 2.0, SDIO     * High-bandwidth peripheral controllers:​ 1G Ethernet, USB 2.0, SDIO
     * Low-bandwidth peripheral controllers:​ SPI, UART, CAN, I2C     * Low-bandwidth peripheral controllers:​ SPI, UART, CAN, I2C
 +    * Dual-channel,​ 1 MSPS internal analog-digital converter
     * Programmable from JTAG and microSD card     * Programmable from JTAG and microSD card
-    * Programmable logic equivalent to Artix-7 FPGA 
   * **Memory**   * **Memory**
     * 512MB DDR3 with 16-bit bus @ 1050Mbps     * 512MB DDR3 with 16-bit bus @ 1050Mbps
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     * Powered from USB or any 4.5V-5.5V external power source     * Powered from USB or any 4.5V-5.5V external power source
   * **USB and Ethernet**   * **USB and Ethernet**
-    * Gigabit Ethernet PHY FIXME (48-bit globally unique EUI-48/​64™ compatible identifier available on sticker)+    * Gigabit Ethernet PHY with 48-bit globally unique EUI-48/​64™ compatible identifier available on sticker
     * USB-JTAG programming circuitry     * USB-JTAG programming circuitry
     * USB-UART bridge     * USB-UART bridge
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 (*Z7-07S variant in parentheses where different) (*Z7-07S variant in parentheses where different)
  
-====== Purchasing Options ======+{{ cora-z7-callout.png?​800 |}}
  
-The Cora Z7 can be purchased with either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Arty Z7-20, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.+^ Callout ​ ^ Description ​                              ^ Callout ​ ^ Description ​                            ^ 
 +| 1        | Power select jumper (Ext. supply / USB)   | 11       | microSD card slot (underside of board) ​ | 
 +| 2        | Power jack (for optional ext. supply) ​    | 12       | USB host port                           | 
 +| 3        | Shared USB JTAG / UART port               | 13       | FPGA programming DONE LED               | 
 +| 4        | Unloaded expansion header ​                | 14       | Processor subsystem reset button ​       | 
 +| 5        | Pmod connectors ​                          | 15       | Ethernet port                           | 
 +| 6        | SPI header (Arduino/​ChipKIT compatible) ​  | 16       | Power on reset button ​                  | 
 +| 7        | Arduino/​ChipKIT shield connectors ​        | 17       | Power good LED                          | 
 +| 8        | Programming mode jumper (JTAG / microSD) ​ | 18       | Zynq-7000 ​                              | 
 +| 9        | User tri-color LEDs                       | 19       | DDR3L memory ​                           | 
 +| 10       | User push buttons ​                        ​| ​         |                                         | 
 + 
 +====== Purchasing Options and Board Variants ====== 
 + 
 +The Cora Z7 can be purchased with either a Zynq-7010 or Zynq-7007S loaded. These two Cora Z7 product variants are referred to as the Cora Z7-10 and Cora Z7-07S, respectively. When Digilent documentation describes functionality that is common to both of these variants, they are referred to collectively as the "Cora Z7". When describing something that is only common to a specific variant, the variant will be explicitly called out by its name.
  
 The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities,​ but the -10 has about a 1.2 times larger internal FPGA and an additional processor core, as compared to the -07S. The differences between the two variants are summarized below: The only difference between the Cora Z7-10 and Cora Z7-07S is the capability of the Zynq part. The Zynq processors both have the same capabilities,​ but the -10 has about a 1.2 times larger internal FPGA and an additional processor core, as compared to the -07S. The differences between the two variants are summarized below:
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 ^ Look-up Tables (LUTs) ​   | 17,​600 ​              | 14,​400 ​              | ^ Look-up Tables (LUTs) ​   | 17,​600 ​              | 14,​400 ​              |
 ^ Flip-Flops ​              | 35,​200 ​              | 28,​800 ​              | ^ Flip-Flops ​              | 35,​200 ​              | 28,​800 ​              |
 +^ DSP Slices ​              | 80                   | 66                   |
 ^ Block RAM                | 270 KB               | 225 KB               | ^ Block RAM                | 270 KB               | 225 KB               |
 ^ Clock Management Tiles   | 2                    | 2                    | ^ Clock Management Tiles   | 2                    | 2                    |
- +/* 
-FIXME Optional SDSOC Voucher. +FIXME Optional 5 Volt Amp Power Supply
- +
-FIXME Optional 5 Volt FIXME Amp Power Supply+
  
 FIXME Optional Micro USB Cable. FIXME Optional Micro USB Cable.
  
 FIXME Optional microSD Card with Out-of-Box Demonstration Project. FIXME Optional microSD Card with Out-of-Box Demonstration Project.
- +*/ 
-For more information on purchasing, see the [[http://​store.digilentinc.com/​arty-z7-apsoc-zynq-7000-development-board-for-makers-and-hobbyists/|Cora Z7 Product Page]]. ​FIXME link+For more information on purchasing, see the [[https://​store.digilentinc.com/​cora-z7/|Cora Z7 Product Page]].
  
 **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[:​reference:​programmable-logic:​arty-z7:​start|Arty Z7-20]] //if they are interested in these types of applications.//​ **Note:** //Due to the sizes of the FPGAs in the Zynq-7010 and Zynq-7007S, they are not very well suited to be used in SDSoC for embedded vision applications. We recommend people purchase the// [[:​reference:​programmable-logic:​arty-z7:​start|Arty Z7-20]] //if they are interested in these types of applications.//​
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 The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL. The Cora Z7 is fully compatible with Xilinx’s high-performance Vivado Design Suite. This toolset melds FPGA logic design and embedded ARM software development into an easy to use, intuitive design flow. It can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. It is also possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in using the processor in their design. As of Vivado release 2015.4, the Logic Analyzer and High-level Synthesis features of Vivado are free to use for all WebPACK targets, which includes the Cora Z7. The Logic Analyzer assists with debugging logic, and the HLS tool allows you to compile C code directly into HDL.
  
-FIXME XDC and Board Files+Master ​XDC files and Board files for the Cora Z7-10 and Z7-07S are available through the [[start|Cora Z7 Resource Center]]. These files are used to inform Vivado about how the Zynq chip on the Cora is configured and connected to the rest of the Cora.
  
 Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information,​ see the [[start|Cora Z7 Resource Center]]. Zynq platforms are well-suited to be embedded Linux targets, and Cora Z7 is no exception. To help you get started, Digilent provides a Petalinux project that will get you up and running with a Linux system quickly. For more information,​ see the [[start|Cora Z7 Resource Center]].
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 //Figure 1.1 Cora Z7 Power Circuit// //Figure 1.1 Cora Z7 Power Circuit//
  
-FIXME Add power-on-reset button? +The USB port can deliver enough power for the vast majority of designs. However, a few demanding applications,​ including any that drive multiple peripheral boards, might require more power than the USB port can provide. Also, some applications may need to run without being connected to a PC’s USB port. In these instances an external power supply can be used by plugging into the Power Jack (J15). The supply must use a coaxial, center-positive 2.1mm (or 2.5mm) internal-diameter plug, and provide a DC voltage of 5 Volts. The supply should provide a minimum current of 1 amp. Ideally, the supply should be capable of providing ​20 Watts of power (5 Volts DC, amps). If the USB port is to be used to deliver power, the Power Select Jumper (JP3) should be set to "​USB"​. If an external power supply is to be used, JP3 should be set to "​EXT"​ instead.
- +
-The USB port can deliver enough power for the vast majority of designs. However, a few demanding applications,​ including any that drive multiple peripheral boards, might require more power than the USB port can provide. Also, some applications may need to run without being connected to a PC’s USB port. In these instances an external power supply can be used by plugging into the Power Jack (J15). The supply must use a coaxial, center-positive 2.1mm (or 2.5mm) internal-diameter plug, and provide a DC voltage of 5 Volts. The supply should provide a minimum current of 1 amp. Ideally, the supply should be capable of providing ​FIXME Watts of power (5 Volts DC, FIXME amps). If the USB port is to be used to deliver power, the Power Select Jumper (JP3) should be set to "​USB"​. If an external power supply is to be used, JP3 should be set to "​EXT"​ instead.+
  
 Voltage regulator circuits from Dialog Semiconductor and ON Semiconductor create the required 3.3V, 1.8V, 1.35V, and 1.00V supplies from the 5V power source. In the event that an external supply or battery pack is used, the on-board Monolithic Power Systems 5V regulator (IC12) provides the 5V source. Table 1.1 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs). The 0.675V supply is created by a simple Voltage divider circuit consisting of two 10 KOhm resistors, sourced from the 1.35V rail. Voltage regulator circuits from Dialog Semiconductor and ON Semiconductor create the required 3.3V, 1.8V, 1.35V, and 1.00V supplies from the 5V power source. In the event that an external supply or battery pack is used, the on-board Monolithic Power Systems 5V regulator (IC12) provides the 5V source. Table 1.1 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs). The 0.675V supply is created by a simple Voltage divider circuit consisting of two 10 KOhm resistors, sourced from the 1.35V rail.
  
 ^ Supply ​ ^ Circuits ​                                                       ^ Device ​                                                ^ Maximum Current ​ ^ ^ Supply ​ ^ Circuits ​                                                       ^ Device ​                                                ^ Maximum Current ​ ^
-| 5.0V    | Onboard Regulators, Arduino/​chipKit Shield Connector, RGB LEDs  | IC4: ON Semiconductor NCP380[(With JP3 set to "​USB"​)] ​ | FIXME TBD        ​|+| 5.0V    | Onboard Regulators, Arduino/​chipKit Shield Connector, RGB LEDs  | IC4: ON Semiconductor NCP380[(With JP3 set to "​USB"​)] ​ |         ​|
 | 3.3V    | FPGA I/O, USB port, Ethernet ​                                   | IC15: Dialog Semiconductor DA9062 ​                     | 2A               | | 3.3V    | FPGA I/O, USB port, Ethernet ​                                   | IC15: Dialog Semiconductor DA9062 ​                     | 2A               |
 | 1.0V    | FPGA, Ethernet ​                                                 | IC15: Dialog Semiconductor DA9062 ​                     | 2.5A             | | 1.0V    | FPGA, Ethernet ​                                                 | IC15: Dialog Semiconductor DA9062 ​                     | 2.5A             |
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 The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series FPGA, and it must be configured either directly by the processor or via the JTAG port. The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series FPGA, and it must be configured either directly by the processor or via the JTAG port.
  
-The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect,​ DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU only contains one, see FIXME [[#​single-vs-dual-core-zynq|Section 2.1 for more information]]. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect,​ and contain readable/​writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore,​ cores implemented in the PL can trigger interrupts to the processors (connections not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory.+The PS consists of many components, including the Application Processing Unit (APU), Advanced Microcontroller Bus Architecture (AMBA) Interconnect,​ DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). The Zynq-7010 APU contains two Cortex-A9 processors, while the Zynq-7007S APU only contains one. Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect,​ and contain readable/​writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore,​ cores implemented in the PL can trigger interrupts to the processors (connections not shown in Figure 2.1) and perform Direct Memory Access (DMA) transfers to and from DDR3 memory.
  
 There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description,​ refer to the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]]. ​ There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description,​ refer to the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference Manual]]. ​
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 ---- ----
  
-==== 2.1 Single versus Dual Core Zynq ==== 
- 
-FIXME Is this section necessary? 
- 
----- 
 ===== 3 Zynq Configuration ===== ===== 3 Zynq Configuration =====
  
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 The Cora Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The USB0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface is configured to act as an embedded host. USB OTG and USB device modes are not supported. The Cora Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is powered at 1.8V. The USB0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface is configured to act as an embedded host. USB OTG and USB device modes are not supported.
  
-The Cora Z7 is technically an “embedded host”, because it does not provide the required 150 µF of capacitance on VBUS required to qualify as a general purpose host. It is possible to modify the Cora Z7 so that it complies with the general purpose USB host requirements by loading C35 with a 150 µF capacitor. Only those experienced at soldering small components on PCBs should attempt this rework. Many USB peripheral devices will work just fine without loading C35. Whether the Cora Z7 is configured as an embedded host or a general purpose host, it can provide ​FIXME 1A on the 5V VBUS line. FIXME (comment) /*Note that loading C35 may cause the Cora Z7 to reset when booting embedded Linux while powered from the USB port, regardless of if any USB device is connected to the host port. This is caused by the in-rush current that C35 causes when the USB host controller is enabled and the VBUS power switch (IC9) is turned on.*/+The Cora Z7 is technically an “embedded host”, because it does not provide the required 150 µF of capacitance on VBUS required to qualify as a general purpose host. It is possible to modify the Cora Z7 so that it complies with the general purpose USB host requirements by loading C35 with a 150 µF capacitor. Only those experienced at soldering small components on PCBs should attempt this rework. Many USB peripheral devices will work just fine without loading C35. Whether the Cora Z7 is configured as an embedded host or a general purpose host, it can provide 1A on the 5V VBUS line.
  
-Note that if your design uses the USB Host port (embedded or general purpose), then the Cora Z7 should be powered via a wall adapter capable of providing more power FIXME (comment) /*(such as the one included in the Cora Z7 accessory kit)*/.+Note that if your design uses the USB Host port (embedded or general purpose), then the Cora Z7 should be powered via a wall adapter capable of providing more power.
  
 ---- ----
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 The Cora Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. ​ The Cora Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 APSoC via RGMII for data and MDIO for management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to MIO pins MIO10 and MIO9, respectively. ​
  
-{{ :​internal:​development:​cora-z7:​cora-ethernet.png?​direct&​500 |Figure 8.1. Ethernet PHY signals}}+{{ cora-ethernet.png?​direct&​500 |Figure 8.1. Ethernet PHY signals}}
 //Figure 8.1. Ethernet PHY signals// //Figure 8.1. Ethernet PHY signals//
  
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 The PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough to be driven from a single source. The PHY is clocked from the same 50 MHz oscillator that clocks the Zynq PS. The parasitic capacitance of the two loads is low enough to be driven from a single source.
  
-On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/​64™ compatible identifier. ​FIXME more info?+On an Ethernet network each node needs a unique MAC address. To this end, a sticker has been applied to the Cora Z7 at the factory, displaying a 48-bit globally unique EUI-48/​64™ compatible identifier.
  
 For more information on using the Gigabit Ethernet MAC, refer to the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]]. For more information on using the Gigabit Ethernet MAC, refer to the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].
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 Figure 9.1 outlines the clocking scheme used on the Cora Z7. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low. Figure 9.1 outlines the clocking scheme used on the Cora Z7. Note that the reference clock output from the Ethernet PHY is used as the 125 MHz reference clock to the PL, in order to cut the cost of including a dedicated oscillator for this purpose. Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low.
  
-{{ :​internal:​development:​cora-z7:​cora-z7-clocking.png?​nolink&​800 | Figure 9.1 Cora Z7 Clocking}}+{{ cora-z7-clocking.png?​nolink&​800 | Figure 9.1 Cora Z7 Clocking}}
  
 //Figure 9.1. Cora Z7 Clocking// //Figure 9.1. Cora Z7 Clocking//
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 The Cora Z7 board includes two tri-color LEDs and 2 push buttons as shown in Figure 11.1. The push buttons are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output). The two push buttons are “momentary” switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The Cora Z7 board includes two tri-color LEDs and 2 push buttons as shown in Figure 11.1. The push buttons are connected to the Zynq PL via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output). The two push buttons are “momentary” switches that normally generate a low output when they are at rest, and a high output only when they are pressed.
  
-{{ :​internal:​development:​cora-z7:​cora-basic-io.png?​direct&​800 |Figure 11.1 Cora Z7 Basic I/O}}+{{ cora-basic-io.png?​direct&​800 |Figure 11.1 Cora Z7 Basic I/O}}
  
 //Figure 11.1. Cora Z7 Basic I/O// //Figure 11.1. Cora Z7 Basic I/O//
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 ===== 12 Pmod Connectors ===== ===== 12 Pmod Connectors =====
  
-Pmod connectors are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 15.1. The VCC and Ground pins can deliver up to 100mA FIXME of current, but care must be taken not to exceed any of the power budgets of the onboard regulators or the external power supply (see the 3.3V rail current limits listed in the "Power Supplies"​ section). ​+Pmod connectors are 2x6, right-angle,​ 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 15.1. The VCC and Ground pins can deliver up to 100mA of current, but care must be taken not to exceed any of the power budgets of the onboard regulators or the external power supply (see the 3.3V rail current limits listed in the "Power Supplies"​ section). ​
  
 {{ :​reference:​programmable-logic:​arty-z7:​arty-z7-pmod.png?​300 |}} {{ :​reference:​programmable-logic:​arty-z7:​arty-z7-pmod.png?​300 |}}
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 The High-speed Pmods have their data signals routed as impedance matched differential pairs for maximum switching speeds. They have pads for loading resistors for added protection, but the Cora Z7 ships with these loaded as 0-Ohm shunts. With the series resistors shunted, these Pmods offer no protection against short circuits, but allow for much faster switching speeds. The signals are paired to the adjacent signals in the same row: pins 1 and 2, pins 3 and 4, pins 7 and 8, and pins 9 and 10.  The High-speed Pmods have their data signals routed as impedance matched differential pairs for maximum switching speeds. They have pads for loading resistors for added protection, but the Cora Z7 ships with these loaded as 0-Ohm shunts. With the series resistors shunted, these Pmods offer no protection against short circuits, but allow for much faster switching speeds. The signals are paired to the adjacent signals in the same row: pins 1 and 2, pins 3 and 4, pins 7 and 8, and pins 9 and 10. 
  
-Traces are routed 100 ohm (+/- 10%) differential. ​FIXME confirm+Traces are routed 100 ohm (+/- 10%) differential.
  
 If pins on this port are used as single-ended signals, coupled pairs may exhibit crosstalk. In applications where this is a concern, one of the signals should be grounded (drive it low from the FPGA) and use its pair for the signal-ended signal. If pins on this port are used as single-ended signals, coupled pairs may exhibit crosstalk. In applications where this is a concern, one of the signals should be grounded (drive it low from the FPGA) and use its pair for the signal-ended signal.
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 Figure 13.1 diagrams the pins found on the shield connector of the Cora Z7. Figure 13.1 diagrams the pins found on the shield connector of the Cora Z7.
  
-{{ :​internal:​development:​cora-z7:​cora-shield.png?​direct&​600 |Figure 13.1. Shield connector pin diagram}}+{{ cora-shield.png?​direct&​600 |Figure 13.1. Shield connector pin diagram}}
 //Figure 13.1. Shield connector pin diagram.// //Figure 13.1. Shield connector pin diagram.//
  
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 The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5, the Cora Z7 uses an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 13.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Cora Z7's GND) that is applied to any of these pins. The pins labeled A0-A5 can also be used as digital inputs or outputs, as they are also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 13.2.1). The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V. On the pins labeled A0-A5, the Cora Z7 uses an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 13.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the Cora Z7's GND) that is applied to any of these pins. The pins labeled A0-A5 can also be used as digital inputs or outputs, as they are also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 13.2.1).
  
-{{ :​internal:​development:​cora-z7:​cora-analog-single-ended.png?​direct&​600 |Figure 13.2.1. Single-Ended Analog Inputs}}+{{ cora-analog-single-ended.png?​direct&​600 |Figure 13.2.1. Single-Ended Analog Inputs}}
 //Figure 13.2.1. Single-Ended Analog Inputs// //Figure 13.2.1. Single-Ended Analog Inputs//
  
 The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 13.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even-numbered pins are connected to the positive pins of the trio and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O.  The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is shown in Figure 13.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even-numbered pins are connected to the positive pins of the trio and the odd numbers are connected to the negative pins (so A6 and A7 form an analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use these pins for Digital I/O. 
  
-{{ :​internal:​development:​cora-z7:​cora-analog-differential.png?​direct&​600 |Figure 13.2.2. Differential Analog Inputs}}+{{ cora-analog-differential.png?​direct&​600 |Figure 13.2.2. Differential Analog Inputs}}
 //Figure 13.2.2. Differential Analog Inputs// //Figure 13.2.2. Differential Analog Inputs//
  
 The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 13.2.3 for this pair of pins is loaded on the Cora Z7. The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown in Figure 13.2.3 for this pair of pins is loaded on the Cora Z7.
  
-{{ :​internal:​development:​cora-z7:​cora-analog-dedicated.png?​direct&​500 |Figure 13.2.3. Dedicated Analog Input Pair}}+{{ cora-analog-dedicated.png?​direct&​500 |Figure 13.2.3. Dedicated Analog Input Pair}}
 //Figure 13.2.3. Dedicated Analog Input Pair// //Figure 13.2.3. Dedicated Analog Input Pair//
  
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 The Cora Z7 has an additional 12 Digital I/O pins in the form of a 16-pin unloaded expansion header (J1). The two outer-most pins (labeled V) of this header are connected to the Cora Z7's 3.3V rail. The next two outermost pins (labeled G) are connected to ground. The remaining 12 pins (labeled IO2-IO13) are directly connected to the Zynq PL. Zynq PL pin mappings for the unloaded expansion header can be found in the Cora Z7 master XDC file, available through the [[start|Cora Z7 Resource Center]]. The Cora Z7 has an additional 12 Digital I/O pins in the form of a 16-pin unloaded expansion header (J1). The two outer-most pins (labeled V) of this header are connected to the Cora Z7's 3.3V rail. The next two outermost pins (labeled G) are connected to ground. The remaining 12 pins (labeled IO2-IO13) are directly connected to the Zynq PL. Zynq PL pin mappings for the unloaded expansion header can be found in the Cora Z7 master XDC file, available through the [[start|Cora Z7 Resource Center]].
  
-{{ :​internal:​development:​cora-z7:​cora-unloaded-header.png?​direct&​500 |Figure 14.1. Unloaded Expansion Header}}+{{ cora-unloaded-header.png?​direct&​500 |Figure 14.1. Unloaded Expansion Header}}
  
 //Figure 14.1. Unloaded Expansion Header// //Figure 14.1. Unloaded Expansion Header//
  
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