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reference:programmable-logic:arty-z7:reference-manual [2018/02/05 09:45]
Elod Gyorgy Added differences from PYNQ-Z1
reference:programmable-logic:arty-z7:reference-manual [2018/07/02 16:15] (current)
Arthur Brown [2 Zynq APSoC Architecture]
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 The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors),​ Advanced Microcontroller Bus Architecture (AMBA) Interconnect,​ DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect,​ and contain readable/​writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore,​ cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory. The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9 processors),​ Advanced Microcontroller Bus Architecture (AMBA) Interconnect,​ DDR3 Memory controller, and various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are connected to the processors as slaves via the AMBA interconnect,​ and contain readable/​writable control registers that are addressable in the processors’ memory space. The programmable logic is also connected to the interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain addressable control registers. Furthermore,​ cores implemented in the PL can trigger interrupts to the processors (connections not shown in Fig. 3) and perform DMA accesses to DDR3 memory.
  
-There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description,​ refer to the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference ​manual]]. +There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a complete and thorough description,​ refer to the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference ​Manual]]. 
  
 Table 2.1 depicts the external components connected to the MIO pins of the Arty Z7. The Zynq Presets File found on the [[reference:​programmable-logic:​arty-z7:​start|Arty Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. ​ Table 2.1 depicts the external components connected to the MIO pins of the Arty Z7. The Zynq Presets File found on the [[reference:​programmable-logic:​arty-z7:​start|Arty Z7 Resource Center]] can be imported into EDK and Vivado Designs to properly configure the PS to work with these peripherals. ​