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reference:programmable-logic:arty-z7:reference-manual [2018/07/02 16:15]
Arthur Brown [2 Zynq APSoC Architecture]
reference:programmable-logic:arty-z7:reference-manual [2019/01/14 19:51] (current)
jon peyron
Line 264: Line 264:
 ====== 4 Quad SPI Flash ====== ====== 4 Quad SPI Flash ======
  
-The Arty Z7 features a Quad SPI serial NOR flash. ​The Spansion S25FL128S is used on this board. The Multi-I/O SPI Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem. ​+The Arty Z7 features a Quad SPI serial NOR flash. ​This Multi-I/O SPI Flash memory is used to provide non-volatile code and data storage. It can be used to initialize the PS subsystem as well as configure the PL subsystem. ​
  
 The relevant device attributes are:  The relevant device attributes are: 
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 The SPI Flash connects to the Zynq-7000 APSoC and supports the Quad SPI interface. This requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/​MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad SPI clock frequency greater than FQSPICLK2 (See the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]] for more on this). ​ The SPI Flash connects to the Zynq-7000 APSoC and supports the Quad SPI interface. This requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/​MIO[8] is left to freely toggle and is connected only to a 20K pull-up resistor to 3.3V. This allows a Quad SPI clock frequency greater than FQSPICLK2 (See the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]] for more on this). ​
 +
 +In manufacturing,​ parts sometimes need to be replaced when the product goes end-of-life. The Quad SPI Flash memory on any particular Arty Z7 may be one of the drop-in replacements found in the Table 4.1 below. To determine which part is used by a particular board, look at the part number printed on IC19 on the bottom of the Arty Z7 (See Figure 4.1).
 +
 +{{:​reference:​programmable-logic:​arty-z7:​arty-z7-flash-callout-600.png?​nolink&​400|}}
 +
 +//Figure 4.1. Arty Z7 Flash IC Location//
 +
 +^ Manufacturer ​ ^ Part Number ​ ^
 +| Spansion ​ | S25FL128SAGMFI00 ​ |
 +| Micron ​ | MT25QL128ABA8ESF-0SIT ​ |
 +| Micron ​ | MT25QL128ABA8ESF-0AAT ​ |
 +| Micron ​ | N25Q128A13ESF40E ​ |
 +
 +//Table 4.1. Arty Z7 Flash IC Drop-in Replacements//​
  
 ---- ----
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 The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter"​. It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]]. The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled "7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter"​. It is also possible to access the XADC core directly using the PS, via the “PS-XADC” interface. This interface is described in full in chapter 30 of the [[http://​www.xilinx.com/​support/​documentation/​user_guides/​ug585-Zynq-7000-TRM.pdf|Zynq Technical Reference manual]].
 +
 +
 +====== Hardware errata ======
 +Although we strive to provide perfect products, we are not infallible. The Arty Z7 is subject to the limitations below.
 +^ Product Name  ^ Variant ​ ^ Revision ​ ^ Problem ​                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ^ Status ​       ^
 +| Arty Z7       | All      | All       | Negative CK-to-DQS delays in the board files are causing critical warnings in Vivado >​2017.4:​\\ [PSU-1] ​ Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values. \\ \\ The negative values are due to CK trace being shorter than any of the four DQS traces.\\ \\ In the early days of Zynq board design negative values where listed as sub-optimal,​ but not erroneous. Tree topology instead of fly-by was also among the routing recommendations for DDR3 layouts. So the Arty (Z7) was designed with this sub-optimal layout due to space constraints. During Write Leveling calibration,​ 0 is used as an initial value instead of the negative preset delays. After calibration,​ if the skew is still too low, the clock is inverted. See ug585 pg 316 for more details. All Arty (Z7)s shipped to customers are functionally tested and pass the DDR3 calibration process. \\ \\ Xilinx recommendations changed in the mean time, both in terms of routing topology and delay values. A trace of this can be found here: https://​www.xilinx.com/​support/​answers/​53039.html. The > 0ns requirement was introduced to be in line with non-Zynq MIG-based designs, where negative delays were never permitted. \\ \\ To silence the warnings, zero board delays can be set in Processing System configuration. The calibration algorithm seems to be using zero starting values anyway when negative delays are given. ​ | will not fix  |
  
 {{tag>rm doc arty-z7}} {{tag>rm doc arty-z7}}