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reference:pmod:pmodi2s2:reference-manual [2018/05/04 16:04]
James Colvin
reference:pmod:pmodi2s2:reference-manual [2018/05/08 21:44] (current)
Arthur Brown
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 ====== Pmod I2S2 Reference Manual ====== ====== Pmod I2S2 Reference Manual ======
  
-The Digilent Pmod I2S2 (Revision A) features a [[|Cirrus CS5343 Multi-Bit Audio A/D Converter]] and a [[https://​www.cirrus.com/​products/​cs4344-45-48/​|Cirrus CS4344 Stereo D/A Converter]],​ each connected to 3.5mm Audio Jacks. These circuits allow a system board to transmit and receive stereo audio signals via the I2S protocol. The Pmod I2S2 supports 24 bit resolution per channel at input sample rates up to 108kHz ​and output sample rates up to 200kHz+The Digilent Pmod I2S2 (Revision A) features a [[|Cirrus CS5343 Multi-Bit Audio A/D Converter]] and a [[https://​www.cirrus.com/​products/​cs4344-45-48/​|Cirrus CS4344 Stereo D/A Converter]],​ each connected to one of two audio jacks. These circuits allow a system board to transmit and receive stereo audio signals via the I2S protocol. The Pmod I2S2 supports 24 bit resolution per channel at input sample rates up to 108 kHz and output sample rates up to 200 kHz
  
 {{Digilent Image Gallery ​ {{Digilent Image Gallery ​
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   * Stereo 24-bit A/D and D/A converters for I2S audio input and output   * Stereo 24-bit A/D and D/A converters for I2S audio input and output
-  * Standard 1/8" ​(3.5mm) stereo audio jacks+  * Standard 1/8 in (3.5mm) stereo audio jacks
   * Optional automatic serial clock generation for audio input   * Optional automatic serial clock generation for audio input
   * 12-pin Pmod Port with two I2S interfaces   * 12-pin Pmod Port with two I2S interfaces
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 |  3    |  D/A SCLK  |  I2S Line Out Converter Serial Clock       ​|:::​| ​ 9    |  A/D SCLK   ​| ​ I2S Line In Converter Serial Clock        | |  3    |  D/A SCLK  |  I2S Line Out Converter Serial Clock       ​|:::​| ​ 9    |  A/D SCLK   ​| ​ I2S Line In Converter Serial Clock        |
 |  4    |  D/A SDIN  |  I2S Line Out Converter Serial Data Input  |:::|  10   ​| ​ A/D SDOUT  |  I2S Line In Converter Serial Data Output ​ | |  4    |  D/A SDIN  |  I2S Line Out Converter Serial Data Input  |:::|  10   ​| ​ A/D SDOUT  |  I2S Line In Converter Serial Data Output ​ |
-|  5    |  GND         ​|  Power Supply Ground ​                    ​|:::|  11   ​| ​ GND        |  Power Supply Ground ​                      | +|  5    |  GND       ​|  Power Supply Ground ​                      ​|:::|  11   ​| ​ GND        |  Power Supply Ground ​                      | 
-|  6    |  VCC         ​|  Power Supply (3.3V/5V                 |:::|  12   ​| ​ VCC        |  Power Supply (3.3V/5V                   |+|  6    |  VCC       ​|  Power Supply (3.3 or 5.0 V              ​|:::|  12   ​| ​ VCC        |  Power Supply (3.3 or 5.0 V              ​|
  
 ^  Jumper JP1                                        ^^ ^  Jumper JP1                                        ^^
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 The CS4344 and CS5343 (henceforth referred to as the "​line-out converter"​ and "​line-in converter",​ respectively) are each connected (to the host board) via their own I2S interface. As seen in the (Pinout table) above, the line-out converter'​s I2S interface is connected to the top row interface of Pmod connector J1, while the line-in converter'​s I2S interface is connected to the bottom row. The CS4344 and CS5343 (henceforth referred to as the "​line-out converter"​ and "​line-in converter",​ respectively) are each connected (to the host board) via their own I2S interface. As seen in the (Pinout table) above, the line-out converter'​s I2S interface is connected to the top row interface of Pmod connector J1, while the line-in converter'​s I2S interface is connected to the bottom row.
  
-Any external power applied to the Pmod I2S must be within ​3V and 5.25V; however, it is recommended that Pmod is operated at 3.3V. Digital logic levels must correspond to the power supply voltage.+Any external power applied to the Pmod I2S must be within ​3 V and 5.25 V; however, it is recommended that Pmod is operated at 3.3 V. Digital logic levels must correspond to the power supply voltage.
  
 === I2S Overview === === I2S Overview ===
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 The fastest clock signal of each I2S interface will be the Master Clock (MCLK); as the name implies, this signal will keep everything nicely synchronized. The Left-Right Clock (LRCK), also known as the Word Select Clock, indicates whether a particular set of data is associated with the left or right audio channel for stereo sound. The fastest clock signal of each I2S interface will be the Master Clock (MCLK); as the name implies, this signal will keep everything nicely synchronized. The Left-Right Clock (LRCK), also known as the Word Select Clock, indicates whether a particular set of data is associated with the left or right audio channel for stereo sound.
  
-The final clock is the Serial Clock (SCLK), also known as the Bit Clock. The line in and line-out converters can each either be provided this clock signal, or generate it internally. More information on how the serial clocks for each converter can be found (below).+The final clock is the Serial Clock (SCLK), also known as the Bit Clock. The line-in and line-out converters can each either be provided this clock signal, or generate it internally. More information on how the serial clocks for each converter can be found (below).
  
 The I2S protocol requires that data is clocked in on the falling edge of SCLK. The first bit of data (MSB) is not clocked in on the falling edge until the first complete serial clock cycle has passed after LRCK has changed state. Data must be valid on the rising edge of SCLK. The I2S protocol requires that data is clocked in on the falling edge of SCLK. The first bit of data (MSB) is not clocked in on the falling edge until the first complete serial clock cycle has passed after LRCK has changed state. Data must be valid on the rising edge of SCLK.
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 |  :::                |  384x                 ​| ​ 64                   ​| ​ 86-108 ​                            | |  :::                |  384x                 ​| ​ 64                   ​| ​ 86-108 ​                            |
  
-In Master Mode, both LRCK and SCLK are automatically generated by the line-in converter. For Master Mode, the provided MCLK rate must be within the range of 4-54KHz. Once the line-in converter has powered up, it automatically selects an MCLK/LRCK ratio of 256x/512x, depending on the MCLK rate.+In Master Mode, both LRCK and SCLK are automatically generated by the line-in converter. For Master Mode, the provided MCLK rate must be within the range of 4-54 KHz. Once the line-in converter has powered up, it automatically selects an MCLK/LRCK ratio of 256x/512x, depending on the MCLK rate.
  
 **Note**: The CS5343'​s Double-Speed Mode is not available in Master Mode on the Pmod I2S2. **Note**: The CS5343'​s Double-Speed Mode is not available in Master Mode on the Pmod I2S2.
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 ===== Quick Start ===== ===== Quick Start =====
  
-To set up a simple 44.1kHz audio passthrough,​ three control signals need to be generated by the host system board.+To set up a simple 44.1 kHz audio passthrough,​ three control signals need to be generated by the host system board.
  
 1. A master clock (MCLK) at a frequency of approximately 22.579 MHz. 1. A master clock (MCLK) at a frequency of approximately 22.579 MHz.