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| reference:instrumentation:zmodadc:reference-manual [2019/10/25 13:29] – [Features] Mircea Dabacan | reference:instrumentation:zmodadc:reference-manual [2019/11/11 20:29] (current) – removed Arthur Brown | ||
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| - | ====== Zmod ADC Reference Manual ====== | ||
| - | |||
| - | The Digilent Zmod ADC is an open-source hardware SYZYGY™ ((The “SYZYGY™ ” mark is owned by Opal Kelly.))compatible pod containing a dual-channel ADC and the associated front end. The Zmod ADC is intended to be used with any SYZYGY™ compatible carrier board having the required capabilities. | ||
| - | {{Digilent Image Gallery | ||
| - | | image = {{reference/ | ||
| - | | image = {{: | ||
| - | }} | ||
| - | |||
| - | // | ||
| - | |||
| - | The analog inputs can be connected to a circuit using SMA cables. Driven by the SYZYGY™ carrier, the Zmod ADC can acquire two simultaneous signals | ||
| - | |||
| - | |||
| - | The Zmod ADC was designed to be a piece in a modular, HW and SW open-source ecosystem. Combined with a SYZYGY™ carrier, other SYZYGY™ compatible pods, Zmod ADC can be used for a variety of applications: | ||
| - | |||
| - | ===== Features ===== | ||
| - | |||
| - | * Channels: 2 | ||
| - | * Channel type: single ended | ||
| - | * Resolution: | ||
| - | * Input range: ±1V (High Gain) or ±25V (Low Gain) | ||
| - | * Absolute Resolution 0.13mV (High Gain) or 3.21mV (Low Gain) | ||
| - | * Accuracy ±10mV±0.5% FIXME (High Gain) or ±100mV±0.5% FIXME (Low Gain) | ||
| - | * Sample rate (real time): 100MS/s | ||
| - | * Input impedance: 1MΩ||18pF | ||
| - | * Analog bandwidth: 70 MHz+ @ 3dB, 30 MHz @ 0.5dB, 20 MHz @ 0.1dB | ||
| - | * Input protected to: ±50V | ||
| - | |||
| - | ===== 1. Architectural Overview and Block Diagram ===== | ||
| - | |||
| - | This document describes the Zmod ADC's circuits, with the intent of providing a better understanding of its electrical functions, operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information to enable complete duplication of the Zmod ADC, but can help users to design custom configurations for programmable parts in the design. | ||
| - | |||
| - | Zmod ADC' | ||
| - | |||
| - | The **Analog Input** block is also called the **Scope**, because of similar structure and behavior to such a front end. The signals in this circuitry use a " | ||
| - | |||
| - | * The** Analog Inputs/ | ||
| - | * **Input Divider and Gain Selection**: | ||
| - | * **Buffer**: high impedance buffer | ||
| - | * **Driver**: provides appropriate signal levels and protection to the ADC. | ||
| - | * **Scope Reference**: | ||
| - | * **ADC**: the analog-to-digital converter for both scope channels. | ||
| - | * The **Power Supplies and Control** block generates all internal supply voltages. | ||
| - | * The **MCU** works as a I2C memory for two different purposes: | ||
| - | * The **DNA** includes the standard [[https:// | ||
| - | * The **Calibration Memory** stores all calibration parameters. Except for the “Probe Calibration” trimmers in the scope Input divider, the Zmod ADC includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The application software uses these parameters to correct the acquired data and the generated signals | ||
| - | |||
| - | In the sections that follow, schematics are not shown separately for identical blocks. | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | ---- | ||
| - | ===== 2. Scope ===== | ||
| - | |||
| - | ==== 2.1. Scope Input Divider and Gain Selection ==== | ||
| - | |||
| - | [[reference: | ||
| - | |||
| - | C< | ||
| - | |||
| - | The IC1 relay switches between two symmetrical R-C dividers. Each of them provide: | ||
| - | * Scope input impedance = 1MOhm || 18pF | ||
| - | * Two different attenuations for high-gain/ | ||
| - | * Controlled capacitance, | ||
| - | * Constant attenuation over a large frequency range (trimmer adjusted) | ||
| - | The maximum voltage rating for scope inputs is limited to: | ||
| - | |||
| - | $$-50V< | ||
| - | |||
| - | The DC low gain is: $$\frac {V_{SC-LG}}{V_{SCOPE-SMA}}=\frac {R_5}{R_1+R_3+R_5}=0.04\label{2}\tag{2}$$ | ||
| - | |||
| - | The low gain range: $$-25V \le V_{SCOPE-SMA} | ||
| - | |||
| - | The high gain is: $$\frac {V_{SC-HG}}{V_{SCOPE-SMA}} = \frac {R_4 + R_6}{R_2 + R_4 + R_6} = 0.96 \label{4}\tag{4}$$ | ||
| - | |||
| - | The high gain range: $$-1V \le V_{SCOPE-SMA} \le 1V \label{5}\tag{5}$$ | ||
| - | |||
| - | The two dividers are designed to have the same equivalent impedance (both active and reactive): | ||
| - | |||
| - | $$R_{ech} = R_1 + R_3 + R_5 = R_2 + R_4 + R_6 = 1Mohm\label{6}\tag{6}$$ | ||
| - | |||
| - | Experiments shown that there are significant parasitic capacities of the layout and buffer input stage: C< | ||
| - | |||
| - | $$C_3*R_2 = (C_{PH} + C_6)*(R_4+R_6)\label{7}\tag{7}$$ | ||
| - | $$(C_{PH} + C_6) = \frac{C_3*R_2}{R_4+R_6} = 18pF\label{8}\tag{8}$$ | ||
| - | |||
| - | $$(C_4 + C_5)*(R_1 + R_3) = (C_{PL} + C_7)*R_5\label{9}\tag{9}$$ | ||
| - | $$(C_{PL} + C_7) = (C_4 + C_5)*\frac{(R_1 + R_3)}{R_5}\label{10}\tag{10}$$ | ||
| - | |||
| - | With the chosen values, the correct adjustment results in about mid-position of trimmers C< | ||
| - | |||
| - | $$C_5 = C_6 = 7pF\label{11}\tag{11}$$ | ||
| - | |||
| - | which solves the parasitic capacities as: | ||
| - | |||
| - | $$C_{PH} = 11pF\label{12}\tag{12}$$ | ||
| - | $$C_{PL} = 8.8pF\label{13}\tag{13}$$ | ||
| - | |||
| - | The Low Gain and High Gain dividers have very close equivalent capacitance, | ||
| - | |||
| - | $$C_{HGech} = \frac{C_3*R_2}{R_2+R_4+R_6} = C_{ech} = 17.28pF\label{14}\tag{14}$$ | ||
| - | $$C_{LGech} = \frac{(C_7+C_{PL})*R_5}{R_1+R_3+R_5} = 16.03p\label{15}\tag{15}$$ | ||
| - | |||
| - | Experiments show that the equivalent capacitances are even closer than the values above, about 18pF. The computing error mainly derives from trimmer position approximation. | ||
| - | |||
| - | $$C_{ech} = 18p\label{16}\tag{16}$$ | ||
| - | |||
| - | The IC2 relay shorts the C1 capacitor when DC coupling is desired. Otherwise, C1 forms a High Pass filter with the selected divider, for AC coupling, with the corner frequency: | ||
| - | |||
| - | $$f_c = \frac{1}{2*\pi*R_{ech}*(C_{ech}+C_{1})} \approx \frac{1}{2*\pi*R_{ech}*C_{1}} = 10.6Hz\label{17}\tag{17}$$ | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | IC1 and IC2 in [[reference: | ||
| - | The nominal coil voltage is 4.5V. | ||
| - | |||
| - | The IC16, IC17 and IC18 in [[reference: | ||
| - | |||
| - | * Low RDS(on) outputs | ||
| - | * Standby mode with zero current drain | ||
| - | * Small 2 × 2 DFN package | ||
| - | * Crossover Current protection | ||
| - | * Thermal Shutdown protection | ||
| - | |||
| - | Normally, all of them have both HIN and LIN inputs " | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | IC14 and IC15 in [[reference: | ||
| - | |||
| - | * 5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic | ||
| - | * Wide supply voltage range from 1.2 V to 5.5 V | ||
| - | * CMOS low power consumption | ||
| - | * Direct interface with TTL levels | ||
| - | * Inputs accept voltages up to 5 V | ||
| - | * Complies with JEDEC standard: | ||
| - | * JESD8-7A (1.65 V to 1.95 V) | ||
| - | * JESD8-5A (2.3 V to 2.7 V) | ||
| - | * JESD8-C/ | ||
| - | * ESD protection: | ||
| - | * HBM JESD22-A114F exceeds 2000 V | ||
| - | * MM JESD22-A115-B exceeds 200 V | ||
| - | * CDM JESD22-C101E exceeds 1000 V | ||
| - | * Specified from -40 °C to +85 °C and -40 °C to +125 °C | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | ==== 2.2. Scope Buffer ==== | ||
| - | |||
| - | A non-inverting [[https:// | ||
| - | |||
| - | * High speed | ||
| - | * −3 dB bandwidth (G = 1, RL = 100 Ω): 1050 MHz | ||
| - | * Slew rate: 870 V/µs | ||
| - | * 0.1% settling time: 9 ns | ||
| - | * Input bias current: 2 pAtypical | ||
| - | * Input capacitance | ||
| - | * Common-mode capacitance: | ||
| - | * Differential mode capacitance: | ||
| - | * Low input noise | ||
| - | * Voltage noise: 4 nV/√Hz at 100 kHz | ||
| - | * Current noise: 2.5 fA/√Hz at 100 kHz | ||
| - | * Low distortion: −90 dBc at 10 MHz (G = 1, RL = 1 kΩ) | ||
| - | * Linear output current: 40 mA | ||
| - | * Supply quiescent current per amplifier: 19 mAtypical | ||
| - | * Powered down supply quiescent current per amplifier: 1.5 mAtypical | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | The [[https:// | ||
| - | |||
| - | The maximum input voltage swing is: $-2.5V< | ||
| - | |||
| - | The maximum output voltage swing is: $-1.3V< | ||
| - | |||
| - | The gain is: $$\frac {V_{BUFF}}{V_{SC-HLG}}=1\label{20}\tag{20}$$ | ||
| - | |||
| - | The actual input and output range (for nominal usage) is: $-1V< | ||
| - | |||
| - | The [[https:// | ||
| - | |||
| - | The Zmod ADC is specified to resist to accidental input voltages up to +/-50V. In these cases, the buffer input voltage is limited by the protection diodes at 0.6V above the AVCC4V5 or below AVCC-2V5. The protection current is limited by R2 (at High Gain) or R1+R3 (at Low Gain) (see the input divider schematic). The worse case is V< | ||
| - | |||
| - | $$I_{+}=\frac{V_{SCOPE-SMA}-V_{AVCC-2V5}}{R_2}=\frac{-50V+2.5V}{40.2kohm}=-1.18mA\label{22}\tag{22}$$ | ||
| - | |||
| - | ==== 2.3. Scope Reference ==== | ||
| - | |||
| - | In [[reference: | ||
| - | |||
| - | [[http:// | ||
| - | * Initial accuracy: ±0.1% (maximum) | ||
| - | * Maximum temperature coefficient: | ||
| - | * Operating temperature range: −40°C to +125°C | ||
| - | * Output current: +10 mA source/−3 mA sink | ||
| - | * Low quiescent current: 100 μA (maximum) | ||
| - | * Low dropout voltage: 250 mV at 2 mA | ||
| - | * Output noise (0.1 | ||
| - | |||
| - | {{: | ||
| - | {{: | ||
| - | // | ||
| - | |||
| - | The ADC reference voltage is: | ||
| - | $$V_{REFADC}=V_{REF1V2SC}*\frac {R_{73}}{R_{71}+R_{73}}=1V\label{23}\tag{23}$$ | ||
| - | |||
| - | An [[https:// | ||
| - | |||
| - | [[https:// | ||
| - | * Low power: 1.1 mA/amp | ||
| - | * Low wideband noise | ||
| - | * 2.1 nV/√Hz | ||
| - | * 1.4 pA/√Hz | ||
| - | * Low 1/f noise | ||
| - | * 7 nV/√Hz @ 10 Hz | ||
| - | * 13 pA/√Hz @ 10 Hz | ||
| - | * Low distortion: −105 dBc @ 100 kHz, VO = 2 V p-p | ||
| - | * High speed | ||
| - | * 80 MHz, −3 dB bandwidth (G = +1) | ||
| - | * 12 V/µs slew rate | ||
| - | * 175 ns settling time to 0.1% | ||
| - | * Low offset voltage: 0.3 mV maximum | ||
| - | * Rail-to-rail output | ||
| - | * Power down | ||
| - | * Wide supply range: 2.7 V to 12 V | ||
| - | |||
| - | {{: | ||
| - | {{: | ||
| - | // | ||
| - | |||
| - | The ADC VCM voltage is: | ||
| - | $$V_{CMSC}=V_{VCMADC}=V_{VCMADC0V9}*(1+\frac {R_{65}}{R_{70}})=1.2V\label{24}\tag{24}$$ | ||
| - | |||
| - | An [[https:// | ||
| - | |||
| - | [[https:// | ||
| - | * Trimmed to High Accuracy: 0.04% Max | ||
| - | * Low Drift: 3ppm/°C Max | ||
| - | * Low Supply Current: 50µA Max | ||
| - | * High Output Current: 50mA Min | ||
| - | * Low Dropout Voltage: 300mV Max | ||
| - | * Excellent Thermal Regulation | ||
| - | * Power Shutdown | ||
| - | * Thermal Limiting | ||
| - | * All Parts Guaranteed Functional from –40°C to 125°C | ||
| - | * Voltage Options: 2.5V, 3V, 3.3V, 4.096V and 5V | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | ---- | ||
| - | |||
| - | ==== 2.4. Scope Driver ==== | ||
| - | |||
| - | IC2, [[https:// | ||
| - | |||
| - | * Low Noise: 1.6nV/√Hz RTI | ||
| - | * Low Power: 18mA at 3V | ||
| - | * Low Distortion (HD2/HD3): | ||
| - | * –80dBc/ | ||
| - | * –104dBc/ | ||
| - | * Rail-to-Rail Differential Input | ||
| - | * 2.7V to 3.5V Supply Voltage Range | ||
| - | * Fully Differential Input and Output | ||
| - | * Adjustable Output Common Mode Voltage | ||
| - | * 800MHz –3dB Bandwidth with AV = 1 | ||
| - | * Gain-Bandwidth Product: 3GHz | ||
| - | * Low Power Shutdown | ||
| - | * Available in 8-Lead MSOP and Tiny 16-Lead | ||
| - | * 3mm × 3mm × 0.75mm QFN Packages | ||
| - | |||
| - | It is used for: | ||
| - | * Driving the differential inputs of the ADC (with low impedance outputs) | ||
| - | * Providing the common mode voltage for the ADC | ||
| - | * ADC protection: IC2 is supplied 3V, while the ADC inputs only support -0.1…2.1V. | ||
| - | |||
| - | {{: | ||
| - | {{: | ||
| - | // | ||
| - | |||
| - | The input common mode voltage range is rail-to-rail: | ||
| - | $$0V \le V_{+LTC6406} = V_{-LTC6406} \le 3V \label{25}\tag{25}$$ | ||
| - | |||
| - | The actual input common mode voltage is: | ||
| - | |||
| - | |||
| - | The driver gain is: | ||
| - | $$G_{drv}=\frac{V_{OUTdiff}}{V_{BUFF}}=\frac{R_{11}}{R_{12}}=\frac{R_{19}}{R_{14}}=1.27\label{26}\tag{26}$$ | ||
| - | |||
| - | The output divider gain: | ||
| - | $$G_{div}=\frac{V_{ADCdiff}}{V_{OUTdiff}}=\frac{R_{16}}{R_{13}+R_{16}}=\frac{R_{17}}{R_{15}+R_{17}}=0.746\label{27}\tag{27}$$ | ||
| - | |||
| - | The nominal Driver input voltage range is: | ||
| - | $$-1V< | ||
| - | |||
| - | The nominal Driver output voltage range is: | ||
| - | $$-1.27V< | ||
| - | |||
| - | With a unity common mode gain, the driver output common mode voltage is: | ||
| - | $$V_{CMOUT}=(V_{OUT+}+V_{OUT-})/ | ||
| - | |||
| - | The nominal Buffer output single ended voltage range is: | ||
| - | $$V_{CMOUT}-V_{OUT\; | ||
| - | |||
| - | The maximum nominal driver single ended current is: | ||
| - | $$I_{OUT\; | ||
| - | |||
| - | which is below the data sheet limit of 5mA, for covering the driver single ended voltage range above. | ||
| - | |||
| - | For passing at the ADC input, the voltages above are multiplied by the resistive divider gain of G< | ||
| - | |||
| - | The nominal differential ADC input voltage range is: | ||
| - | |||
| - | $$-1V< | ||
| - | |||
| - | The output divider common mode voltage is close to the recommended 0.9V: | ||
| - | |||
| - | $$V_{CMADC}=(V_{ADCP}+V_{ADCN})/ | ||
| - | |||
| - | The ADC input single ended voltage range is: | ||
| - | |||
| - | $$0.395V< | ||
| - | |||
| - | For the ADC input protection, the maximum driver single ended voltage should be considered. The driver amplifier datasheet only specifies the linear output voltage range. There is no information about the worst case saturated output voltages. Based on the data sheet and measurements, | ||
| - | |||
| - | $$V_{OUT\; | ||
| - | |||
| - | Resulting a stress value at the ADC input: | ||
| - | |||
| - | $$V_{ADC\; | ||
| - | |||
| - | which is less than the allowed voltage at the ADC input = 2.1V. | ||
| - | |||
| - | ---- | ||
| - | |||
| - | ==== 2.5. Scope ADC ==== | ||
| - | |||
| - | The Zmod ADC uses a dual channel, high speed, low power, 14-bit, 105MS/s ADC (Analog part number [[http:// | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | The important features of AD9648: | ||
| - | * SNR = 74.5dBFS @70 MHz | ||
| - | * SFDR =91dBc @70 MHz | ||
| - | * Low power: 78mW/ | ||
| - | * Differential analog input with 650 MHz bandwidth | ||
| - | * IF sampling frequencies to 200 MHz | ||
| - | * On-chip voltage reference and sample-and-hold circuit | ||
| - | * 2 V p-p differential analog input | ||
| - | * DNL = ±0.35 LSB | ||
| - | * Serial port control options | ||
| - | * Offset binary, gray code, or two's complement data format | ||
| - | * Optional clock duty cycle stabilizer | ||
| - | * Integer 1-to-8 input clock divider | ||
| - | * Data output multiplex option | ||
| - | * Built-in selectable digital test pattern generation | ||
| - | * Energy-saving power-down modes | ||
| - | * Data clock out with programmable clock and data alignment | ||
| - | |||
| - | The differential inputs are driven via a low-pass filter comprised of C114 together with R13, R15, R16, R17 in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by 4 to operate the ADC at a constant 100 MHz sampling rate. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage. | ||
| - | |||
| - | The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8V by the SYZYGY™ voltage V< | ||
| - | |||
| - | The multiplexed mode is used, to combine the two channels on a single data bus and minimize the number of used FPGA pins. CLKOUT_SC is provided to the FPGA for synchronizing data. | ||
| - | ---- | ||
| - | |||
| - | ==== 2.6. Scope Signal Scaling ==== | ||
| - | |||
| - | |||
| - | Combining Gain equations \ref{2}, \ref{4}, \ref{20}, \ref{26}, and \ref{27} from previous chapters, the total scope gains are: | ||
| - | |||
| - | $$Low \; gain = \frac{V_{ADC\; | ||
| - | $$High \; gain = \frac{V_{ADC\; | ||
| - | |||
| - | Considering the ADC input voltage range shown in \ref{33}: | ||
| - | |||
| - | $$at \; low \; gain: -26.3V< | ||
| - | $$at \; high \; gain: -1.1V< | ||
| - | |||
| - | To cover component value tolerances and to allow software calibration, | ||
| - | |||
| - | $$at \; low \; gain: -25V< | ||
| - | $$at \; high \; gain: -1V< | ||
| - | |||
| - | With the 14-bit ADC, the absolute resolution of the scope is: | ||
| - | |||
| - | $$at \; low \; gain: \frac{52.6V}{2^{14}}=3.21mV\label{43}\tag{43}$$ | ||
| - | $$at \; high \; gain: \frac{2.12V}{2^{14}}=0.13mV\label{44}\tag{44}$$ | ||
| - | |||
| - | For V< | ||
| - | |||
| - | $$V_{in} = \frac{N \cdot Range \cdot (1+CG)}{2^{13}} + CA \label{45}\tag{45}$$ | ||
| - | |||
| - | were: | ||
| - | * N = the 14 bit, 2's complement integer number returned by the ADC | ||
| - | * V< | ||
| - | * CA = calibration Additive constant (for the appropriate channel and gain; see [[reference: | ||
| - | * CG = calibration Gain constant (for the appropriate channel and gain; see [[reference: | ||
| - | * Range= the ideal Range of the Scope input stage (approximation of the values in equation \ref{40}): | ||
| - | * 1.086 (for low range: ±1V) or | ||
| - | * 26.25 (for high range: ±25V) | ||
| - | |||
| - | ---- | ||
| - | ==== 2.7 Scope Spectral Characteristics ==== | ||
| - | |||
| - | [[reference: | ||
| - | The signal swept from 800kHz to 80MHz. The effective values of the input and output signals were recorded for each frequency. The measurements were furter processesd to display the input stage frequency characteristics, | ||
| - | |||
| - | For both scales, the 3dB bandwidth is 70MHz+. The 0.5dB bandwidth is 30MHz and the 0.1dB bandwidth is 20MHz. | ||
| - | |||
| - | The standard -3dB bandwidth definition is derived from filter theory. At cutout frequency, the scope attenuates the spectral components by 0.707, assuming an error of ~30%, way too high for a measuring instrument. The bandwidth with a specified flatness is useful to better define the scope spectral performances. The Zmod ADC exhibits 30MHz+ @ 0.5dB, meaning that a 30 MHz sinusoidal signal is shown with a flatness error of a max 5.6%. 20MHz @ 0.1dB means that a 5 MHz sinusoidal signal is shown with a flatness error of a max 1.1%. | ||
| - | |||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | ===== 3. MCU ===== | ||
| - | |||
| - | The [[https:// | ||
| - | |||
| - | The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as " | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | * Program Memory Type: Flash | ||
| - | * Program Memory Size (KB): 4 | ||
| - | * CPU Speed (MIPS/ | ||
| - | * SRAM Bytes: 256 | ||
| - | * Data EEPROM/HEF (bytes): 256 | ||
| - | * Digital Communication Peripherals: | ||
| - | * Capture/ | ||
| - | * Timers: 1 x 8-bit, 1 x 16-bit | ||
| - | * Number of Comparators: | ||
| - | * Temperature Range (C): -40 to 85 | ||
| - | * Operating Voltage Range (V): 1.8 to 5.5 | ||
| - | * Pin Count: 14 | ||
| - | * Low Power: Yes | ||
| - | |||
| - | // | ||
| - | |||
| - | ^ Address | ||
| - | | 0x8000 - 0x80FF | ||
| - | | 0x8100 - 0x817F | ||
| - | | 0x8180 - 0x83FF | ||
| - | ==== 3.1. SYZYGY™ DNA ==== | ||
| - | |||
| - | The Zmod ADC is compliant with [[https:// | ||
| - | |||
| - | // | ||
| - | |||
| - | ^ Contents | ||
| - | |DNA full data length | ||
| - | |DNA header length | ||
| - | |SYZYGY DNA major version | ||
| - | |SYZYGY DNA minor version | ||
| - | |Required SYZYGY DNA major version | ||
| - | |Required SYZYGY DNA minor version | ||
| - | |Maximum operating 5V load (mA) | ||
| - | |Maximum operating 3.3V load (mA) | ||
| - | |Maximum VIO load (mA) |uint16 |2 |270 |0x800C | ||
| - | |Attribute flags |uint16 |2 |0 |0x800E | ||
| - | |Minimum operating VIO (10 mV steps)|uint16 |2 |180 |0x8010 | ||
| - | |Maximum operating VIO (10 mV steps)|uint16 |2 |180 |0x8012 | ||
| - | |Minimum operating VIO (10 mV steps)|uint16 |2 |170 |0x8014 | ||
| - | |Maximum operating VIO (10 mV steps)|uint16 |2 |190 |0x8016 | ||
| - | |Minimum operating VIO (10 mV steps)|uint16 |2 |0 |0x8018 | ||
| - | |Maximum operating VIO (10 mV steps)|uint16 |2 |0 |0x801A | ||
| - | |Minimum operating VIO (10 mV steps)|uint16 |2 |0 |0x801C | ||
| - | |Maximum operating VIO (10 mV steps)|uint16 |2 |0 |0x801E | ||
| - | |Manufacturer name length | ||
| - | |Product name length | ||
| - | |Product model / Part number length |uint8 | ||
| - | |Product version / revision length | ||
| - | |Serial number length | ||
| - | |RESERVED | ||
| - | |CRC-16 (most significant byte) | ||
| - | |CRC-16 (least significant byte) |uint8 | ||
| - | | END DATA HEADER | ||
| - | |Manufacturer name |string |12 | ||
| - | |Product name | ||
| - | |Product model / Part number | ||
| - | |Product version / revision | ||
| - | |Serial number | ||
| - | |||
| - | ==== 3.2. Calibration Memory ==== | ||
| - | |||
| - | The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, | ||
| - | |||
| - | * 0.1% resistors and 1% capacitors in all the critical analog signal paths | ||
| - | * Capacitive trimmers for balancing the Scope Input Divider and Gain Selection | ||
| - | * No other mechanical trimmers (as these are big, expensive, unreliable and affected by vibrations, aging, and temperature drifts) | ||
| - | * Software calibration, | ||
| - | * User software calibration, | ||
| - | |||
| - | A software calibration is performed on each device as a part of the manufacturing test. Reference signals are connected to the Scope inputs. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Zmod ADC device, both as Factory Calibration Data and User Calibration Data. The WaveForms software allows the user performing an in-house calibration and overwrite the User Calibration Data. Returning to Factory Calibration is always possible. | ||
| - | |||
| - | The Software reads the calibration parameters from the Zmod ADC MCU via the I2C bus and uses them to correct the acquired signals. | ||
| - | The structure of the calibration data is shown below: | ||
| - | |||
| - | // | ||
| - | ^ Heading 1 | ** Name ** ^ Size (Bytes) | ||
| - | | Magic ID | ||
| - | | Calibration Time | ||
| - | | Channel 1 LG Gain | CG | 4 | ||
| - | | Channel 1 LG Offset | ||
| - | | Channel 1 HG Gain | CG | 4 | ||
| - | | Channel 1 HG Offset | ||
| - | | Channel 2 LG Gain | CG | 4 | ||
| - | | Channel 2 LG Offset | ||
| - | | Channel 2 HG Gain | CG | 4 | ||
| - | | Channel 2 HG Offset | ||
| - | | Reserved Area | | ||
| - | | Log | | ||
| - | | CRC | | ||
| - | |||
| - | |||
| - | // | ||
| - | |||
| - | ^ | ||
| - | | 0x7000 - 0x707F | ||
| - | | 0x7080 - 0x70FF | ||
| - | |||
| - | At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C. To re-enable the write protection one has to write a any other number to the magic address. | ||
| - | |||
| - | // | ||
| - | ^ Magic Number | ||
| - | | 0xD2 | ||
| - | |||
| - | |||
| - | ---- | ||
| - | |||
| - | |||
| - | ===== 4. Power Supplies and Control ===== | ||
| - | |||
| - | This block includes the internal power supplies. | ||
| - | |||
| - | The Zmod ADC gets the digital rails from the carrier board, via the SYZYGY connector: | ||
| - | |||
| - | * VCC5V0 - used for relays and analog supplies | ||
| - | * VCC3V3 - used for the MCU and analog supplies | ||
| - | * Vadj = 1.8V - used for the ADC digital rail | ||
| - | |||
| - | |||
| - | The internal analog rails sequence is: | ||
| - | |||
| - | * AVCC1V8 - ADC analog rail | ||
| - | * AVCC3V0 - ADC driver | ||
| - | * AVCC-2V5, AVCC4V5 - Scope buffer, reference voltage | ||
| - | |||
| - | |||
| - | |||
| - | ==== 4.1. AVCC1V8 ==== | ||
| - | |||
| - | The analog supply AVCC1V8 is built from VCC5V0 using IC21, an [[http:// | ||
| - | |||
| - | * Input voltage: 2.3 V to 5.5 V | ||
| - | * Peak efficiency: 95% | ||
| - | * 3 MHz fixed frequency operation | ||
| - | * Typical quiescent current: 24 μA | ||
| - | * Very small solution size | ||
| - | * 6-lead, 1 mm × 1.5 mm WLCSP package | ||
| - | * Fast load and line transient response | ||
| - | * 100% duty cycle low dropout mode | ||
| - | * Internal synchronous rectifier, compensation, | ||
| - | * Current overload and thermal shutdown protections | ||
| - | * Ultra-low shutdown current: 0.2 μA (typical) | ||
| - | * Forced PWM and automatic PWM/PSM modes | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | ==== 4.2. AVCC3V0 ==== | ||
| - | |||
| - | The analog supply AVCC3V0 is built from VCC3V3 using IC22, an [[https:// | ||
| - | |||
| - | * Input voltage supply range: 2.3 V to 5.5 V | ||
| - | * 300 mA maximum output current | ||
| - | * Fixed and adjustable output voltage versions | ||
| - | * Very low dropout voltage: 85 mV at 300 mA load | ||
| - | * Low quiescent current: 45 µA at no load | ||
| - | * Low shutdown current: <1 µA | ||
| - | * Initial accuracy: ±1% accuracy | ||
| - | * Up to 31 fixed-output voltage options available from | ||
| - | * 1.75 V to 3.3 V | ||
| - | * Adjustable-output voltage range | ||
| - | * 0.8 V to 5.0 V (ADP123) | ||
| - | * Excellent PSRR performance: | ||
| - | * Excellent load/line transient response | ||
| - | * Optimized for small 1.0 μF ceramic capacitors | ||
| - | * Current limit and thermal overload protection | ||
| - | * Logic controlled enable | ||
| - | * Compact packages: 5-lead TSOT and 6-lead 2 mm × 2 mm LFCSP | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | ==== 4.3. AVCC4V5 ==== | ||
| - | |||
| - | The analog supply AVCC4V5 is built from VCC5V0 using IC19, an [[https:// | ||
| - | |||
| - | * Input voltage supply range: 2.3 V to 5.5 V | ||
| - | * 300 mA maximum output current | ||
| - | * Fixed and adjustable output voltage versions | ||
| - | * Very low dropout voltage: 85 mV at 300 mA load | ||
| - | * Low quiescent current: 45 µA at no load | ||
| - | * Low shutdown current: <1 µA | ||
| - | * Initial accuracy: ±1% accuracy | ||
| - | * Up to 31 fixed-output voltage options available from | ||
| - | * 1.75 V to 3.3 V | ||
| - | * Adjustable-output voltage range | ||
| - | * 0.8 V to 5.0 V (ADP123) | ||
| - | * Excellent PSRR performance: | ||
| - | * Excellent load/line transient response | ||
| - | * Optimized for small 1.0 μF ceramic capacitors | ||
| - | * Current limit and thermal overload protection | ||
| - | * Logic controlled enable | ||
| - | * Compact packages: 5-lead TSOT and 6-lead 2 mm × 2 mm LFCSP | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | ==== 4.4. AVCC-2V5 ==== | ||
| - | |||
| - | The AVCC-2V5 analog power supply is implemented with the [[http:// | ||
| - | |||
| - | * 1.2 A maximum load current | ||
| - | * ±2% output accuracy over temperature range | ||
| - | * 1.4 MHz switching frequency | ||
| - | * High efficiency up to 91% | ||
| - | * Current-mode control architecture | ||
| - | * Output voltage from 0.8 V to 0.85 × VIN | ||
| - | * Automatic PFM/PWM mode switching | ||
| - | * Integrated high-side MOSFET | ||
| - | * Internal compensation and soft start | ||
| - | * Undervoltage lockout (UVLO), Overcurrent protection (OCP) and thermal shutdown (TSD) | ||
| - | * Available in ultrasmall, 6-lead TSOT package | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | |||
| - | ===== 5. The SYZYGY™ Connector ===== | ||
| - | |||
| - | The SYZYGY™ connector in provides the interface with the carrier board. The used signals are: | ||
| - | * Power rails | ||
| - | * VCC5V0 | ||
| - | * VCC3V3 | ||
| - | * VADJ - needs to be set by the carier board to 1.8V | ||
| - | * GND | ||
| - | * Shield | ||
| - | * SYZYGY™ I2C bus: | ||
| - | * MCU_SCLUSCK | ||
| - | * MCU_SDA_MOSI | ||
| - | * ADC differential input clock | ||
| - | * CLKIN_ADC_P | ||
| - | * CLKIN_ADC_N | ||
| - | * ADC single ended output clock: | ||
| - | * CLKOUT_ADC (coupled with GND in the differential P2C pair) | ||
| - | * R_GA for geographical address identification | ||
| - | * SYNC_ADC for ADC internal clock divider synchronization | ||
| - | * ADC data bus: DOUT_ADC_0...13 | ||
| - | * ADC SPI bus: | ||
| - | * CS_SC1n | ||
| - | * SCLK_SC | ||
| - | * SDIO_SC | ||
| - | * relay control | ||
| - | * SCx_yy_z | ||
| - | |||
| - | {{: | ||
| - | // | ||
| - | |||
| - | ===== 6. The SYZYGY™ compatibility table ===== | ||
| - | |||
| - | // | ||
| - | ^ Parameter | ||
| - | | Maximum 5V supply current | ||
| - | | Maximum 3.3V supply current | ||
| - | | VIO supply voltage | ||
| - | | Maximum VIO supply current | ||
| - | | Total number of I/O | 28 | | ||
| - | | Number of differential I/O pairs | 0 | | ||
| - | | Width | Single | ||
| - | |||
| - | |||
| - | |||
| - | **Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania** | ||