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reference:instrumentation:digital-discovery:reference-manual [2019/12/02 18:51]
Arthur Brown
reference:instrumentation:digital-discovery:reference-manual [2020/07/09 20:26] (current)
Arthur Brown
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 ====== Digital Discovery Reference Manual ====== ====== Digital Discovery Reference Manual ======
  
-The Digilent Digital Discovery™ is a combined logic analyzer and pattern generator instrument that was created to be the ultimate embedded development companion. The Digital Discovery was designed to optimize channels, speed, and portability. The small form factor facilitates easy storage and provides a whole suite of advanced features to allow you to debug, visualize, and simulate ​digital signals for most embedded projects. The digital inputs and outputs can be connected to a circuit using simple wire probes or breadboard wires; alternatively,​ the Digital Discovery High Speed Adapter and impedance-matched probes can be used to connect and utilize the inputs and outputs for more advanced projects. The Digital Discovery is driven by the free [[https://​reference.digilentinc.com/​reference/​software/​waveforms/​waveforms-3/​start|WaveForms]] (3.5.4 or later) software and can be configured to be any of the instruments below: ​+The Digilent Digital Discovery™ is a combined logic analyzer and pattern generator instrument that was created to be the ultimate embedded development companion. The Digital Discovery was designed to optimize channels, speed, and portability. The small form factor facilitates easy storage and provides a whole suite of advanced features to allow you to debug, visualize, and stimulate ​digital signals for most embedded projects. The digital inputs and outputs can be connected to a circuit using simple wire probes or breadboard wires; alternatively,​ the Digital Discovery High Speed Adapter and impedance-matched probes can be used to connect and utilize the inputs and outputs for more advanced projects. The Digital Discovery is driven by the free [[https://​reference.digilentinc.com/​reference/​software/​waveforms/​waveforms-3/​start|WaveForms]] (3.5.4 or later) software and can be configured to be any of the instruments below: ​
  
   * 24-channel digital logic analyzer (1.2…3.3V CMOS, up to 800MS/​s(with the High Speed Adapter))   * 24-channel digital logic analyzer (1.2…3.3V CMOS, up to 800MS/​s(with the High Speed Adapter))
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 The I/O Level Translators block includes: The I/O Level Translators block includes:
 - Input protection: series PTC (33Ω, positive thermal coefficient thermistor) and parallel ESD/​overvoltage diodes to 5.2V and GND. - Input protection: series PTC (33Ω, positive thermal coefficient thermistor) and parallel ESD/​overvoltage diodes to 5.2V and GND.
-- Voltage level translators,​ SN74CBT3384C. When DIO_USR signals are driven by the DUT, the voltage at the FPGA pins is limited at VCCIO_SW-1V = 3.3V. When the FPGA drives DIO_USR signals, they pass unlimited ​trough ​the low impedance SN74CBT3384C buffer.+- Voltage level translators,​ SN74CBT3384C. When DIO_USR signals are driven by the DUT, the voltage at the FPGA pins is limited at VCCIO_SW-1V = 3.3V. When the FPGA drives DIO_USR signals, they pass unlimited ​through ​the low impedance SN74CBT3384C buffer.
 - Pull resistors: 10k, individually settable as Pull-Up, Pull-Down or High-Z. This is done with a second FPGA pin associated to each DIO, which can be driven High, Low or HiZ. The Pull-Up voltage is VCCIO_PROG. - Pull resistors: 10k, individually settable as Pull-Up, Pull-Down or High-Z. This is done with a second FPGA pin associated to each DIO, which can be driven High, Low or HiZ. The Pull-Up voltage is VCCIO_PROG.
 - DIO_FPGA pin: the bank supply voltage is VCCIO_PROG>​ The WaveForms software can set VCCIO_PROG from 1.2 to 3.3V. The FPGA input threshold level is about 45% of VCCIO_PROG. The output strength can be set from 2mA to 16mA. The output slew rate can be set as: Quiet, Slow or Fast. - DIO_FPGA pin: the bank supply voltage is VCCIO_PROG>​ The WaveForms software can set VCCIO_PROG from 1.2 to 3.3V. The FPGA input threshold level is about 45% of VCCIO_PROG. The output strength can be set from 2mA to 16mA. The output slew rate can be set as: Quiet, Slow or Fast.
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   * 24 high-speed input channels (DIN0…23),​ accessible through one 2x16 connector, used with the Logic Analyzer in WaveForms (560kΩ||10pF)   * 24 high-speed input channels (DIN0…23),​ accessible through one 2x16 connector, used with the Logic Analyzer in WaveForms (560kΩ||10pF)
-  * 16 digital I/Os (DIO24…39) arranged in two Pmod-style (2x6) connectors, used with the Logic Analyzer in WaveForms ((The 16 DIO lines are primarily intended for the Pattern Generator, protocol controllers and Static IO instruments. For user convenience,​ some or all of them can be used by the Logic Analyzer also (see footnote 2). However, DIO input circuitry is different compared to DIN. Even more, when driving a DIO pin with the Pattern Generator and reading it back with the Logic Analyzer, the signal is read at the FPGA pin and does not propagate ​trough ​the external DIO circuitry. Consequently,​ when combining DIN and DIO pins in the Logic Analyzer, misalignments can be observed, at high acquisition rate.)) ​+  * 16 digital I/Os (DIO24…39) arranged in two Pmod-style (2x6) connectors, used with the Logic Analyzer in WaveForms ((The 16 DIO lines are primarily intended for the Pattern Generator, protocol controllers and Static IO instruments. For user convenience,​ some or all of them can be used by the Logic Analyzer also (see footnote 2). However, DIO input circuitry is different compared to DIN. Even more, when driving a DIO pin with the Pattern Generator and reading it back with the Logic Analyzer, the signal is read at the FPGA pin and does not propagate ​through ​the external DIO circuitry. Consequently,​ when combining DIN and DIO pins in the Logic Analyzer, misalignments can be observed, at high acquisition rate.)) ​
   * 800MSps input sample rate when using maximum 8 inputs (and the High Speed Adapter), 400 MSps with maximum 16 inputs (with the High Speed Adapter), 200MSps and lower with maximum 32 inputs ((Available combinations in WaveForms:   * 800MSps input sample rate when using maximum 8 inputs (and the High Speed Adapter), 400 MSps with maximum 16 inputs (with the High Speed Adapter), 200MSps and lower with maximum 32 inputs ((Available combinations in WaveForms:
   - 200MHz, DIN0…23, DIO24…31   - 200MHz, DIN0…23, DIO24…31
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   * 16 digital I/Os arranged in two Pmod-style (2x6) connectors.   * 16 digital I/Os arranged in two Pmod-style (2x6) connectors.
-  * Each of the 16 pins can be configured for input (Logic analyzer) or set as output ((The 16 DIO lines are primarily intended for the Pattern Generator, protocol controllers and Static IO instruments. For user convenience,​ some or all of them can be used by the Logic Analyzer also (see footnote 2). However, DIO input circuitry is different compared to DIN. Even more, when driving a DIO pin with the Pattern Generator and reading it back with the Logic Analyzer, the signal is read at the FPGA pin and does not propagate ​trough ​the external DIO circuitry. Consequently,​ when combining DIN and DIO pins in the Logic Analyzer, misalignments can be observed, at high acquisition rate.)).+  * Each of the 16 pins can be configured for input (Logic analyzer) or set as output ((The 16 DIO lines are primarily intended for the Pattern Generator, protocol controllers and Static IO instruments. For user convenience,​ some or all of them can be used by the Logic Analyzer also (see footnote 2). However, DIO input circuitry is different compared to DIN. Even more, when driving a DIO pin with the Pattern Generator and reading it back with the Logic Analyzer, the signal is read at the FPGA pin and does not propagate ​through ​the external DIO circuitry. Consequently,​ when combining DIN and DIO pins in the Logic Analyzer, misalignments can be observed, at high acquisition rate.)).
   * Algorithmic pattern generator (no buffers used) ((Real time implemented in the FPGA configuration.))   * Algorithmic pattern generator (no buffers used) ((Real time implemented in the FPGA configuration.))
   * Custom pattern buffer/ch.: 32Ksamples   * Custom pattern buffer/ch.: 32Ksamples