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reference:add-ons:fmc-pcam-adapter:reference-manual [2019/04/09 16:55]
Elod Gyorgy [1.5. I2C Multiplexer] renamed to switch for consistency
reference:add-ons:fmc-pcam-adapter:reference-manual [2019/04/17 13:26] (current)
Elod Gyorgy Added compatibilty note regarding FPGA architectures
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   * The carrier card might have either the low-pin count or the high-pin count FMC female connector. However, not all pins are required to be wired. Compare the carrier card FMC pin-out against the pin-out from chapter 1.4 below.   * The carrier card might have either the low-pin count or the high-pin count FMC female connector. However, not all pins are required to be wired. Compare the carrier card FMC pin-out against the pin-out from chapter 1.4 below.
  
 +==== FPGA I/O Architecture Compatibility ====
 +Receiving several independent source-synchronous high-speed interfaces in the FPGA is no easy feat due to I/O and clocking restrictions of the FPGA architecture. The VITA 57.1 specs are not granular enough for the requirements of today'​s high-speed I/O architectures. Therefore, not all carrier cards will be able to support all ports of the FMC Pcam Adapter simultaneously. Some of the requirements are:
 +  * Clock inputs are mapped to LA00, LA01, LA17, and LA18. Verify that the carrier board maps these to clock-capable input pins.
 +  * Each clock has two data lanes associated with it. Verify that the clock signal can be routed to I/O primitives sampling the data lanes. On some architectures the clock and its data lanes must be mapped to the same bank.
 +  * Two ports are mapped to LA00-LA16, and the other two mapped to LA17-LA33. Usually, carrier cards split these groups into separate banks. Therefore, each bank must support two ports at once. This puts a considerable constraint on the resources available in each bank. Clock buffers, PLLs and high-speed de-serialization primitives must be capable of receiving two independent D-PHY interfaces. The UltraScale architecture in particular has a very restrictive clock/​strobe propagation mechanism. The side-effect of propagation is that some pins are made unavailable for other purposes including other Pcam ports.
  
 +Digilent recommends implementing an RTL design with the desired number of D-PHY interfaces constrained to the pinout of the carrier card to be used for development before committing to the FMC Pcam Adapter.
  
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