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reference:add-ons:fmc-pcam-adapter:reference-manual [2019/04/17 13:26]
Elod Gyorgy Added compatibilty note regarding FPGA architectures
reference:add-ons:fmc-pcam-adapter:reference-manual [2019/05/08 14:56] (current)
Elod Gyorgy [FPGA I/O Architecture Compatibility] Added note on unavailability of some pins, even non-FMC, due to propagation
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 ====== FMC Pcam Adapter Reference Manual ====== ====== FMC Pcam Adapter Reference Manual ======
  
-===== Revision History =====+The FMC Pcam Adapter is an FMC mezzanine (peripheral) board allowing interfacing up to four Pcam camera modules to field-programmable gate array (FPGA) based systems. It extends the capabilities of development platforms to enable multi-camera video applications.
  
-Created April 9, 2019+{{Digilent Image Gallery  
 +| image = {{ :​reference:​add-ons:​fmc-pcam-adapter:​fmc-pcam-adapter-obl-1000.png?​direct |}} 
 +| image = {{ :​reference:​add-ons:​fmc-pcam-adapter:​fmc-pcam-adapter-top-1000.png?​direct |}} 
 +}}
  
-This manual applies to REV C.0 of both variants (Dual and Quad) of the board.+===== Features =====
  
-===== Overview ===== 
-The FMC Pcam Adapter is an FMC mezzanine (peripheral) board allowing interfacing up to four Pcam camera modules to field-programmable gate array (FPGA) based systems. It extends the capabilities of development platforms to enable multi-camera video applications. 
-There are two variants available: Dual and Quad, based on the number of Pcam connectors and related circuitry. Dual makes connecting two Pcam 5C (or similar) possible, with Quad increasing that to four. 
- 
-Features include: 
   * Two/Four Pcam system-side connectors   * Two/Four Pcam system-side connectors
   * Level translators from MIPI D-PHY to LVDS and LVCMOS   * Level translators from MIPI D-PHY to LVDS and LVCMOS
   * Male FMC LPC connector for digital signals   * Male FMC LPC connector for digital signals
-  * Compatible with a wide range of VADJ voltages (1.8V – 3.3V)+  * Compatible with a wide range of V<​sub>​ADJ</​sub> ​voltages (1.8V – 3.3V) 
 + 
 +===== Purchasing Options ===== 
 + 
 +There are two variants available: Dual and Quad, based on the number of Pcam connectors and related circuitry. Dual makes connecting two Pcam 5C (or similar) possible, with Quad increasing that to four. 
 + 
 +===== Revision History ===== 
 + 
 +Created April 9, 2019 
 + 
 +This manual applies to REV C.0 of both variants (Dual and Quad) of the board.
  
 ===== Carrier Card Compatibility ===== ===== Carrier Card Compatibility =====
 As with any FMC mezzanine module, there are some compatibility requirements. These must be evaluated before connecting and powering the module. As with any FMC mezzanine module, there are some compatibility requirements. These must be evaluated before connecting and powering the module.
-  * Supported ​VADJ voltage range is 1.8 V - 3.3 V. The voltage is controlled by the carrier card.+  * Supported ​V<​sub>​ADJ</​sub> ​voltage range is 1.8 V - 3.3 V. The voltage is controlled by the carrier card.
   * The carrier card must be capable of providing enough current. See [[reference:​add-ons:​fmc-pcam-adapter:​reference-manual#​power_supplies|Power Supplies]].   * The carrier card must be capable of providing enough current. See [[reference:​add-ons:​fmc-pcam-adapter:​reference-manual#​power_supplies|Power Supplies]].
-  * Must use I/O standards compatible with the voltage levels of the digital outputs, and the chosen ​VADJ. For example, LVDS_25 and LVCMOS25 with a VADJ of 2.5V. +  * Must use I/O standards compatible with the voltage levels of the digital outputs, and the chosen ​V<​sub>​ADJ</​sub>​. For example, LVDS_25 and LVCMOS25 with a V<​sub>​ADJ</​sub> ​of 2.5V. 
-  * Receiver signal termination for outputs is the responsibility of the carrier card. For example, DIFF_TERM can be used for LVDS_25 and a VADJ of 2.5V.+  * Receiver signal termination for outputs is the responsibility of the carrier card. For example, DIFF_TERM can be used for LVDS_25 and a V<​sub>​ADJ</​sub> ​of 2.5V.
   * The carrier card might have either the low-pin count or the high-pin count FMC female connector. However, not all pins are required to be wired. Compare the carrier card FMC pin-out against the pin-out from chapter 1.4 below.   * The carrier card might have either the low-pin count or the high-pin count FMC female connector. However, not all pins are required to be wired. Compare the carrier card FMC pin-out against the pin-out from chapter 1.4 below.
- 
 ==== FPGA I/O Architecture Compatibility ==== ==== FPGA I/O Architecture Compatibility ====
-Receiving several independent source-synchronous high-speed interfaces in the FPGA is no easy feat due to I/O and clocking restrictions ​of the FPGA architecture. The VITA 57.1 specs are not granular enough for the requirements of today'​s high-speed I/O architectures. Therefore, not all carrier cards will be able to support all ports of the FMC Pcam Adapter simultaneously. Some of the requirements are:+Receiving several independent source-synchronous high-speed interfaces in the FPGA is no easy feat due to I/O and clocking restrictions ​specific to the FPGA architecture. The VITA 57.1 specs are not granular enough for the requirements of today'​s high-speed I/O architectures. Therefore, not all carrier cards will be able to support all ports of the FMC Pcam Adapter simultaneously. Some of the requirements are:
   * Clock inputs are mapped to LA00, LA01, LA17, and LA18. Verify that the carrier board maps these to clock-capable input pins.   * Clock inputs are mapped to LA00, LA01, LA17, and LA18. Verify that the carrier board maps these to clock-capable input pins.
   * Each clock has two data lanes associated with it. Verify that the clock signal can be routed to I/O primitives sampling the data lanes. On some architectures the clock and its data lanes must be mapped to the same bank.   * Each clock has two data lanes associated with it. Verify that the clock signal can be routed to I/O primitives sampling the data lanes. On some architectures the clock and its data lanes must be mapped to the same bank.
-  * Two ports are mapped to LA00-LA16, and the other two mapped to LA17-LA33. Usually, carrier cards split these groups into separate banks. Therefore, each bank must support two ports at once. This puts a considerable constraint on the resources available in each bank. Clock buffers, PLLs and high-speed de-serialization primitives must be capable of receiving two independent D-PHY interfaces. The UltraScale architecture in particular has a very restrictive clock/​strobe propagation mechanism. The side-effect of propagation is that some pins are made unavailable for other purposes including other Pcam ports.+  * Two ports are mapped to LA00-LA16, and the other two mapped to LA17-LA33. Usually, carrier cards split these groups into separate banks. Therefore, each bank must support two ports at once. This puts a considerable constraint on the resources available in each bank. Clock buffers, PLLs and high-speed de-serialization primitives must be capable of receiving two independent D-PHY interfaces. The UltraScale architecture in particular has a very restrictive clock/​strobe propagation mechanism. The side-effect of propagation is that some pins are made unavailable for other purposes including other Pcam ports. This might include pins unrelated to FMC, but mapped to the FMC bank.
  
 Digilent recommends implementing an RTL design with the desired number of D-PHY interfaces constrained to the pinout of the carrier card to be used for development before committing to the FMC Pcam Adapter. Digilent recommends implementing an RTL design with the desired number of D-PHY interfaces constrained to the pinout of the carrier card to be used for development before committing to the FMC Pcam Adapter.
 +
 +==== Compatibility Matrix ====
 +The table below lists carrier cards confirmed compatible by Digilent. Boards not listed can still be compatible, if the requirements above are met. Check back for updates as the list will be extended.
 +
 +^  Carrier Card  ^ Manufacturer ​ ^  FMC Port  ^ V<​sub>​ADJ</​sub> ​ ^ Simultaneous Pcam Port Usage              ||||
 +| :::            | :::           | :::        | :::              ^ A                             ^ B  ^ C  ^ D  ^
 +| ZedBoard ​      | Digilent ​     | J1 (LPC)   | 2.5 V            | ✔                             | ✔  | ✔  | ✔  |
 +//Table 1. Confirmed compatibility matrix.//
  
 ---- ----
 ====== 1. Functional Description ====== ====== 1. Functional Description ======
  
-The adapter board'​s main purpose is to translate the MIPI D-PHY input to LVDS/LVCMOS outputs that are supported on most FPGAs. It also translates the 3.3V control signals of the Pcam to the adjustable I/O voltage powering the FMC bank, VADJ. Therefore, compatibility is extended to boards with FPGAs that have only low-voltage I/O banks (%%<=%% 1.8V).+The adapter board'​s main purpose is to translate the MIPI D-PHY input to LVDS/LVCMOS outputs that are supported on most FPGAs. It also translates the 3.3V control signals of the Pcam to the adjustable I/O voltage powering the FMC bank, V<​sub>​ADJ</​sub>​. Therefore, compatibility is extended to boards with FPGAs that have only low-voltage I/O banks (%%<=%% 1.8V).
 ==== 1.1. Pcam ports ==== ==== 1.1. Pcam ports ====
 The Pcam ports are system-side,​ 15-pin, bottom-load,​ top-contact FFC connectors. Pcam modules are connected using the flexible-foil cable provided with them. The correct cable orientation is with the contact pads facing away from the board. Please see Figure 2 below for details. The Pcam ports are system-side,​ 15-pin, bottom-load,​ top-contact FFC connectors. Pcam modules are connected using the flexible-foil cable provided with them. The correct cable orientation is with the contact pads facing away from the board. Please see Figure 2 below for details.
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 ==== 1.2. Level translators ==== ==== 1.2. Level translators ====
  
-There are two types of level translators onboard: for control signals and for MIPI D-PHY inputs. Both translate between voltage levels of the FMC bank supplied by VADJ and a second power domain.+There are two types of level translators onboard: for control signals and for MIPI D-PHY inputs. Both translate between voltage levels of the FMC bank supplied by V<​sub>​ADJ</​sub> ​and a second power domain.
  
 === 1.2.1. Control signals === === 1.2.1. Control signals ===
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 The high-speed outputs are compliant with Xilinx LVDS_25 and LVDS standards. These standards have a typical input common-mode voltage of 1.2V for 100Ω transmission lines. It is important to mention that for LVDS high-speed lines, 100Ω differential termination is needed at the receiver, on the carrier board. The Xilinx LVDS_25 and LVDS standards offer the possibility of enabling differential termination internal to the FPGA (using DIFF_TERM = TRUE constraint);​ for this the constraint file has to be modified accordingly. If the carrier board has external differential termination on these lines, the DIFF_TERM constraint is not needed. The high-speed outputs are compliant with Xilinx LVDS_25 and LVDS standards. These standards have a typical input common-mode voltage of 1.2V for 100Ω transmission lines. It is important to mention that for LVDS high-speed lines, 100Ω differential termination is needed at the receiver, on the carrier board. The Xilinx LVDS_25 and LVDS standards offer the possibility of enabling differential termination internal to the FPGA (using DIFF_TERM = TRUE constraint);​ for this the constraint file has to be modified accordingly. If the carrier board has external differential termination on these lines, the DIFF_TERM constraint is not needed.
  
-The low-power signals are compliant with the LVCMOS standard corresponding to the selected ​VADJ voltage level. ​+The low-power signals are compliant with the LVCMOS standard corresponding to the selected ​V<​sub>​ADJ</​sub> ​voltage level. ​
  
 The DC characteristics for the high-speed outputs of the MC20901 IC are listed in the table below. ​ The DC characteristics for the high-speed outputs of the MC20901 IC are listed in the table below. ​
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 | 3P3VAUX ​    | IPMI FRU EEPROM, I2C multiplexer ​     | 20                                | 20    | | 3P3VAUX ​    | IPMI FRU EEPROM, I2C multiplexer ​     | 20                                | 20    |
 | 3P3V        | LDOs, Pcam VCC3V3, level translators ​ | 1000                              | 500   | | 3P3V        | LDOs, Pcam VCC3V3, level translators ​ | 1000                              | 500   |
-VADJ        | Level translators ​                    | 400                               | 200   |+V<​sub>​ADJ</​sub> ​       | Level translators ​                    | 400                               | 200   |
 //Table 6. Loads on FMC Power Rails// //Table 6. Loads on FMC Power Rails//
  
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 ==== 1.8.  FMC Support ==== ==== 1.8.  FMC Support ====
-The FMC Pcam Adapter uses a Samtec ASP-134604-01 low pin-count male connector as the main connector for digital signals. The board fully conforms to the VITA 57.1 specs. The connector supports the full range of 1.8V-3.3V bank supply voltages (VADJ). Check compatibility requirements above.+The FMC Pcam Adapter uses a Samtec ASP-134604-01 low pin-count male connector as the main connector for digital signals. The board fully conforms to the VITA 57.1 specs. The connector supports the full range of 1.8V-3.3V bank supply voltages (V<​sub>​ADJ</​sub>​). Check compatibility requirements above.
  
 I²C serves as the IPMI EEPROM, providing hardware definition information. For more information,​ consult the VITA 57.1 specs. I²C serves as the IPMI EEPROM, providing hardware definition information. For more information,​ consult the VITA 57.1 specs.
 +
 +{{tag>rm doc fmc-pcam-adapter}}