Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2552052
date_generatedTue Jul 9 16:15:16 2019 os_platformWIN64
product_versionVivado v2019.1 (64-bit) project_id46b6e2df37d74dba89e045d8fec53da6
project_iteration19 random_id5d069473bb775433b3992119d43e4bf1
registration_id176233316_1777514562_210653918_608 route_designTRUE
target_devicexc7s25 target_familyspartan7
target_packagecsga225 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-7800X CPU @ 3.50GHz cpu_speed3504 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_add_element=1 abstractcombinedpanel_remove_selected_elements=2 addsrcwizard_specify_hdl_netlist_block_design=1 basedialog_cancel=33
basedialog_no=1 basedialog_ok=58 basedialog_yes=27 boardchooser_board_table=1
cmdmsgdialog_ok=1 commandsinput_type_tcl_command_here=4 confirmsavetexteditsdialog_cancel=1 constraintschooserpanel_add_files=1
coretreetablepanel_core_tree_table=9 createsrcfiledialog_file_name=5 customizecoredialog_documentation=1 definemodulesdialog_define_modules_and_specify_io_ports=10
definemodulesdialog_entity_name=1 filesetpanel_file_set_panel_tree=111 floatingtopdialog_ignore_and_continue_with_invalid_top=1 flownavigatortreepanel_flow_navigator_tree=66
graphicalview_zoom_fit=4 graphicalview_zoom_in=6 hardwaretreepanel_hardware_tree_table=2 mainmenumgr_edit=2
mainmenumgr_file=4 mainmenumgr_project=1 msgtreepanel_discard_user_created_messages=3 msgtreepanel_message_severity=5
msgtreepanel_message_view_tree=23 msgview_critical_warnings=2 msgview_warning_messages=7 netlisttreeview_netlist_tree=7
pacommandnames_add_sources=6 pacommandnames_auto_connect_target=1 pacommandnames_auto_update_hier=12 pacommandnames_close_hardware_design=5
pacommandnames_message_window=1 pacommandnames_new_project=1 pacommandnames_open_hardware_manager=2 pacommandnames_reset_composite_file=2
pacommandnames_reset_run_to_previous_step=1 pacommandnames_set_as_top=3 pacommandnames_set_used_in_prop=1 pacommandnames_simulation_live_restart=1
pacommandnames_simulation_live_run=2 pacommandnames_simulation_relaunch=1 pacommandnames_simulation_run_behavioral=1 paviews_code=2
paviews_project_summary=12 programdebugtab_program_device=18 programdebugtab_refresh_device=1 programfpgadialog_program=20
programfpgadialog_specify_bitstream_file=1 programfpgadialog_specify_debug_probes_file=4 progressdialog_background=3 projectnamechooser_project_name=1
rdicommands_delete=1 rdiviews_waveform_viewer=5 settingsdialog_project_tree=1 simpleoutputproductdialog_generate_output_products_immediately=6
simpleoutputproductdialog_reset_output_products=2 simulationscopespanel_simulate_scope_table=1 srcchooserpanel_create_file=4 srcmenu_ip_documentation=9
srcmenu_ip_hierarchy=13 srcmenu_refresh_hierarchy=1 tclconsoleview_tcl_console_code_editor=4
java_command_handlers
addsources=7 autoconnecttarget=1 closedesign=5 coreview=3
customizecore=4 editdelete=4 editpaste=3 fliptoviewtaskimplementation=1
launchprogramfpga=22 managecompositetargets=2 newproject=1 openhardwaremanager=13
openrecenttarget=1 programdevice=6 recustomizecore=14 runbitgen=27
savefileproxyhandler=5 setsourceenabled=1 settopnode=3 showview=6
simulationrelaunch=1 simulationrestart=1 simulationrun=1 simulationrunfortime=2
toolssettings=1 viewtaskimplementation=1 viewtaskprogramanddebug=1 viewtaskprojectmanager=8
viewtaskrtlanalysis=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=5 export_simulation_ies=5
export_simulation_modelsim=5 export_simulation_questa=5 export_simulation_riviera=5 export_simulation_vcs=5
export_simulation_xsim=5 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=3 simulator_language=Mixed srcsetcount=4 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=3 totalsynthesisruns=3

unisim_transformation
post_unisim_transformation
bufg=2 fdre=29 gnd=5 ibuf=11
lut1=5 lut2=5 lut3=4 lut4=4
lut5=3 lut6=9 mmcme2_adv=1 muxf7=2
muxf8=1 obuf=11 vcc=4 xadc=1
pre_unisim_transformation
bufg=2 fdre=29 gnd=5 ibuf=11
lut1=5 lut2=5 lut3=4 lut4=4
lut5=3 lut6=9 mmcme2_adv=1 muxf7=2
muxf8=1 obuf=11 vcc=4 xadc=1

ip_statistics
clk_wiz_v6_0_3_0_0/1
clkin1_period=83.333 clkin2_period=10.0 clock_mgr_type=NA component_name=clk_wiz_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=false use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false
xadc_wiz_v3_3_6/1
channel_averaging=None component_name=xadc_wiz_0 core_container=false dclk_frequency=100
enable_axi=false enable_axi4stream=false enable_busy=true enable_convst=false
enable_convstclk=false enable_dclk=true enable_drp=true enable_eoc=true
enable_eos=true enable_vbram_alaram=false enable_vccaux_alaram=false enable_vccddro_alaram=false
enable_vccint_alaram=false enable_vccpaux_alaram=false enable_vccpint_alaram=false iptotal=1
ot_alaram=false sequencer_mode=on startup_channel_selection=contineous_sequence timing_mode=continuous
user_temp_alaram=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 rpbf-3=7

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-6=2

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.001612 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.061252
die=xc7s25csga225-1 dsp_output_toggle=12.500000 dynamic=0.111392 effective_thetaja=3.7
enable_probability=0.990000 family=spartan7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.004301 input_toggle=12.500000 junction_temp=25.6 (C)
logic=0.000040 mmcm=0.104125 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.172644 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=csga225 pct_clock_constrained=1.000000 pct_inputs_defined=9 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.000180 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=15.6 (C/W)
thetasa=46.2 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=3.7
user_junc_temp=25.6 (C) user_thetajb=15.6 (C/W) user_thetasa=46.2 (C/W) vccadc_dynamic_current=0.000800
vccadc_static_current=0.020000 vccadc_total_current=0.020800 vccadc_voltage=1.800000 vccaux_dynamic_current=0.057873
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.009462 vccaux_total_current=0.067336 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000098 vccbram_total_current=0.000098 vccbram_voltage=1.000000 vccint_dynamic_current=0.001800
vccint_static_current=0.004822 vccint_total_current=0.006622 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.001206
vcco33_static_current=0.001000 vcco33_total_current=0.002206 vcco33_voltage=3.300000 version=2019.1
xadc=0.001940

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=48 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=12 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=6 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=12 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=3 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=33.33
plle2_adv_available=3 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=80 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=45 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=90 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=45 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 fdre_functional_category=Flop & Latch fdre_used=37
ibuf_functional_category=IO ibuf_used=11 lut1_functional_category=LUT lut1_used=4
lut2_functional_category=LUT lut2_used=5 lut3_functional_category=LUT lut3_used=4
lut4_functional_category=LUT lut4_used=4 lut5_functional_category=LUT lut5_used=3
lut6_functional_category=LUT lut6_used=9 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
muxf7_functional_category=MuxFx muxf7_used=2 muxf8_functional_category=MuxFx muxf8_used=1
obuf_functional_category=IO obuf_used=11 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=7300 f7_muxes_fixed=0 f7_muxes_used=2 f7_muxes_util_percentage=0.03
f8_muxes_available=3650 f8_muxes_fixed=0 f8_muxes_used=1 f8_muxes_util_percentage=0.03
lut_as_logic_available=14600 lut_as_logic_fixed=0 lut_as_logic_used=23 lut_as_logic_util_percentage=0.16
lut_as_memory_available=5000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=29200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=37 register_as_flip_flop_util_percentage=0.13
register_as_latch_available=29200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=14600 slice_luts_fixed=0 slice_luts_used=23 slice_luts_util_percentage=0.16
slice_registers_available=29200 slice_registers_fixed=0 slice_registers_used=37 slice_registers_util_percentage=0.13
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=14600 lut_as_logic_fixed=0
lut_as_logic_used=23 lut_as_logic_util_percentage=0.16 lut_as_memory_available=5000 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=21 lut_in_front_of_the_register_is_used_fixed=21 lut_in_front_of_the_register_is_used_used=4
register_driven_from_outside_the_slice_fixed=4 register_driven_from_outside_the_slice_used=25 register_driven_from_within_the_slice_fixed=25 register_driven_from_within_the_slice_used=12
slice_available=3650 slice_fixed=0 slice_registers_available=29200 slice_registers_fixed=0
slice_registers_used=37 slice_registers_util_percentage=0.13 slice_used=13 slice_util_percentage=0.36
slicel_fixed=0 slicel_used=11 slicem_fixed=0 slicem_used=2
unique_control_sets_available=3650 unique_control_sets_fixed=3650 unique_control_sets_used=4 unique_control_sets_util_percentage=0.11
using_o5_and_o6_fixed=0.11 using_o5_and_o6_used=6 using_o5_output_only_fixed=6 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=17
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=1 xadc_used=1 xadc_util_percentage=100.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7s25csga225-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=top -verilog_define=default::[not_specified]
usage
elapsed=00:00:21s hls_ip=0 memory_gain=574.301MB memory_peak=1014.859MB

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::