Nexys 4 DDR - Getting Started with Microblaze Servers


This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the Getting Started with Microblaze guide by making use of the on-board Ethernet port and GPIOs for the Nexys 4 DDR FPGA board.

At the end of this tutorial you will have a comprehensive hardware design for Nexys4 DDR that makes use of various Hardware ports on the Nexys 4 DDR which are managed by the Microblaze Softcore Processor block.



  • Digilent Nexys 4 DDR FPGA Board
  • Micro USB Cable


  • Xilinx Vivado 2015.X with the SDK package

Board Support Files

  • Board Support Files


Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add Ethernet functionality and create an echo server.

General Design Flow

I. Vivado

  • Open Vivado and select Nexys 4 DDR board
  • Create an new Vivado Project
  • Create empty block design workspace inside the new project
  • Add required IP blocks using the IP integrator tool and build Hardware Design
  • Validate and save block design
  • Create HDL system wrapper
  • Run design Synthesis and Implementation
  • Generate Bit File
  • Export Hardware Design including the generated bit stream file to SDK tool
  • Launch SDK

Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.


  • Create new application project and select default Hello World template
  • Program FPGA
  • Run configuration by selecting the correct UART COM Port and Baud Rate


1. Creating a New Project

1.1) Open up Vivado and click Create New Project to open Vivado's New Project wizard.

1.2) A new window will open up, click Next and you'll see the screen below. Name your project (no spaces!) and choose your project saving directory before clicking Next. Underscores are a good substitute for empty spaces.

1.3) We will be building this project from the ground up and adding our own sources so we will want to create an RTL project. Select RTL Project and leave the Do not specify sources box unchecked. Click Next.

1.4) If you have followed the Board Support File Wiki guide then click next and select Boards. From the filter options make required selections for Vendor, Display Name and Board Revision. Nexys 4 DDR should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.

1.5) Click Next, a summary of the new project design sources and target device is displayed. Click Finish.

At this point you have successfully created a project that will properly communicate with the Nexys 4 DDR.

2. Creating New Block Design

2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design.

2.2) On the left you should see the Flow Navigator. Select Create Block Design under the IP Integrator. Give a name to your design without any empty spaces.

Add the Microblaze Core:

2.3) An empty design workspace is created where you can add IP blocks. Click on the Add IP button. This should open a catalog of pre-built IP blocks from Xilinx IP repository. Search for “Microblaze” and double click on it to add the IP block to your empty design.

2.4) This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the Run Block Automation message prompt or by double clicking on the block itself.

2.5) Select Run Block Automation and a customization assistant window will open with default settings. Set up like picture below.

2.6) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. Do not click on Run Connection Automation yet.

Adding the Necessary Output Clocks:

2.7) Double click on the Clock Wizard (clk_wiz_1) IP block.

2.8) Change CLK_IN1 to use “sys clock”, and EXT_RESET_IN to use “reset” as shown below and click OK. This will customize the block with our new user settings.

2.9) Select the Output Clocks tab.

2.10) Enable clk_out2, and clk_out3. Set clk_out2 to “200.0” MHz, clk_out3 to “50.0” MHz, and set Reset Type as Active Low. The left panel shows a GUI representation of the block and its internal settings. Observe that the reset pin will now read as resetn. Once finished click OK.

3. Adding the IP Cores

3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:
 * Memory Interface Generator
 * Ethernet PHY MII to Reduced MII
 * AXI Uartlite
 * AXI EthernetLite
 * AXI Timer
3.2) Add all of these to your design, one at a time, using the Add IP button. Once they are all added, you should see the four blocks shown below.

4. Configuring and Routing the IP Cores

4.1) Click Run Block Automation and run it for the mig_7series_0 block.

When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for the Nexys 4 DDR. Click OK to dismiss this message.

4.2) On the AXI EthernetLite block, connect the MII output to the MII input on the Ethernet PHY MII to Reduced MII block. To do this, hover over the blue rectangle next to MII+ until you see a pencil cursor. Click and drag this over to the +MII input of the other block and release.

4.2) Route clk_out2 and clk_out3 on your Clocking Wizard block to sys_clk_i on the Memory Interface Generator and ref_clk on the Ethernet PHY MII to Reduced MII block respectively.

4.3) Click Run Connection Automation. Un-check the microblaze_0 check-box and click OK.

4.4) Click Regenerate Layout (circled in blue below), and your block design should look like this:

4.5) Route interrupt on the AXI Timer block to In0[0:0] on the Concat block. Next route ip2intc_irpt on the AXI EthernetLite block to In1[0:0] on the Concat block.

4.6) Connect resetn on the Clocking Wizard block to the reset pin.

4.7) Right click somewhere in the background (white space) of your design and click Create Port…, or use the shortcut, Ctrl-K. Name this port “eth_ref_clk” and change the options to the one in the picture below. Click OK once finished.

4.8) Connect this eth_ref_clk pin to ref_clk on the Ethernet PHY MII to Reducted MII block.

4.9) Right click on the blue striped rectangle next to the DDR2+ bus on the Memory Interface Generator block and click Make External.

4.10) Clicking Regenerate Layout again will result in your final block design layout for this project.

4.11) We must now connect the eth_ref_clk pin to the correct pin on the FPGA by creating an XDC file. Under the Design window, select the Sources tab. Expand the contraints folder, right click on constr and click Add Sources…

4.12) Select Add or create constraints and click Next.

4.13) Click Create File…, name your new contraints file and click OK and then Finish.

4.14) Open your new constraints file and paste the following line of code in it:
   set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk 

Save the xdc file when you are finished.

4.15) Now, right click on your design_1 block diagram and click Create HDL Wrapper. When the window pops up, select the Let Vivado manage wrapper and auto-update bullet and click OK.

4.16) Click Generate Bitstream at the top of the work space. This process will take a while.

5. Exporting Hardware Design to SDK

5.1) On the top left corner of the window, from the tool bar click on File→Export Hardware. Make sure the generated bitstream is included by checking the box. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.

There is currently a bug where the download.bit file is not generated for the Nexys 4 DDR board. To work around this, click File→Export→Export Bitstream File… then navigate to project/project.sdk/design_1_wrapper_hw_platform_0 and export a new bit file called “download”

6. Launching SDK

6.1) Go to File→Launch SDK and click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete.

7. Inside SDK for Vivado

7.1) A new window for SDK will open. The HW design specification and included IP blocks are displayed in the system.hdf file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server.

8. Creating New Application Project in SDK

8.1) Go to File→New→Application Project in the main toolbar. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure the Target Hardware is the correct hardware design. In our case, it will be design_1_wrapper_hw_platform_0.

If for example, you also have another hardware design in the Project Explorer window, then you will also see this design name in the Target Hardware drop down selection list.

Since we only have one hardware design design_1_wrapper_hw_platform_0 this will be our target hardware. Select Create New under Board Support Package. The tool will automatically populate the Board Support Package name to match with the give project name. Click Next.

8.2) Select IwIP Echo Server under the list of available templates and click Finish.

8.3) After completing the previous step, you will see two new folders in the Project Explorer panel. echo_server which contains all the binaries, .C and .H (Header) files, and echo_server_bsp which is the board support folder.

echo_server is our main working source folder. This also contains an important file shown here in the src folder called lscript.ld. This is a Xilinx auto generated linker script file. Double click on this file to open.

9. Verify Linker Script File for Memory Region Mapping

9.1) In the linker script, take a look at the Section to Memory Region Mapping box. If you did the Make DDR2 External step then the target memory region column must read mig_7series_0.
9.2) Scroll down to check if this applies to all rows. If for any region it does not say mig_7series_0, then click on the row under the Memory Region column and select mig_7series_0.

10.1) Open the system.mss file within the echo_server_bsp folder and click Modify this BSP's Settings.

10.2) Once in Board Support Package Settings select Overview→standalone→lwip141. The configuration table for the lwip141 library should now be visible on the right. Navigate to temac_adapter_options→phy_link_speed. Here you will need to change CONFIG_LINKSPEED_AUTODETECT to CONFIG_LINKSPEED100 so that it looks like the picture below.

11. Programming FPGA with Bit File

11.1) Make sure that the Nexys 4 DDR is turned on and connected to the host PC via micro USB cable. On the main toolbar, click Xilinx Tools→Program FPGA
Make sure that the Hardware Platform is selected as design_1_wrapper_hw_platform_0.

In the software configuration box, under ELF File to Initialize in Block RAM column, the row option must read bootloop. If not, click on the row and select bootloop.

Now click on Program.

12. Setting up the SDK Serial Console and Running the Server

12.1) Right click on the echo_server project folder and select Run As→Run Configurations

12.2) Go to the STDIO Connection tab and check the Connect STDIO to Console check-box. Click Apply, then click Run.

13. Running the Server

13.1) In the console window at the bottom of the screen the details of the connection will be displayed.

14. Testing the Server with Tera Term

14.1) Connect your PC to your Nexys 4 DDR using an Ethernet cable. If using a router, watch the UART console to find out the IP of the Nexys 4 DDR echo server, and connect to that IP address. Setting up the connection as static is unnecessary.
14.2) In order to connect to the echo server directly from your computer, you must set up your Ethernet connection with a static IP address. To do this:
14.2.1) Right click your internet connection and click Open Network and Sharing Center.

14.2.2) Find the Ethernet Connection to your Nexys 4 DDR. It should be an unidentified network. Click Local Area Connection.

14.2.3) Click Properties.

14.2.4) Select Internet Protocol Version 4 (TCP/IPv4) and click Properties.

14.2.5) Click the Use the following IP address: bullet and type in an IP address “192.168.1.XX”, where XX is a value between 2 and 255, but not 10. This IP must not be the same as another already on your network. Make sure to click within the Subnet mask field to get the mask to autofill. Click Ok and you will have a static IP address.

14.3) Open Tera Term and type in the following info and click Ok.

14.4) Type anything into the console and press your keyboard's Enter key. The echo server will echo back your input and display it in the console.

You can go to Setup→Terminal and change the settings below for a more traditional echo server format