Genesys 2 - Getting Started with Microblaze Servers

Note:The Genesys2 uses a Gigabit Ethernet module which requires the TEMAC IP that is not contained in the Vivado Webpack. In order to complete this tutorial, you must either purchase a license for the TEMAC IP or get the evaluation license for free from their website by following this guide.

Overview

This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the Getting Started with Microblaze guide by making use of the on-board Ethernet port and GPIOs for the Genesys2 FPGA board.

At the end of this tutorial you will have a comprehensive hardware design for the Genesys2 that makes use of various Hardware ports on the Genesys2 which are managed by the Microblaze Softcore Processor block.

NOTE: The Genesys2 requires Vivado Design Edition or System Edition which supports the Kintex-7 FPGA. This is not the same as the free webpack version


Prerequisites

Hardware

  • Digilent Genesys2 FPGA Board
  • 2 Micro USB Cables for UART communication and JTAG programming
  • Ethernet Cable

Software

  • Xilinx Vivado 2015.X
    • System Edition or Design Edition must be installed to support the Kintex-7 FPGA
  • Xilinx SDK
    • Same version as your Vivado installation
  • Serial Terminal Application
    • Tera Term is used in this tutorial
  • TEMAC IP license installed

Board Support Files

  • Board Support Files – These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.

Tutorial

1. Creating the Project

When you first run Vivado this will be the main start window where you can create a new project or open a recent one.

1.1) Click on Create New Project. Choose the Project Name and Location such that there are no blank spaces. This is an important naming convention to follow for project names, file names and location paths.
Underscore in a good substitute for empty spaces.

It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects.

Name your Project and select the Project location and click Next.

1.2) Choose Project Type as RTL Project. Leave the - do not specify sources box unchecked and click Next.

1.3) We will not be importing or creating any files here, so click Next until the part select screen.

1.4) If you have completed the Board Support File Wiki guide, select Boards.
Genesys2 should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. Select the Genesys2 and click Next.

1.5) A summary of the new project design sources and target device is displayed. Click Finish.


2. Creating New Block Design

This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager.

For our design, we will use the IP Integrator to create a new block design.

2.1) On the left you should see the Flow Navigator. Select Create Block Design under the IP Integrator. Give a name to your design (without any empty spaces) and click Ok.



You have created a new block design.


3. Adding the DDR3 Component

3.1) Click the Board tab (Highlighted in orange below)



This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs.
3.2) Click and drag the DDR3 SDRAM component onto the empty block design. Vivado will automatically connect the DDR3 SDRAM and system clock to the MIG IP.

3.3) Click Run Connection Automation in the green banner above. Click Ok.



Vivado will connect your system reset to sys_rst on the MIG.

4. Adding the Microblaze Processor & Configuration

4.1) Click the Add IP button and search for Microblaze.



Double click Microblaze to add it to your block design.

4.2) Click Run Block Automation to open the Block automation for the Microblaze processor.

Here you can choose how much memory to give your Microblaze processor. Configure the options to match the picture below, then click OK.

4.3) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. Do not click on Run Connection Automation yet.


5. Adding Peripheral Components

5.1) Go into the Boards tab again and find the USB UART component. Click and drag this onto the block design to add the Uartlite block to your design.
5.2) Find the Ethernet PHY and drag this onto the block design to add the Ethernet block to your design.

5.3) Click the Add IP button and search for Timer. Double click AXI Timer to add it to your block design.

5.4) Click Run Block Automation in the green banner. Then click OK on the screen that pops up.



This will create a new Ethernet DMA IP block as well as a clock wizard.
5.5) Find the clock wizard axi_ethernet_0_refclk and connect clk_in1 to the ui_clk output on the mig_7series_0 block.

5.6) Click Run Connection Automation in the green banner. Check the All Automation checkbox and click OK.



You might get a warning about obsolete automations. Just Run Connection Automation again on all automations. This will create one AXI Interconnect for the DDR Memory and another for peripheral components.

6. Connecting the Interrupts

6.1) Find the Concat block and double click it to open its settings.

6.2) Change the Number of Ports to 5. Click OK.

6.3) The Concat block takes interrupt inputs and sends them to the Microblaze controller.



Route the following connections to the inputs of the Concat block; order does not matter:
- interrupt on the AXI Timer block.
- mm2s_introut and s2mm_introut on the axi_ethernet_0_dma block.
- mac_irq and interrupt on the axi_ethernet_0 block.

7. Validating Design and making an HDL Wrapper

7.1) Click the Regenerate Layout button to rearrange your block design.

7.2) Select Validate Design. This will check for design and connection errors.
7.3) After the design validation step we will proceed with creating a HDL System Wrapper. Click on the Sources tab and find your block design.

7.4) Right click on your block design and click Create HDL Wrapper. Let Vivado manage wrapper and auto-update and click OK.



This will create a top module in VHDL and will allow you to generate a bitstream.

8. Generating Bit File

8.1) In the top toolbar in Vivado, click Generate Bitstream. This can also be found in the Flow Navigator panel on the left, under Program and Debug.
If you haven't already saved your design, you will get a prompt to save the block design.
8.2) The bit file generation will begin. The tool will run Synthesis and Implementation. After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window.

This process can take anywhere from 5 to 60 minutes depending on your computer.
8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click Cancel.

9. Exporting Hardware Design to SDK

9.1) On the main toolbar, click File and select Export Hardware. Check the box to Include Bitstream and click OK. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.



A new file directory will be created under echo_server.SDK similar to the Vivado hardware design project name. Two other files, .sysdef and .hdf are also created. This step essentially creates a new SDK Workspace.
9.2) On the main toolbar, click File and then Launch SDK. Leave both of the dropdown menus as their default Local to Project and click OK. This will open Xilinx SDK and import your hardware.


10. Inside Xilinx SDK

10.1) The HW design specification and included IP blocks are displayed in the system.hdf file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.

From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.

10.2) Within the Project Explorer tab on the left, you can see your hardware platform.

system is the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.

11. Creating New Application Project in SDK

11.1) Click the New dropdown arrow and select Application Project.



Give your project a name that has no empty spaces and click Next.
11.2) Select lwIP Echo Server from the list of templates and click OK.

You will see two new folders in the Project Explorer panel.

  • echo_server which contains all the binaries, .C and .H (Header) files
  • echo_server_bsp which is the board support folder

echo_server is our main working source folder. This also contains an important file shown here which is the “lscript.ld”. This is a Xilinx auto generated linker script file. Double click on this file to open.

11.3) Back in the Project Explorer, double click and open system.mss under the echo_server_bsp folder. Click Modify this BSP's Settings.

11.4) Click lwip141 then find temac_adapter_options and click the arrow. Find phy_link_speed and change the Value to CONFIG_LINKSPEED100. If your router supports Gigabit transfers, change this value to CONFIG_LINKSPEED1000. Click OK.


12. Programming FPGA with Bit File

12.1) Make sure that the Genesys2 is turned on and connected to the host PC via both the JTAG USB port and the UART USB port.

On the top toolbar, click the Program FPGA button.
12.2) Click Program to program your FPGA with your hardware design.


13. Setting up UART Terminal

13.1) Open up a Serial Terminal application (Tera Term). Connect to the Genesys2 UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block.


14. Program the Microblaze Processor

14.1) Make sure you have your Genesys2 plugged into a router before beginning.
14.2) Back in SDK, select your echo_server project and click the Run As… button. Select Launch on Hardware (System Debugger) and click OK.

14.3) Your program will run and you should see the IP information inside of your Serial Terminal.

14.4) Connect to the echo server by opening another terminal and connecting to the Board IP on port 7.

14.5) Test your echo server by typing something into the terminal. Depending on your settings, you might not see the characters until you press Enter. When you do, the message will be sent to the Echo Server, and will be echoed back onto your Terminal!