Getting Started with Vivado for Hardware-Only Designs

The goal of this guide is to familiarize the reader with the Vivado tools through the “Hello World!” of hardware, blinking an LED.

Note: While this guide was originally created using Vivado 2016.4, the workflow described has not substantially changed, and the guide works as described through to Vivado 2022.1, the latest version as of the time of writing.

Prior to starting this guide make sure to install Vivado:

• For versions 2019.2 and later, see Installing Vivado, Vitis, and Digilent Board Files.
• For versions prior to 2019.2, see Installing Vivado, Xilinx SDK, and Digilent Board Files.
• Download digilent-xdc-master.zip and extract it to a disk drive folder for later use.

Constraint files describe the requirements put upon a design by the components surrounding an FPGA - including all peripherals, external clocks, and more.

In order to connect the ports found in an RTL top module (described later) with the physical pins of the FPGA, a constraint file needs to be added or created. Digilent provides Xilinx Design Constraint (XDC) files for each board. Download digilent-xdc-master.zip, the ZIP Archive containing each of these master XDC files, then extract it in a location you will remember.

Verilog is one of several hardware description languages (HDLs) that can be used within Vivado to describe a circuit to be implemented within an FPGA. This section describes how to create a Verilog file within Vivado, and create a simple circuit that will work on any Digilent FPGA development board.

Unlike when the constraint file was added, at this point, a Define Module dialog will pop up. You can rename your Verilog module using the Module name field, but this is unnecessary. The Verilog module's clock and led ports need to be defined. Clicking the Add () button will add an empty slot for a port to the I/O Port Definitions list.

There are five fields to define for each of the module's I/O ports:

• Port Name: This field defines the name of the port and needs to match one of the names you used in your XDC file.
• Direction: This drop-down menu can be set to input, output, or inout, defining the direction that signals propagate through this port, with respect to your module. Outputs are the signals that your module will be controlling.
• Bus: This can be checked or not, when checked, this port consists of multiple single-bit signals, grouped into a single bus.
• MSB: The index of the most significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.
• LSB: The index of the least significant bit of the port, if it is a bus. This option is grayed out for single-bit ports.

Note: If you are defining a module that will be instantiated in another module, which we will not go into in this guide, be aware that the port names of non-“top” modules should not be declared in the XDC.

If your board uses differential clocking, add two single-bit input ports with the same names as the positive and negative clock ports that were uncommented in your XDC file. Otherwise, add a single single-bit input port with the same name as the clock port that was uncommented in your XDC file.

Add a single-bit output port with the same name as the LED port that was uncommented in your XDC file.

Once these two or three ports have been added, click OK to continue.

At this point, the new source file will be added to the Design Sources folder in the Sources pane of the Project Manager. Expand this folder and double-click on the file to open it.

Next, some Verilog code needs to be written to define how the design will actually behave.

Between the ');' that comes after the module's port list and the 'endmodule' statement, add the following lines of code.

This snippet of code implements a 25-bit counter, which will increment by 1 every clock cycle, and roll back over to 0 after ~33 million cycles (about a third of a second, given a 100MHz input clock). The LED is directly driven by the top bit of the counter, which, of the bits, changes the least frequently. Given a 100MHz clock, the LED will blink (go through a full cycle of low-to-high-to-low transitions) approximately three times per second.

reg [24:0] count = 0;
 
assign led = count[24];
 
always @ (posedge(clk)) count <= count + 1;

If your board is differentially clocked, add the following lines of code after ');' and before the 'reg [24:0] count = 0;' line.

This instantiates a differential input buffer, which will allow you to get a non-differential clock that can be used to clock the FPGA fabric.

wire clk;
 
IBUFGDS clk_inst (
    .O(clk),
    .I(clk_p),
    .IB(clk_n)
);

It should be noted that the rate at which the clock will blink will differ depending on the board used. System clocks on different Digilent boards run at a number of different rates, depending on the needs of the board. The system clock period in nanoseconds can be found on the create_clock line of the XDC file.

After completing this guide, it is suggested to try changing the provided Verilog code so that the clock blinks at 1 Hertz. (Note that the XDC file only describes the period of the input clock, and changing it will only misinform the tools, rather than changing the input clock period)

In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.

This starts with Synthesis. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click either in the toolbar or in the Flow Navigator. The output of Synthesis is then passed to Implementation.

Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either in the toolbar or in the Flow Navigator. This output is then passed on to the Bitstream Generator.

The Bitstream Generator generates the final output file needed for programming the FPGA. To run Bitstream Generation click either in the toolbar or in the Flow Navigator. With no settings changed, the generator will create a '.bit' file.

Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop-up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so click Cancel. The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.

You should now see one of the LEDs on your board blinking!

Be sure to visit your board's resource center for more tutorials and demo projects. A link to each resource center can be found on this wiki's Programmable Logic page.