cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: CR_II_Demo                          Date:  3- 4-2015,  9:51AM
Device Used: XC2C256-7-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
75 /256 ( 29%) 171 /896  ( 19%) 157 /640  ( 25%) 56 /256 ( 22%) 21 /118 ( 18%)

** Function Block Resources **

Function Mcells   FB Inps  Pterms   IO       CTC      CTR      CTS      CTE     
Block    Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1      16/16*    20/40    15/56     0/ 6    0/1      0/1      0/1      0/1
FB2      16/16*    24/40    45/56     0/ 8    1/1*     0/1      0/1      0/1
FB3      16/16*    30/40    16/56     0/ 6    0/1      0/1      0/1      0/1
FB4      10/16     24/40    12/56     0/ 8    1/1*     0/1      0/1      0/1
FB5       0/16      0/40     0/56     0/ 5    0/1      0/1      0/1      0/1
FB6       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB7       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB8       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB9       0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB10      0/16      0/40     0/56     0/ 9    0/1      0/1      0/1      0/1
FB11      4/16      2/40     4/56     4/ 8    0/1      0/1      0/1      0/1
FB12      1/16      1/40     1/56     0/ 6    1/1*     0/1      0/1      0/1
FB13      0/16      0/40     0/56     0/ 8    0/1      0/1      0/1      0/1
FB14      5/16     35/40    22/56     5/ 8    0/1      0/1      0/1      0/1
FB15      0/16      0/40     0/56     0/ 7    0/1      0/1      0/1      0/1
FB16      7/16     21/40    56/56*    7/ 7*   0/1      0/1      0/1      0/1
         -----    -------  -------   -----    ---      ---      ---      ---
Total    75/256   157/640  171/896   16/118   3/16     0/16     0/16     0/16

CTC - Control Term Clock
CTR - Control Term Reset
CTS - Control Term Set
CTE - Control Term Output Enable

* - Resource is exhausted

** Global Control Resources **

GCK         GSR         GTS         DGE         
Used/Tot    Used/Tot    Used/Tot    Used/Tot    
1/3         1/1         0/4         0/1

Signal 'CLK' mapped onto global clock net GCK2.
Signal 'BTN<0>' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :    18    108
Output        :   16          16    |  GCK/IO           :     1      3
Bidirectional :    0           0    |  GTS/IO           :     0      4
GCK           :    1           1    |  GSR/IO           :     1      1
GTS           :    0           0    |  CDR/IO           :     0      1
GSR           :    1           1    |  DGE/IO           :     1      1
                 ----        ----
        Total     21          21

End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'CR_II_Demo.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'CLK' based upon the LOC
   constraint 'P38'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld - Unable to map all desired signals into function block, FB16.
   Buffering output signal CAT<2> to allow all signals assigned to this function
   block to be placed.
*************************  Summary of Mapped Logic  ************************

** 16 Outputs **

Signal                       Total Total Bank Loc     Pin   Pin       Pin     I/O      I/O       Slew Reg     Reg Init
Name                         Pts   Inps               No.   Type      Use     STD      Style     Rate Use     State
ANO<0>                       1     2     2    FB11_13 126   I/O       O       LVCMOS18           FAST         
ANO<1>                       1     2     2    FB11_14 128   I/O       O       LVCMOS18           FAST         
ANO<2>                       1     2     2    FB11_15 129   I/O       O       LVCMOS18           FAST         
ANO<3>                       1     2     2    FB11_16 130   I/O       O       LVCMOS18           FAST         
LD<0>                        1     2     1    FB14_4  69    I/O       O       LVCMOS18           FAST         
LD<1>                        1     2     1    FB14_6  68    I/O       O       LVCMOS18           FAST         
LD<2>                        1     2     1    FB14_13 66    I/O       O       LVCMOS18           FAST         
LD<3>                        7     15    1    FB14_14 64    I/O       O       LVCMOS18           FAST DFF     RESET
CAT<6>                       12    18    1    FB14_16 61    I/O       O       LVCMOS18           FAST         
CAT<2>                       1     1     1    FB16_5  60    I/O       O       LVCMOS18           FAST         
CAT<7>                       1     2     1    FB16_6  59    I/O       O       LVCMOS18           FAST         
CAT<3>                       14    20    1    FB16_11 58    I/O       O       LVCMOS18           FAST         
CAT<4>                       10    20    1    FB16_12 57    I/O       O       LVCMOS18           FAST         
CAT<0>                       14    20    1    FB16_13 56    I/O       O       LVCMOS18           FAST         
CAT<5>                       16    18    1    FB16_15 54    I/O       O       LVCMOS18           FAST         
CAT<1>                       12    20    1    FB16_16 53    I/O       O       LVCMOS18           FAST         

** 59 Buried Nodes **

Signal                       Total Total Loc     Reg     Reg Init
Name                         Pts   Inps          Use     State
Inst_clk_div/base_count<8>   1     9     FB1_1   TFF     RESET
Inst_clk_div/base_count<7>   1     7     FB1_2   TFF     RESET
Inst_clk_div/base_count<17>  1     17    FB1_3   TFF     RESET
Inst_clk_div/base_count<19>  2     20    FB1_4   TFF     RESET
Inst_clk_div/base_count<6>   1     6     FB1_5   TFF     RESET
Inst_clk_div/base_count<18>  2     19    FB1_6   TFF     RESET
Inst_clk_div/base_count<5>   1     5     FB1_7   TFF     RESET
Inst_clk_div/base_count<4>   1     4     FB1_8   TFF     RESET
Inst_clk_div/base_count<3>   1     3     FB1_9   TFF     RESET
Inst_clk_div/base_count<2>   1     2     FB1_10  TFF     RESET
Inst_clk_div/base_count<1>   1     1     FB1_11  TFF     RESET
Inst_clk_div/base_count<13>  2     14    FB1_12  TFF     RESET
Inst_clk_div/base_count<12>  2     13    FB1_13  TFF     RESET
Inst_clk_div/base_count<10>  2     11    FB1_14  TFF     RESET
Inst_clk_div/disp_count<0>   0     0     FB1_15  TFF     RESET
Inst_clk_div/base_count<0>   0     0     FB1_16  TFF     RESET
Inst_Timer_Block/S_HUNS<2>   2     6     FB2_1   TFF     RESET
Inst_Timer_Block/S_HUNS<3>   3     8     FB2_2   TFF     RESET
Inst_Timer_Block/T0/TC_ONES  4     8     FB2_3   DFF     RESET
Inst_Timer_Block/S_THOU<2>   2     7     FB2_4   TFF     RESET
Inst_Timer_Block/T0/TC_TENS  5     9     FB2_5   DFF     RESET
Inst_Timer_Block/S_TENS<3>   3     7     FB2_6   TFF     RESET
Inst_Timer_Block/S_TENS<1>   3     7     FB2_7   TFF     RESET
Inst_Timer_Block/S_ONES<3>   3     6     FB2_8   TFF     RESET
Inst_Timer_Block/S_ONES<1>   3     6     FB2_9   TFF     RESET
N_PZ_467                     2     10    FB2_10          
N_PZ_466                     2     10    FB2_11          
Inst_Timer_Block/T0/TC_HUNS  6     10    FB2_12  DFF     RESET
Inst_Timer_Block/S_THOU<1>   4     9     FB2_13  TFF     RESET
Inst_Timer_Block/S_THOU<3>   3     9     FB2_14  TFF     RESET
Inst_Timer_Block/S_HUNS<1>   4     8     FB2_15  TFF     RESET
CAT<2>_BUFR                  12    18    FB2_16          
Inst_clk_div/disp_count<10>  1     10    FB3_1   TFF     RESET
Inst_clk_div/disp_count<9>   1     9     FB3_2   TFF     RESET
Inst_clk_div/disp_count<8>   1     8     FB3_3   TFF     RESET
Inst_clk_div/disp_count<4>   1     4     FB3_4   TFF     RESET
Inst_clk_div/disp_count<7>   1     7     FB3_5   TFF     RESET
Inst_clk_div/disp_count<3>   1     3     FB3_6   TFF     RESET
Inst_clk_div/disp_count<2>   1     2     FB3_7   TFF     RESET
Inst_clk_div/disp_count<1>   1     1     FB3_8   TFF     RESET

Signal                       Total Total Loc     Reg     Reg Init
Name                         Pts   Inps          Use     State
N_PZ_446                     1     12    FB3_9           
Inst_clk_div/base_count<9>   1     9     FB3_10  TFF     RESET
Inst_clk_div/base_count<11>  1     11    FB3_11  TFF     RESET
Inst_clk_div/base_count<14>  1     14    FB3_12  TFF     RESET
Inst_clk_div/base_count<15>  1     15    FB3_13  TFF     RESET
Inst_clk_div/disp_count<6>   1     6     FB3_14  TFF     RESET
Inst_clk_div/base_count<16>  1     16    FB3_15  TFF     RESET
Inst_clk_div/disp_count<5>   1     5     FB3_16  TFF     RESET
Inst_Timer_Block/S_THOU<0>   2     5     FB4_7   TFF     RESET
Inst_Timer_Block/S_HUNS<0>   2     4     FB4_8   TFF     RESET
Inst_Timer_Block/S_TENS<0>   2     3     FB4_9   TFF     RESET
Inst_Timer_Block/S_2BIT<1>   2     2     FB4_10  TFF     RESET
Inst_Timer_Block/S_2BIT<0>   1     1     FB4_11  TFF     RESET
Inst_Timer_Block/S_ONES<2>   2     4     FB4_12  TFF     RESET
Inst_clk_div/disp_count<11>  1     11    FB4_13  TFF     RESET
Inst_Timer_Block/S_TENS<2>   2     5     FB4_14  TFF     RESET
Inst_clk_div/disp_count<12>  1     12    FB4_15  TFF     RESET
s_disp                       1     13    FB4_16  TFF     RESET
Inst_Timer_Block/S_ONES<0>   1     1     FB12_15 TFF     RESET

** 5 Inputs **

Signal                       Bank Loc     Pin   Pin       Pin     I/O      I/O
Name                                      No.   Type      Use     STD      Style
BTN<0>                       2    FB1_3   143   GSR/I/O   GSR/I   LVCMOS18 KPR
CLK                          1    FB6_4   38    GCK/I/O   GCK     LVCMOS18 KPR
SW<0>                        1    FB6_12  39    DGE/I/O   I       LVCMOS18 KPR
SW<1>                        2    FB11_11 124   I/O       I       LVCMOS18 KPR
BTN<1>                       2    FB12_15 94    I/O       I       LVCMOS18 KPR

Legend:
Pin No.   - ~     - User Assigned
I/O Style - OD    - OpenDrain
          - PU    - Pullup
          - KPR   - Keeper
          - S     - SchmittTrigger
          - DG    - DataGate
Reg Use   - LATCH - Transparent latch
          - DFF   - D-flip-flop
          - DEFF  - D-flip-flop with clock enable
          - TFF   - T-flip-flop
          - TDFF  - Dual-edge-triggered T-flip-flop
          - DDFF  - Dual-edge-triggered flip-flop
          - DDEFF - Dual-edge-triggered flip-flop with clock enable
          /S (after any above flop/latch type) indicates initial state is Set
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
              VRF - Vref
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               20/20
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   15/41
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Inst_clk_div/base_count<8>    1     FB1_1        (b)     (b)               
Inst_clk_div/base_count<7>    1     FB1_2        (b)     (b)               
Inst_clk_div/base_count<17>   1     FB1_3   143  GSR/I/O GSR/I             
Inst_clk_div/base_count<19>   2     FB1_4   142  I/O     (b)               
Inst_clk_div/base_count<6>    1     FB1_5        (b)     (b)               
Inst_clk_div/base_count<18>   2     FB1_6   140  I/O     (b)               
Inst_clk_div/base_count<5>    1     FB1_7        (b)     (b)               
Inst_clk_div/base_count<4>    1     FB1_8        (b)     (b)               
Inst_clk_div/base_count<3>    1     FB1_9        (b)     (b)               
Inst_clk_div/base_count<2>    1     FB1_10       (b)     (b)               
Inst_clk_div/base_count<1>    1     FB1_11       (b)     (b)               
Inst_clk_div/base_count<13>   2     FB1_12  139  I/O     (b)               
Inst_clk_div/base_count<12>   2     FB1_13  138  I/O     (b)               
Inst_clk_div/base_count<10>   2     FB1_14  137  I/O     (b)               
Inst_clk_div/disp_count<0>    0     FB1_15       (b)     (b)               
Inst_clk_div/base_count<0>    0     FB1_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: Inst_clk_div/base_count<0>    8: Inst_clk_div/base_count<16>  15: Inst_clk_div/base_count<5> 
  2: Inst_clk_div/base_count<10>   9: Inst_clk_div/base_count<17>  16: Inst_clk_div/base_count<6> 
  3: Inst_clk_div/base_count<11>  10: Inst_clk_div/base_count<18>  17: Inst_clk_div/base_count<7> 
  4: Inst_clk_div/base_count<12>  11: Inst_clk_div/base_count<1>   18: Inst_clk_div/base_count<8> 
  5: Inst_clk_div/base_count<13>  12: Inst_clk_div/base_count<2>   19: Inst_clk_div/base_count<9> 
  6: Inst_clk_div/base_count<14>  13: Inst_clk_div/base_count<3>   20: N_PZ_446 
  7: Inst_clk_div/base_count<15>  14: Inst_clk_div/base_count<4>  

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Inst_clk_div/base_count<8> 
                  X.........XXXXXXX..X.................... 9       
Inst_clk_div/base_count<7> 
                  X.........XXXXXX........................ 7       
Inst_clk_div/base_count<17> 
                  XXXXXXXX..XXXXXXXXX..................... 17      
Inst_clk_div/base_count<19> 
                  XXXXXXXXXXXXXXXXXXXX.................... 20      
Inst_clk_div/base_count<6> 
                  X.........XXXXX......................... 6       
Inst_clk_div/base_count<18> 
                  XXXXXXXXX.XXXXXXXXXX.................... 19      
Inst_clk_div/base_count<5> 
                  X.........XXXX.......................... 5       
Inst_clk_div/base_count<4> 
                  X.........XXX........................... 4       
Inst_clk_div/base_count<3> 
                  X.........XX............................ 3       
Inst_clk_div/base_count<2> 
                  X.........X............................. 2       
Inst_clk_div/base_count<1> 
                  X....................................... 1       
Inst_clk_div/base_count<13> 
                  XXXX......XXXXXXXXXX.................... 14      
Inst_clk_div/base_count<12> 
                  XXX.......XXXXXXXXXX.................... 13      
Inst_clk_div/base_count<10> 
                  X.........XXXXXXXXXX.................... 11      
Inst_clk_div/disp_count<0> 
                  ........................................ 0       
Inst_clk_div/base_count<0> 
                  ........................................ 0       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB2  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               24/16
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   45/11
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Inst_Timer_Block/S_HUNS<2>    2     FB2_1   2    GTS/I/O (b)    +          
Inst_Timer_Block/S_HUNS<3>    3     FB2_2        (b)     (b)    +          
Inst_Timer_Block/T0/TC_ONES   4     FB2_3   3    GTS/I/O (b)    +          
Inst_Timer_Block/S_THOU<2>    2     FB2_4   4    I/O     (b)    +          
Inst_Timer_Block/T0/TC_TENS   5     FB2_5   5    GTS/I/O (b)    +          
Inst_Timer_Block/S_TENS<3>    3     FB2_6        (b)     (b)    +          
Inst_Timer_Block/S_TENS<1>    3     FB2_7        (b)     (b)    +          
Inst_Timer_Block/S_ONES<3>    3     FB2_8        (b)     (b)    +          
Inst_Timer_Block/S_ONES<1>    3     FB2_9        (b)     (b)    +          
N_PZ_467                      2     FB2_10       (b)     (b)               
N_PZ_466                      2     FB2_11       (b)     (b)               
Inst_Timer_Block/T0/TC_HUNS   6     FB2_12  6    GTS/I/O (b)    +          
Inst_Timer_Block/S_THOU<1>    4     FB2_13  7    I/O     (b)    +          
Inst_Timer_Block/S_THOU<3>    3     FB2_14  9    I/O     (b)    +          
Inst_Timer_Block/S_HUNS<1>    4     FB2_15  10   I/O     (b)    +          
CAT<2>_BUFR                   12    FB2_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: BTN<0>                       9: Inst_Timer_Block/S_ONES<0>  17: Inst_Timer_Block/S_THOU<0> 
  2: BTN<1>                      10: Inst_Timer_Block/S_ONES<1>  18: Inst_Timer_Block/S_THOU<1> 
  3: Inst_Timer_Block/S_2BIT<0>  11: Inst_Timer_Block/S_ONES<2>  19: Inst_Timer_Block/S_THOU<2> 
  4: Inst_Timer_Block/S_2BIT<1>  12: Inst_Timer_Block/S_ONES<3>  20: Inst_Timer_Block/S_THOU<3> 
  5: Inst_Timer_Block/S_HUNS<0>  13: Inst_Timer_Block/S_TENS<0>  21: Inst_Timer_Block/T0/TC_HUNS 
  6: Inst_Timer_Block/S_HUNS<1>  14: Inst_Timer_Block/S_TENS<1>  22: Inst_Timer_Block/T0/TC_ONES 
  7: Inst_Timer_Block/S_HUNS<2>  15: Inst_Timer_Block/S_TENS<2>  23: Inst_Timer_Block/T0/TC_TENS 
  8: Inst_Timer_Block/S_HUNS<3>  16: Inst_Timer_Block/S_TENS<3>  24: LD<3> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Inst_Timer_Block/S_HUNS<2> 
                  .X..XX...............XXX................ 6       
Inst_Timer_Block/S_HUNS<3> 
                  .X..XXXX.............XXX................ 8       
Inst_Timer_Block/T0/TC_ONES 
                  XX......XXXX.........X.X................ 8       
Inst_Timer_Block/S_THOU<2> 
                  .X..............XX..XXXX................ 7       
Inst_Timer_Block/T0/TC_TENS 
                  XX..........XXXX.....XXX................ 9       
Inst_Timer_Block/S_TENS<3> 
                  .X..........XXXX.....X.X................ 7       
Inst_Timer_Block/S_TENS<1> 
                  .X..........XXXX.....X.X................ 7       
Inst_Timer_Block/S_ONES<3> 
                  .X......XXXX...........X................ 6       
Inst_Timer_Block/S_ONES<1> 
                  .X......XXXX...........X................ 6       
N_PZ_467          ..XXXXXX....XXXX........................ 10      
N_PZ_466          ..XX....XXXX....XXXX.................... 10      
Inst_Timer_Block/T0/TC_HUNS 
                  XX..XXXX............XXXX................ 10      
Inst_Timer_Block/S_THOU<1> 
                  .X..............XXXXXXXX................ 9       
Inst_Timer_Block/S_THOU<3> 
                  .X..............XXXXXXXX................ 9       
Inst_Timer_Block/S_HUNS<1> 
                  .X..XXXX.............XXX................ 8       
CAT<2>_BUFR       ..XXXXXXXXXXXXXXXXXX.................... 18      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB3  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               30/10
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   16/40
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
Inst_clk_div/disp_count<10>   1     FB3_1   136  I/O     (b)               
Inst_clk_div/disp_count<9>    1     FB3_2   135  I/O     (b)               
Inst_clk_div/disp_count<8>    1     FB3_3   134  I/O     (b)               
Inst_clk_div/disp_count<4>    1     FB3_4        (b)     (b)               
Inst_clk_div/disp_count<7>    1     FB3_5   133  I/O     (b)               
Inst_clk_div/disp_count<3>    1     FB3_6        (b)     (b)               
Inst_clk_div/disp_count<2>    1     FB3_7        (b)     (b)               
Inst_clk_div/disp_count<1>    1     FB3_8        (b)     (b)               
N_PZ_446                      1     FB3_9        (b)     (b)               
Inst_clk_div/base_count<9>    1     FB3_10       (b)     (b)               
Inst_clk_div/base_count<11>   1     FB3_11       (b)     (b)               
Inst_clk_div/base_count<14>   1     FB3_12       (b)     (b)               
Inst_clk_div/base_count<15>   1     FB3_13       (b)     (b)               
Inst_clk_div/disp_count<6>    1     FB3_14  132  I/O     (b)               
Inst_clk_div/base_count<16>   1     FB3_15       (b)     (b)               
Inst_clk_div/disp_count<5>    1     FB3_16  131  I/O     (b)               

Signals Used by Logic in Function Block
  1: Inst_clk_div/base_count<0>   11: Inst_clk_div/base_count<19>  21: Inst_clk_div/disp_count<0> 
  2: Inst_clk_div/base_count<10>  12: Inst_clk_div/base_count<1>   22: Inst_clk_div/disp_count<1> 
  3: Inst_clk_div/base_count<11>  13: Inst_clk_div/base_count<2>   23: Inst_clk_div/disp_count<2> 
  4: Inst_clk_div/base_count<12>  14: Inst_clk_div/base_count<3>   24: Inst_clk_div/disp_count<3> 
  5: Inst_clk_div/base_count<13>  15: Inst_clk_div/base_count<4>   25: Inst_clk_div/disp_count<4> 
  6: Inst_clk_div/base_count<14>  16: Inst_clk_div/base_count<5>   26: Inst_clk_div/disp_count<5> 
  7: Inst_clk_div/base_count<15>  17: Inst_clk_div/base_count<6>   27: Inst_clk_div/disp_count<6> 
  8: Inst_clk_div/base_count<16>  18: Inst_clk_div/base_count<7>   28: Inst_clk_div/disp_count<7> 
  9: Inst_clk_div/base_count<17>  19: Inst_clk_div/base_count<8>   29: Inst_clk_div/disp_count<8> 
 10: Inst_clk_div/base_count<18>  20: Inst_clk_div/base_count<9>   30: Inst_clk_div/disp_count<9> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Inst_clk_div/disp_count<10> 
                  ....................XXXXXXXXXX.......... 10      
Inst_clk_div/disp_count<9> 
                  ....................XXXXXXXXX........... 9       
Inst_clk_div/disp_count<8> 
                  ....................XXXXXXXX............ 8       
Inst_clk_div/disp_count<4> 
                  ....................XXXX................ 4       
Inst_clk_div/disp_count<7> 
                  ....................XXXXXXX............. 7       
Inst_clk_div/disp_count<3> 
                  ....................XXX................. 3       
Inst_clk_div/disp_count<2> 
                  ....................XX.................. 2       
Inst_clk_div/disp_count<1> 
                  ....................X................... 1       
N_PZ_446          .XXXXXXXXXX.......XX.................... 12      
Inst_clk_div/base_count<9> 
                  X..........XXXXXXXX..................... 9       
Inst_clk_div/base_count<11> 
                  XX.........XXXXXXXXX.................... 11      
Inst_clk_div/base_count<14> 
                  XXXXX......XXXXXXXXX.................... 14      
Inst_clk_div/base_count<15> 
                  XXXXXX.....XXXXXXXXX.................... 15      
Inst_clk_div/disp_count<6> 
                  ....................XXXXXX.............. 6       
Inst_clk_div/base_count<16> 
                  XXXXXXX....XXXXXXXXX.................... 16      
Inst_clk_div/disp_count<5> 
                  ....................XXXXX............... 5       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB4  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               24/16
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   12/44
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB4_1   11   I/O           
(unused)                      0     FB4_2   12   I/O           
(unused)                      0     FB4_3   13   I/O           
(unused)                      0     FB4_4   14   I/O           
(unused)                      0     FB4_5   15   I/O           
(unused)                      0     FB4_6   16   I/O           
Inst_Timer_Block/S_THOU<0>    2     FB4_7        (b)     (b)    +          
Inst_Timer_Block/S_HUNS<0>    2     FB4_8        (b)     (b)    +          
Inst_Timer_Block/S_TENS<0>    2     FB4_9        (b)     (b)    +          
Inst_Timer_Block/S_2BIT<1>    2     FB4_10       (b)     (b)               
Inst_Timer_Block/S_2BIT<0>    1     FB4_11       (b)     (b)               
Inst_Timer_Block/S_ONES<2>    2     FB4_12  17   I/O     (b)    +          
Inst_clk_div/disp_count<11>   1     FB4_13       (b)     (b)               
Inst_Timer_Block/S_TENS<2>    2     FB4_14  18   I/O     (b)    +          
Inst_clk_div/disp_count<12>   1     FB4_15       (b)     (b)               
s_disp                        1     FB4_16       (b)     (b)               

Signals Used by Logic in Function Block
  1: BTN<1>                        9: Inst_Timer_Block/T0/TC_TENS  17: Inst_clk_div/disp_count<4> 
  2: Inst_Timer_Block/S_2BIT<0>   10: Inst_clk_div/disp_count<0>   18: Inst_clk_div/disp_count<5> 
  3: Inst_Timer_Block/S_ONES<0>   11: Inst_clk_div/disp_count<10>  19: Inst_clk_div/disp_count<6> 
  4: Inst_Timer_Block/S_ONES<1>   12: Inst_clk_div/disp_count<11>  20: Inst_clk_div/disp_count<7> 
  5: Inst_Timer_Block/S_TENS<0>   13: Inst_clk_div/disp_count<12>  21: Inst_clk_div/disp_count<8> 
  6: Inst_Timer_Block/S_TENS<1>   14: Inst_clk_div/disp_count<1>   22: Inst_clk_div/disp_count<9> 
  7: Inst_Timer_Block/T0/TC_HUNS  15: Inst_clk_div/disp_count<2>   23: LD<3> 
  8: Inst_Timer_Block/T0/TC_ONES  16: Inst_clk_div/disp_count<3>   24: s_disp 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
Inst_Timer_Block/S_THOU<0> 
                  X.....XXX.............X................. 5       
Inst_Timer_Block/S_HUNS<0> 
                  X......XX.............X................. 4       
Inst_Timer_Block/S_TENS<0> 
                  X......X..............X................. 3       
Inst_Timer_Block/S_2BIT<1> 
                  .X.....................X................ 2       
Inst_Timer_Block/S_2BIT<0> 
                  .......................X................ 1       
Inst_Timer_Block/S_ONES<2> 
                  X.XX..................X................. 4       
Inst_clk_div/disp_count<11> 
                  .........XX..XXXXXXXXX.................. 11      
Inst_Timer_Block/S_TENS<2> 
                  X...XX.X..............X................. 5       
Inst_clk_div/disp_count<12> 
                  .........XXX.XXXXXXXXX.................. 12      
s_disp            .........XXXXXXXXXXXXX.................. 13      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB5  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB5_1        (b)           
(unused)                      0     FB5_2   33   I/O           
(unused)                      0     FB5_3        (b)           
(unused)                      0     FB5_4   32   GCK/I/O       
(unused)                      0     FB5_5   31   I/O           
(unused)                      0     FB5_6   30   GCK/I/O       
(unused)                      0     FB5_7        (b)           
(unused)                      0     FB5_8        (b)           
(unused)                      0     FB5_9        (b)           
(unused)                      0     FB5_10       (b)           
(unused)                      0     FB5_11       (b)           
(unused)                      0     FB5_12       (b)           
(unused)                      0     FB5_13       (b)           
(unused)                      0     FB5_14  28   I/O           
(unused)                      0     FB5_15       (b)           
(unused)                      0     FB5_16       (b)           
*********************************** FB6  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB6_1   34   I/O           
(unused)                      0     FB6_2   35   CDR/I/O       
(unused)                      0     FB6_3        (b)           
(unused)                      0     FB6_4   38   GCK/I/O GCK   
(unused)                      0     FB6_5        (b)           
(unused)                      0     FB6_6        (b)           
(unused)                      0     FB6_7        (b)           
(unused)                      0     FB6_8        (b)           
(unused)                      0     FB6_9        (b)           
(unused)                      0     FB6_10       (b)           
(unused)                      0     FB6_11       (b)           
(unused)                      0     FB6_12  39   DGE/I/O I     
(unused)                      0     FB6_13  40   I/O           
(unused)                      0     FB6_14  41   I/O           
(unused)                      0     FB6_15  42   I/O           
(unused)                      0     FB6_16  43   I/O           
*********************************** FB7  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB7_1        (b)           
(unused)                      0     FB7_2        (b)           
(unused)                      0     FB7_3        (b)           
(unused)                      0     FB7_4        (b)           
(unused)                      0     FB7_5   26   I/O           
(unused)                      0     FB7_6   25   I/O           
(unused)                      0     FB7_7        (b)           
(unused)                      0     FB7_8        (b)           
(unused)                      0     FB7_9        (b)           
(unused)                      0     FB7_10       (b)           
(unused)                      0     FB7_11  24   I/O           
(unused)                      0     FB7_12  23   I/O           
(unused)                      0     FB7_13  22   I/O           
(unused)                      0     FB7_14  21   I/O           
(unused)                      0     FB7_15  20   I/O           
(unused)                      0     FB7_16  19   I/O           
*********************************** FB8  ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB8_1   44   I/O           
(unused)                      0     FB8_2   45   I/O           
(unused)                      0     FB8_3   46   I/O           
(unused)                      0     FB8_4        (b)           
(unused)                      0     FB8_5   48   I/O           
(unused)                      0     FB8_6   49   I/O           
(unused)                      0     FB8_7        (b)           
(unused)                      0     FB8_8        (b)           
(unused)                      0     FB8_9        (b)           
(unused)                      0     FB8_10       (b)           
(unused)                      0     FB8_11  50   I/O           
(unused)                      0     FB8_12  51   I/O           
(unused)                      0     FB8_13  52   I/O           
(unused)                      0     FB8_14       (b)           
(unused)                      0     FB8_15       (b)           
(unused)                      0     FB8_16       (b)           
*********************************** FB9  ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB9_1   112  I/O           
(unused)                      0     FB9_2   113  I/O           
(unused)                      0     FB9_3        (b)           
(unused)                      0     FB9_4   114  I/O           
(unused)                      0     FB9_5        (b)           
(unused)                      0     FB9_6   115  I/O           
(unused)                      0     FB9_7        (b)           
(unused)                      0     FB9_8        (b)           
(unused)                      0     FB9_9        (b)           
(unused)                      0     FB9_10       (b)           
(unused)                      0     FB9_11       (b)           
(unused)                      0     FB9_12  116  I/O           
(unused)                      0     FB9_13  117  I/O           
(unused)                      0     FB9_14  118  I/O           
(unused)                      0     FB9_15  119  I/O           
(unused)                      0     FB9_16       (b)           
*********************************** FB10 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB10_1  111  I/O           
(unused)                      0     FB10_2  110  I/O           
(unused)                      0     FB10_3  107  I/O           
(unused)                      0     FB10_4  106  I/O           
(unused)                      0     FB10_5  105  I/O           
(unused)                      0     FB10_6  104  I/O           
(unused)                      0     FB10_7       (b)           
(unused)                      0     FB10_8       (b)           
(unused)                      0     FB10_9       (b)           
(unused)                      0     FB10_10      (b)           
(unused)                      0     FB10_11      (b)           
(unused)                      0     FB10_12 103  I/O           
(unused)                      0     FB10_13      (b)           
(unused)                      0     FB10_14 102  I/O           
(unused)                      0     FB10_15      (b)           
(unused)                      0     FB10_16 101  I/O           
*********************************** FB11 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               2/38
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   4/52
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB11_1       (b)           
(unused)                      0     FB11_2       (b)           
(unused)                      0     FB11_3       (b)           
(unused)                      0     FB11_4       (b)           
(unused)                      0     FB11_5  120  I/O           
(unused)                      0     FB11_6  121  I/O           
(unused)                      0     FB11_7       (b)           
(unused)                      0     FB11_8       (b)           
(unused)                      0     FB11_9       (b)           
(unused)                      0     FB11_10      (b)           
(unused)                      0     FB11_11 124  I/O     I     
(unused)                      0     FB11_12 125  I/O           
ANO<0>                        1     FB11_13 126  I/O     O                 
ANO<1>                        1     FB11_14 128  I/O     O                 
ANO<2>                        1     FB11_15 129  I/O     O                 
ANO<3>                        1     FB11_16 130  I/O     O                 

Signals Used by Logic in Function Block
  1: Inst_Timer_Block/S_2BIT<0>   2: Inst_Timer_Block/S_2BIT<1> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
ANO<0>            XX...................................... 2       
ANO<1>            XX...................................... 2       
ANO<2>            XX...................................... 2       
ANO<3>            XX...................................... 2       
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB12 ***********************************
This function block is part of I/O Bank number:               2
Number of function block inputs used/remaining:               1/39
Number of function block control terms used/remaining:        1/3
Number of PLA product terms used/remaining:                   1/55
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB12_1       (b)           
(unused)                      0     FB12_2  100  I/O           
(unused)                      0     FB12_3       (b)           
(unused)                      0     FB12_4       (b)           
(unused)                      0     FB12_5       (b)           
(unused)                      0     FB12_6       (b)           
(unused)                      0     FB12_7       (b)           
(unused)                      0     FB12_8       (b)           
(unused)                      0     FB12_9       (b)           
(unused)                      0     FB12_10      (b)           
(unused)                      0     FB12_11 98   I/O           
(unused)                      0     FB12_12 97   I/O           
(unused)                      0     FB12_13 96   I/O           
(unused)                      0     FB12_14 95   I/O           
Inst_Timer_Block/S_ONES<0>    1     FB12_15 94   I/O     I      +          
(unused)                      0     FB12_16      (b)           

Signals Used by Logic in Function Block
  1: LD<3>            

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB13 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB13_1  75   I/O           
(unused)                      0     FB13_2  76   I/O           
(unused)                      0     FB13_3  77   I/O           
(unused)                      0     FB13_4       (b)           
(unused)                      0     FB13_5  78   I/O           
(unused)                      0     FB13_6  79   I/O           
(unused)                      0     FB13_7       (b)           
(unused)                      0     FB13_8       (b)           
(unused)                      0     FB13_9       (b)           
(unused)                      0     FB13_10      (b)           
(unused)                      0     FB13_11      (b)           
(unused)                      0     FB13_12 80   I/O           
(unused)                      0     FB13_13 81   I/O           
(unused)                      0     FB13_14 82   I/O           
(unused)                      0     FB13_15      (b)           
(unused)                      0     FB13_16      (b)           
*********************************** FB14 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               35/5
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   22/34
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB14_1  74   I/O           
(unused)                      0     FB14_2  71   I/O           
(unused)                      0     FB14_3  70   I/O           
LD<0>                         1     FB14_4  69   I/O     O                 
(unused)                      0     FB14_5       (b)           
LD<1>                         1     FB14_6  68   I/O     O                 
(unused)                      0     FB14_7       (b)           
(unused)                      0     FB14_8       (b)           
(unused)                      0     FB14_9       (b)           
(unused)                      0     FB14_10      (b)           
(unused)                      0     FB14_11      (b)           
(unused)                      0     FB14_12      (b)           
LD<2>                         1     FB14_13 66   I/O     O                 
LD<3>                         7     FB14_14 64   I/O     O                 
(unused)                      0     FB14_15      (b)           
CAT<6>                        12    FB14_16 61   I/O     O                 

Signals Used by Logic in Function Block
  1: BTN<0>                      13: Inst_Timer_Block/S_TENS<1>   25: Inst_clk_div/base_count<15> 
  2: Inst_Timer_Block/S_2BIT<0>  14: Inst_Timer_Block/S_TENS<2>   26: Inst_clk_div/base_count<16> 
  3: Inst_Timer_Block/S_2BIT<1>  15: Inst_Timer_Block/S_TENS<3>   27: Inst_clk_div/base_count<17> 
  4: Inst_Timer_Block/S_HUNS<0>  16: Inst_Timer_Block/S_THOU<0>   28: Inst_clk_div/base_count<18> 
  5: Inst_Timer_Block/S_HUNS<1>  17: Inst_Timer_Block/S_THOU<1>   29: Inst_clk_div/base_count<19> 
  6: Inst_Timer_Block/S_HUNS<2>  18: Inst_Timer_Block/S_THOU<2>   30: Inst_clk_div/base_count<7> 
  7: Inst_Timer_Block/S_HUNS<3>  19: Inst_Timer_Block/S_THOU<3>   31: Inst_clk_div/base_count<8> 
  8: Inst_Timer_Block/S_ONES<0>  20: Inst_clk_div/base_count<10>  32: Inst_clk_div/base_count<9> 
  9: Inst_Timer_Block/S_ONES<1>  21: Inst_clk_div/base_count<11>  33: LD<3> 
 10: Inst_Timer_Block/S_ONES<2>  22: Inst_clk_div/base_count<12>  34: SW<0> 
 11: Inst_Timer_Block/S_ONES<3>  23: Inst_clk_div/base_count<13>  35: SW<1> 
 12: Inst_Timer_Block/S_TENS<0>  24: Inst_clk_div/base_count<14> 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
LD<0>             .................................XX..... 2       
LD<1>             .................................XX..... 2       
LD<2>             .................................XX..... 2       
LD<3>             X..................XXXXXXXXXXXXXX....... 15      
CAT<6>            .XXXXXXXXXXXXXXXXXX..................... 18      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*********************************** FB15 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               0/40
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   0/56
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB15_1       (b)           
(unused)                      0     FB15_2  83   I/O           
(unused)                      0     FB15_3       (b)           
(unused)                      0     FB15_4       (b)           
(unused)                      0     FB15_5       (b)           
(unused)                      0     FB15_6       (b)           
(unused)                      0     FB15_7       (b)           
(unused)                      0     FB15_8       (b)           
(unused)                      0     FB15_9       (b)           
(unused)                      0     FB15_10      (b)           
(unused)                      0     FB15_11 85   I/O           
(unused)                      0     FB15_12 86   I/O           
(unused)                      0     FB15_13 87   I/O           
(unused)                      0     FB15_14 88   I/O           
(unused)                      0     FB15_15 91   I/O           
(unused)                      0     FB15_16 92   I/O           
*********************************** FB16 ***********************************
This function block is part of I/O Bank number:               1
Number of function block inputs used/remaining:               21/19
Number of function block control terms used/remaining:        0/4
Number of PLA product terms used/remaining:                   56/0
Signal                        Total Loc     Pin  Pin     Pin   CTC CTR CTS CTE
Name                          Pt            No.  Type    Use   
(unused)                      0     FB16_1       (b)           
(unused)                      0     FB16_2       (b)           
(unused)                      0     FB16_3       (b)           
(unused)                      0     FB16_4       (b)           
CAT<2>                        1     FB16_5  60   I/O     O                 
CAT<7>                        1     FB16_6  59   I/O     O                 
(unused)                      0     FB16_7       (b)           
(unused)                      0     FB16_8       (b)           
(unused)                      0     FB16_9       (b)           
(unused)                      0     FB16_10      (b)           
CAT<3>                        14    FB16_11 58   I/O     O                 
CAT<4>                        10    FB16_12 57   I/O     O                 
CAT<0>                        14    FB16_13 56   I/O     O                 
(unused)                      0     FB16_14      (b)           
CAT<5>                        16    FB16_15 54   I/O     O                 
CAT<1>                        12    FB16_16 53   I/O     O                 

Signals Used by Logic in Function Block
  1: CAT<2>_BUFR                  8: Inst_Timer_Block/S_ONES<0>  15: Inst_Timer_Block/S_TENS<3> 
  2: Inst_Timer_Block/S_2BIT<0>   9: Inst_Timer_Block/S_ONES<1>  16: Inst_Timer_Block/S_THOU<0> 
  3: Inst_Timer_Block/S_2BIT<1>  10: Inst_Timer_Block/S_ONES<2>  17: Inst_Timer_Block/S_THOU<1> 
  4: Inst_Timer_Block/S_HUNS<0>  11: Inst_Timer_Block/S_ONES<3>  18: Inst_Timer_Block/S_THOU<2> 
  5: Inst_Timer_Block/S_HUNS<1>  12: Inst_Timer_Block/S_TENS<0>  19: Inst_Timer_Block/S_THOU<3> 
  6: Inst_Timer_Block/S_HUNS<2>  13: Inst_Timer_Block/S_TENS<1>  20: N_PZ_466 
  7: Inst_Timer_Block/S_HUNS<3>  14: Inst_Timer_Block/S_TENS<2>  21: N_PZ_467 

Signal                     1         2         3         4 FB      
Name             0----+----0----+----0----+----0----+----0 Inputs  
CAT<2>            X....................................... 1       
CAT<7>            .XX..................................... 2       
CAT<3>            .XXXXXXXXXXXXXXXXXXXX................... 20      
CAT<4>            .XXXXXXXXXXXXXXXXXXXX................... 20      
CAT<0>            .XXXXXXXXXXXXXXXXXXXX................... 20      
CAT<5>            .XXXXXXXXXXXXXXXXXX..................... 18      
CAT<1>            .XXXXXXXXXXXXXXXXXXXX................... 20      
                 0----+----1----+----2----+----3----+----4
                           0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


ANO(0) <= NOT ((NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0)));


ANO(1) <= NOT ((NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0)));


ANO(2) <= NOT ((Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0)));


ANO(3) <= NOT ((Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0)));


CAT(0) <= ((N_PZ_466)
	OR (N_PZ_467)
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(1) AND NOT Inst_Timer_Block/S_THOU(2) AND 
	Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(2) AND 
	Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND NOT Inst_Timer_Block/S_THOU(2) AND 
	NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2) AND 
	Inst_Timer_Block/S_HUNS(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(2) AND 
	Inst_Timer_Block/S_HUNS(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2) AND 
	NOT Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(1) AND NOT Inst_Timer_Block/S_TENS(2) AND 
	Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(1) AND Inst_Timer_Block/S_TENS(2) AND 
	Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(1) AND NOT Inst_Timer_Block/S_TENS(2) AND 
	NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2) AND 
	NOT Inst_Timer_Block/S_ONES(3)));


CAT(1) <= ((Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(2) AND NOT N_PZ_466)
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(2) AND NOT N_PZ_467)
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(1) AND Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(2) AND NOT N_PZ_467)
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(2) AND NOT N_PZ_466)
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(2) AND 
	NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(1) AND 
	Inst_Timer_Block/S_HUNS(2) AND NOT Inst_Timer_Block/S_HUNS(3) AND NOT N_PZ_467)
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(1) AND 
	Inst_Timer_Block/S_TENS(2) AND NOT Inst_Timer_Block/S_TENS(3) AND NOT N_PZ_467)
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2) AND 
	NOT Inst_Timer_Block/S_ONES(3)));


CAT(2) <= CAT(2)_BUFR;


CAT(2)_BUFR <= ((Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(2) AND Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(1) AND 
	Inst_Timer_Block/S_THOU(2) AND Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(2) AND Inst_Timer_Block/S_HUNS(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(1) AND 
	Inst_Timer_Block/S_HUNS(2) AND Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(2) AND Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(1) AND 
	Inst_Timer_Block/S_TENS(2) AND Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(2) AND Inst_Timer_Block/S_ONES(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(1) AND 
	Inst_Timer_Block/S_ONES(2) AND Inst_Timer_Block/S_ONES(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(1) AND NOT Inst_Timer_Block/S_THOU(2) AND 
	NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2) AND 
	NOT Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(1) AND NOT Inst_Timer_Block/S_TENS(2) AND 
	NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2) AND 
	NOT Inst_Timer_Block/S_ONES(3)));


CAT(3) <= ((N_PZ_466)
	OR (N_PZ_467)
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(2))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND NOT Inst_Timer_Block/S_THOU(2))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(2))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(1) AND Inst_Timer_Block/S_TENS(2))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(1) AND NOT Inst_Timer_Block/S_TENS(2))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(1) AND NOT Inst_Timer_Block/S_THOU(2) AND 
	Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2) AND 
	Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(1) AND NOT Inst_Timer_Block/S_TENS(2) AND 
	Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3)));


CAT(4) <= ((N_PZ_466)
	OR (N_PZ_467)
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND NOT Inst_Timer_Block/S_THOU(2))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(1) AND NOT Inst_Timer_Block/S_TENS(2))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2)));


CAT(5) <= ((Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(1) AND NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(2) AND NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(1) AND 
	NOT Inst_Timer_Block/S_THOU(2) AND NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(2) AND NOT Inst_Timer_Block/S_HUNS(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(1) AND 
	NOT Inst_Timer_Block/S_HUNS(2) AND NOT Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(1) AND NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(2) AND NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(1) AND 
	NOT Inst_Timer_Block/S_TENS(2) AND NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(2) AND NOT Inst_Timer_Block/S_ONES(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(1) AND 
	NOT Inst_Timer_Block/S_ONES(2) AND NOT Inst_Timer_Block/S_ONES(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(2) AND 
	Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(2) AND 
	Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(1) AND Inst_Timer_Block/S_TENS(2) AND 
	Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3)));


CAT(6) <= ((Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_THOU(1) AND 
	NOT Inst_Timer_Block/S_THOU(2) AND NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(1) AND 
	NOT Inst_Timer_Block/S_HUNS(2) AND NOT Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(1) AND 
	NOT Inst_Timer_Block/S_TENS(2) AND NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_ONES(1) AND 
	NOT Inst_Timer_Block/S_ONES(2) AND NOT Inst_Timer_Block/S_ONES(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_THOU(0) AND 
	Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(2) AND 
	NOT Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(2) AND 
	Inst_Timer_Block/S_THOU(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(2) AND 
	NOT Inst_Timer_Block/S_HUNS(3))
	OR (Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(2) AND 
	Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_TENS(0) AND 
	Inst_Timer_Block/S_TENS(1) AND Inst_Timer_Block/S_TENS(2) AND 
	NOT Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(1) AND Inst_Timer_Block/S_TENS(2) AND 
	Inst_Timer_Block/S_TENS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2) AND 
	NOT Inst_Timer_Block/S_ONES(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3)));


CAT(7) <= NOT ((NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0)));

FTCPE_Inst_Timer_Block/S_2BIT0: FTCPE port map (Inst_Timer_Block/S_2BIT(0),'0',s_disp,NOT BTN<0>,'0','1');

FTCPE_Inst_Timer_Block/S_2BIT1: FTCPE port map (Inst_Timer_Block/S_2BIT(1),Inst_Timer_Block/S_2BIT(0),s_disp,NOT BTN<0>,'0','1');

FTCPE_Inst_Timer_Block/S_HUNS0: FTCPE port map (Inst_Timer_Block/S_HUNS(0),Inst_Timer_Block/S_HUNS_T(0),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_HUNS_T(0) <= (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS);

FTCPE_Inst_Timer_Block/S_HUNS1: FTCPE port map (Inst_Timer_Block/S_HUNS(1),Inst_Timer_Block/S_HUNS_T(1),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_HUNS_T(1) <= ((BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1))
	OR (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(2))
	OR (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(3)));

FTCPE_Inst_Timer_Block/S_HUNS2: FTCPE port map (Inst_Timer_Block/S_HUNS(2),Inst_Timer_Block/S_HUNS_T(2),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_HUNS_T(2) <= (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1));

FTCPE_Inst_Timer_Block/S_HUNS3: FTCPE port map (Inst_Timer_Block/S_HUNS(3),Inst_Timer_Block/S_HUNS_T(3),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_HUNS_T(3) <= ((BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS AND Inst_Timer_Block/S_HUNS(0) AND 
	Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(2))
	OR (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS AND Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2) AND 
	Inst_Timer_Block/S_HUNS(3)));

FDCPE_Inst_Timer_Block/S_ONES0: FDCPE port map (Inst_Timer_Block/S_ONES(0),BTN(1),LD(3),NOT BTN<0>,'0','1');

FTCPE_Inst_Timer_Block/S_ONES1: FTCPE port map (Inst_Timer_Block/S_ONES(1),Inst_Timer_Block/S_ONES_T(1),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_ONES_T(1) <= (BTN(1) AND Inst_Timer_Block/S_ONES(0))
	XOR (BTN(1) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3));

FTCPE_Inst_Timer_Block/S_ONES2: FTCPE port map (Inst_Timer_Block/S_ONES(2),Inst_Timer_Block/S_ONES_T(2),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_ONES_T(2) <= (BTN(1) AND Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1));

FTCPE_Inst_Timer_Block/S_ONES3: FTCPE port map (Inst_Timer_Block/S_ONES(3),Inst_Timer_Block/S_ONES_T(3),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_ONES_T(3) <= ((BTN(1) AND Inst_Timer_Block/S_ONES(0) AND 
	Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2))
	OR (BTN(1) AND Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3)));

FTCPE_Inst_Timer_Block/S_TENS0: FTCPE port map (Inst_Timer_Block/S_TENS(0),Inst_Timer_Block/S_TENS_T(0),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_TENS_T(0) <= (BTN(1) AND Inst_Timer_Block/T0/TC_ONES);

FTCPE_Inst_Timer_Block/S_TENS1: FTCPE port map (Inst_Timer_Block/S_TENS(1),Inst_Timer_Block/S_TENS_T(1),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_TENS_T(1) <= (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/S_TENS(0))
	XOR (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/S_TENS(0) AND NOT Inst_Timer_Block/S_TENS(1) AND 
	NOT Inst_Timer_Block/S_TENS(2) AND Inst_Timer_Block/S_TENS(3));

FTCPE_Inst_Timer_Block/S_TENS2: FTCPE port map (Inst_Timer_Block/S_TENS(2),Inst_Timer_Block/S_TENS_T(2),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_TENS_T(2) <= (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/S_TENS(0) AND Inst_Timer_Block/S_TENS(1));

FTCPE_Inst_Timer_Block/S_TENS3: FTCPE port map (Inst_Timer_Block/S_TENS(3),Inst_Timer_Block/S_TENS_T(3),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_TENS_T(3) <= ((BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/S_TENS(0) AND Inst_Timer_Block/S_TENS(1) AND 
	Inst_Timer_Block/S_TENS(2))
	OR (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/S_TENS(0) AND NOT Inst_Timer_Block/S_TENS(1) AND 
	NOT Inst_Timer_Block/S_TENS(2) AND Inst_Timer_Block/S_TENS(3)));

FTCPE_Inst_Timer_Block/S_THOU0: FTCPE port map (Inst_Timer_Block/S_THOU(0),Inst_Timer_Block/S_THOU_T(0),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_THOU_T(0) <= (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS AND Inst_Timer_Block/T0/TC_HUNS);

FTCPE_Inst_Timer_Block/S_THOU1: FTCPE port map (Inst_Timer_Block/S_THOU(1),Inst_Timer_Block/S_THOU_T(1),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_THOU_T(1) <= ((Inst_Timer_Block/S_THOU(0) AND BTN(1) AND 
	Inst_Timer_Block/T0/TC_ONES AND Inst_Timer_Block/T0/TC_TENS AND 
	Inst_Timer_Block/T0/TC_HUNS AND Inst_Timer_Block/S_THOU(1))
	OR (Inst_Timer_Block/S_THOU(0) AND BTN(1) AND 
	Inst_Timer_Block/T0/TC_ONES AND Inst_Timer_Block/T0/TC_TENS AND 
	Inst_Timer_Block/T0/TC_HUNS AND Inst_Timer_Block/S_THOU(2))
	OR (Inst_Timer_Block/S_THOU(0) AND BTN(1) AND 
	Inst_Timer_Block/T0/TC_ONES AND Inst_Timer_Block/T0/TC_TENS AND 
	Inst_Timer_Block/T0/TC_HUNS AND NOT Inst_Timer_Block/S_THOU(3)));

FTCPE_Inst_Timer_Block/S_THOU2: FTCPE port map (Inst_Timer_Block/S_THOU(2),Inst_Timer_Block/S_THOU_T(2),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_THOU_T(2) <= (Inst_Timer_Block/S_THOU(0) AND BTN(1) AND 
	Inst_Timer_Block/T0/TC_ONES AND Inst_Timer_Block/T0/TC_TENS AND 
	Inst_Timer_Block/T0/TC_HUNS AND Inst_Timer_Block/S_THOU(1));

FTCPE_Inst_Timer_Block/S_THOU3: FTCPE port map (Inst_Timer_Block/S_THOU(3),Inst_Timer_Block/S_THOU_T(3),LD(3),NOT BTN<0>,'0','1');
Inst_Timer_Block/S_THOU_T(3) <= ((Inst_Timer_Block/S_THOU(0) AND BTN(1) AND 
	Inst_Timer_Block/T0/TC_ONES AND Inst_Timer_Block/T0/TC_TENS AND 
	Inst_Timer_Block/T0/TC_HUNS AND Inst_Timer_Block/S_THOU(1) AND 
	Inst_Timer_Block/S_THOU(2))
	OR (Inst_Timer_Block/S_THOU(0) AND BTN(1) AND 
	Inst_Timer_Block/T0/TC_ONES AND Inst_Timer_Block/T0/TC_TENS AND 
	Inst_Timer_Block/T0/TC_HUNS AND NOT Inst_Timer_Block/S_THOU(1) AND 
	NOT Inst_Timer_Block/S_THOU(2) AND Inst_Timer_Block/S_THOU(3)));

FDCPE_Inst_Timer_Block/T0/TC_HUNS: FDCPE port map (Inst_Timer_Block/T0/TC_HUNS,Inst_Timer_Block/T0/TC_HUNS_D,LD(3),'0','0','1');
Inst_Timer_Block/T0/TC_HUNS_D <= ((NOT BTN(1) AND Inst_Timer_Block/T0/TC_HUNS)
	OR (NOT Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_HUNS)
	OR (NOT BTN(0) AND Inst_Timer_Block/T0/TC_HUNS)
	OR (NOT Inst_Timer_Block/T0/TC_TENS AND 
	Inst_Timer_Block/T0/TC_HUNS)
	OR (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND BTN(0) AND 
	Inst_Timer_Block/T0/TC_TENS AND NOT Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND NOT Inst_Timer_Block/S_HUNS(2) AND 
	Inst_Timer_Block/S_HUNS(3)));

FDCPE_Inst_Timer_Block/T0/TC_ONES: FDCPE port map (Inst_Timer_Block/T0/TC_ONES,Inst_Timer_Block/T0/TC_ONES_D,LD(3),'0','0','1');
Inst_Timer_Block/T0/TC_ONES_D <= ((NOT BTN(1) AND Inst_Timer_Block/T0/TC_ONES)
	OR (Inst_Timer_Block/T0/TC_ONES AND NOT BTN(0))
	OR (BTN(1) AND BTN(0) AND NOT Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND NOT Inst_Timer_Block/S_ONES(2) AND 
	Inst_Timer_Block/S_ONES(3)));

FDCPE_Inst_Timer_Block/T0/TC_TENS: FDCPE port map (Inst_Timer_Block/T0/TC_TENS,Inst_Timer_Block/T0/TC_TENS_D,LD(3),'0','0','1');
Inst_Timer_Block/T0/TC_TENS_D <= ((NOT BTN(1) AND Inst_Timer_Block/T0/TC_TENS)
	OR (NOT Inst_Timer_Block/T0/TC_ONES AND 
	Inst_Timer_Block/T0/TC_TENS)
	OR (NOT BTN(0) AND Inst_Timer_Block/T0/TC_TENS)
	OR (BTN(1) AND Inst_Timer_Block/T0/TC_ONES AND BTN(0) AND 
	NOT Inst_Timer_Block/S_TENS(0) AND NOT Inst_Timer_Block/S_TENS(1) AND 
	NOT Inst_Timer_Block/S_TENS(2) AND Inst_Timer_Block/S_TENS(3)));

FTCPE_Inst_clk_div/base_count0: FTCPE port map (Inst_clk_div/base_count(0),'0',CLK,NOT BTN<0>,'0','1');

FTCPE_Inst_clk_div/base_count1: FTCPE port map (Inst_clk_div/base_count(1),Inst_clk_div/base_count(0),CLK,NOT BTN<0>,'0','1');

FTCPE_Inst_clk_div/base_count2: FTCPE port map (Inst_clk_div/base_count(2),Inst_clk_div/base_count_T(2),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(2) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(1));

FTCPE_Inst_clk_div/base_count3: FTCPE port map (Inst_clk_div/base_count(3),Inst_clk_div/base_count_T(3),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(3) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(1) AND Inst_clk_div/base_count(2));

FTCPE_Inst_clk_div/base_count4: FTCPE port map (Inst_clk_div/base_count(4),Inst_clk_div/base_count_T(4),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(4) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(1) AND Inst_clk_div/base_count(2) AND 
	Inst_clk_div/base_count(3));

FTCPE_Inst_clk_div/base_count5: FTCPE port map (Inst_clk_div/base_count(5),Inst_clk_div/base_count_T(5),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(5) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(1) AND Inst_clk_div/base_count(2) AND 
	Inst_clk_div/base_count(3) AND Inst_clk_div/base_count(4));

FTCPE_Inst_clk_div/base_count6: FTCPE port map (Inst_clk_div/base_count(6),Inst_clk_div/base_count_T(6),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(6) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(1) AND Inst_clk_div/base_count(2) AND 
	Inst_clk_div/base_count(3) AND Inst_clk_div/base_count(4) AND 
	Inst_clk_div/base_count(5));

FTCPE_Inst_clk_div/base_count7: FTCPE port map (Inst_clk_div/base_count(7),Inst_clk_div/base_count_T(7),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(7) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(1) AND Inst_clk_div/base_count(2) AND 
	Inst_clk_div/base_count(3) AND Inst_clk_div/base_count(4) AND 
	Inst_clk_div/base_count(5) AND Inst_clk_div/base_count(6));

FTCPE_Inst_clk_div/base_count8: FTCPE port map (Inst_clk_div/base_count(8),Inst_clk_div/base_count_T(8),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(8) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND NOT N_PZ_446);

FTCPE_Inst_clk_div/base_count9: FTCPE port map (Inst_clk_div/base_count(9),Inst_clk_div/base_count_T(9),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(9) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8));

FTCPE_Inst_clk_div/base_count10: FTCPE port map (Inst_clk_div/base_count(10),Inst_clk_div/base_count_T(10),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(10) <= ((Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND N_PZ_446)
	OR (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(9)));

FTCPE_Inst_clk_div/base_count11: FTCPE port map (Inst_clk_div/base_count(11),Inst_clk_div/base_count_T(11),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(11) <= (Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(10) AND Inst_clk_div/base_count(7) AND 
	Inst_clk_div/base_count(1) AND Inst_clk_div/base_count(2) AND 
	Inst_clk_div/base_count(3) AND Inst_clk_div/base_count(4) AND 
	Inst_clk_div/base_count(5) AND Inst_clk_div/base_count(6) AND 
	Inst_clk_div/base_count(8) AND Inst_clk_div/base_count(9));

FTCPE_Inst_clk_div/base_count12: FTCPE port map (Inst_clk_div/base_count(12),Inst_clk_div/base_count_T(12),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(12) <= ((Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND N_PZ_446)
	OR (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(9)));

FTCPE_Inst_clk_div/base_count13: FTCPE port map (Inst_clk_div/base_count(13),Inst_clk_div/base_count_T(13),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(13) <= ((Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND N_PZ_446)
	OR (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND Inst_clk_div/base_count(9)));

FTCPE_Inst_clk_div/base_count14: FTCPE port map (Inst_clk_div/base_count(14),Inst_clk_div/base_count_T(14),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(14) <= (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND Inst_clk_div/base_count(9) AND 
	Inst_clk_div/base_count(13));

FTCPE_Inst_clk_div/base_count15: FTCPE port map (Inst_clk_div/base_count(15),Inst_clk_div/base_count_T(15),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(15) <= (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND Inst_clk_div/base_count(9) AND 
	Inst_clk_div/base_count(13) AND Inst_clk_div/base_count(14));

FTCPE_Inst_clk_div/base_count16: FTCPE port map (Inst_clk_div/base_count(16),Inst_clk_div/base_count_T(16),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(16) <= (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND Inst_clk_div/base_count(9) AND 
	Inst_clk_div/base_count(13) AND Inst_clk_div/base_count(14) AND 
	Inst_clk_div/base_count(15));

FTCPE_Inst_clk_div/base_count17: FTCPE port map (Inst_clk_div/base_count(17),Inst_clk_div/base_count_T(17),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(17) <= (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND Inst_clk_div/base_count(9) AND 
	Inst_clk_div/base_count(13) AND Inst_clk_div/base_count(14) AND 
	Inst_clk_div/base_count(15) AND Inst_clk_div/base_count(16));

FTCPE_Inst_clk_div/base_count18: FTCPE port map (Inst_clk_div/base_count(18),Inst_clk_div/base_count_T(18),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(18) <= ((Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND N_PZ_446)
	OR (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND Inst_clk_div/base_count(9) AND 
	Inst_clk_div/base_count(13) AND Inst_clk_div/base_count(14) AND 
	Inst_clk_div/base_count(15) AND Inst_clk_div/base_count(16) AND 
	Inst_clk_div/base_count(17)));

FTCPE_Inst_clk_div/base_count19: FTCPE port map (Inst_clk_div/base_count(19),Inst_clk_div/base_count_T(19),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/base_count_T(19) <= ((Inst_clk_div/base_count(0) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND N_PZ_446)
	OR (Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(0) AND Inst_clk_div/base_count(10) AND 
	Inst_clk_div/base_count(7) AND Inst_clk_div/base_count(1) AND 
	Inst_clk_div/base_count(2) AND Inst_clk_div/base_count(3) AND 
	Inst_clk_div/base_count(4) AND Inst_clk_div/base_count(5) AND 
	Inst_clk_div/base_count(6) AND Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND Inst_clk_div/base_count(9) AND 
	Inst_clk_div/base_count(13) AND Inst_clk_div/base_count(14) AND 
	Inst_clk_div/base_count(15) AND Inst_clk_div/base_count(16) AND 
	Inst_clk_div/base_count(17) AND Inst_clk_div/base_count(18)));

FTCPE_Inst_clk_div/disp_count0: FTCPE port map (Inst_clk_div/disp_count(0),'0',CLK,NOT BTN<0>,'0','1');

FTCPE_Inst_clk_div/disp_count1: FTCPE port map (Inst_clk_div/disp_count(1),Inst_clk_div/disp_count(0),CLK,NOT BTN<0>,'0','1');

FTCPE_Inst_clk_div/disp_count2: FTCPE port map (Inst_clk_div/disp_count(2),Inst_clk_div/disp_count_T(2),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(2) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1));

FTCPE_Inst_clk_div/disp_count3: FTCPE port map (Inst_clk_div/disp_count(3),Inst_clk_div/disp_count_T(3),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(3) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2));

FTCPE_Inst_clk_div/disp_count4: FTCPE port map (Inst_clk_div/disp_count(4),Inst_clk_div/disp_count_T(4),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(4) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2) AND 
	Inst_clk_div/disp_count(3));

FTCPE_Inst_clk_div/disp_count5: FTCPE port map (Inst_clk_div/disp_count(5),Inst_clk_div/disp_count_T(5),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(5) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2) AND 
	Inst_clk_div/disp_count(3) AND Inst_clk_div/disp_count(4));

FTCPE_Inst_clk_div/disp_count6: FTCPE port map (Inst_clk_div/disp_count(6),Inst_clk_div/disp_count_T(6),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(6) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2) AND 
	Inst_clk_div/disp_count(3) AND Inst_clk_div/disp_count(4) AND 
	Inst_clk_div/disp_count(5));

FTCPE_Inst_clk_div/disp_count7: FTCPE port map (Inst_clk_div/disp_count(7),Inst_clk_div/disp_count_T(7),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(7) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2) AND 
	Inst_clk_div/disp_count(3) AND Inst_clk_div/disp_count(4) AND 
	Inst_clk_div/disp_count(5) AND Inst_clk_div/disp_count(6));

FTCPE_Inst_clk_div/disp_count8: FTCPE port map (Inst_clk_div/disp_count(8),Inst_clk_div/disp_count_T(8),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(8) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2) AND 
	Inst_clk_div/disp_count(3) AND Inst_clk_div/disp_count(4) AND 
	Inst_clk_div/disp_count(5) AND Inst_clk_div/disp_count(6) AND 
	Inst_clk_div/disp_count(7));

FTCPE_Inst_clk_div/disp_count9: FTCPE port map (Inst_clk_div/disp_count(9),Inst_clk_div/disp_count_T(9),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(9) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2) AND 
	Inst_clk_div/disp_count(3) AND Inst_clk_div/disp_count(4) AND 
	Inst_clk_div/disp_count(5) AND Inst_clk_div/disp_count(6) AND 
	Inst_clk_div/disp_count(7) AND Inst_clk_div/disp_count(8));

FTCPE_Inst_clk_div/disp_count10: FTCPE port map (Inst_clk_div/disp_count(10),Inst_clk_div/disp_count_T(10),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(10) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(1) AND Inst_clk_div/disp_count(2) AND 
	Inst_clk_div/disp_count(3) AND Inst_clk_div/disp_count(4) AND 
	Inst_clk_div/disp_count(5) AND Inst_clk_div/disp_count(6) AND 
	Inst_clk_div/disp_count(7) AND Inst_clk_div/disp_count(8) AND 
	Inst_clk_div/disp_count(9));

FTCPE_Inst_clk_div/disp_count11: FTCPE port map (Inst_clk_div/disp_count(11),Inst_clk_div/disp_count_T(11),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(11) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(10) AND Inst_clk_div/disp_count(1) AND 
	Inst_clk_div/disp_count(2) AND Inst_clk_div/disp_count(3) AND 
	Inst_clk_div/disp_count(4) AND Inst_clk_div/disp_count(5) AND 
	Inst_clk_div/disp_count(6) AND Inst_clk_div/disp_count(7) AND 
	Inst_clk_div/disp_count(8) AND Inst_clk_div/disp_count(9));

FTCPE_Inst_clk_div/disp_count12: FTCPE port map (Inst_clk_div/disp_count(12),Inst_clk_div/disp_count_T(12),CLK,NOT BTN<0>,'0','1');
Inst_clk_div/disp_count_T(12) <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(10) AND Inst_clk_div/disp_count(1) AND 
	Inst_clk_div/disp_count(2) AND Inst_clk_div/disp_count(3) AND 
	Inst_clk_div/disp_count(4) AND Inst_clk_div/disp_count(5) AND 
	Inst_clk_div/disp_count(6) AND Inst_clk_div/disp_count(7) AND 
	Inst_clk_div/disp_count(8) AND Inst_clk_div/disp_count(9) AND 
	Inst_clk_div/disp_count(11));


LD(0) <= NOT ((NOT SW(1) AND SW(0)));


LD(1) <= NOT ((SW(1) AND NOT SW(0)));


LD(2) <= NOT ((SW(1) AND SW(0)));

FDCPE_LD3: FDCPE port map (LD(3),LD_D(3),CLK,'0','0','1');
LD_D(3) <= NOT (((NOT BTN(0) AND NOT LD(3))
	OR (BTN(0) AND NOT Inst_clk_div/base_count(17) AND 
	NOT Inst_clk_div/base_count(19))
	OR (BTN(0) AND NOT Inst_clk_div/base_count(18) AND 
	NOT Inst_clk_div/base_count(19))
	OR (BTN(0) AND NOT Inst_clk_div/base_count(11) AND 
	NOT Inst_clk_div/base_count(13) AND NOT Inst_clk_div/base_count(14) AND 
	NOT Inst_clk_div/base_count(15) AND NOT Inst_clk_div/base_count(16) AND 
	NOT Inst_clk_div/base_count(19))
	OR (BTN(0) AND NOT Inst_clk_div/base_count(12) AND 
	NOT Inst_clk_div/base_count(13) AND NOT Inst_clk_div/base_count(14) AND 
	NOT Inst_clk_div/base_count(15) AND NOT Inst_clk_div/base_count(16) AND 
	NOT Inst_clk_div/base_count(19))
	OR (BTN(0) AND NOT Inst_clk_div/base_count(10) AND 
	NOT Inst_clk_div/base_count(9) AND NOT Inst_clk_div/base_count(13) AND 
	NOT Inst_clk_div/base_count(14) AND NOT Inst_clk_div/base_count(15) AND 
	NOT Inst_clk_div/base_count(16) AND NOT Inst_clk_div/base_count(19))
	OR (BTN(0) AND NOT Inst_clk_div/base_count(10) AND 
	NOT Inst_clk_div/base_count(7) AND NOT Inst_clk_div/base_count(8) AND 
	NOT Inst_clk_div/base_count(13) AND NOT Inst_clk_div/base_count(14) AND 
	NOT Inst_clk_div/base_count(15) AND NOT Inst_clk_div/base_count(16) AND 
	NOT Inst_clk_div/base_count(19))));


N_PZ_446 <= (NOT Inst_clk_div/base_count(11) AND 
	Inst_clk_div/base_count(10) AND NOT Inst_clk_div/base_count(8) AND 
	Inst_clk_div/base_count(12) AND NOT Inst_clk_div/base_count(9) AND 
	Inst_clk_div/base_count(13) AND NOT Inst_clk_div/base_count(14) AND 
	NOT Inst_clk_div/base_count(15) AND NOT Inst_clk_div/base_count(16) AND 
	NOT Inst_clk_div/base_count(17) AND Inst_clk_div/base_count(18) AND 
	Inst_clk_div/base_count(19));


N_PZ_466 <= ((Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_THOU(0) AND 
	NOT Inst_Timer_Block/S_THOU(1) AND Inst_Timer_Block/S_THOU(2) AND 
	NOT Inst_Timer_Block/S_THOU(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_ONES(0) AND 
	NOT Inst_Timer_Block/S_ONES(1) AND Inst_Timer_Block/S_ONES(2) AND 
	NOT Inst_Timer_Block/S_ONES(3)));


N_PZ_467 <= ((Inst_Timer_Block/S_2BIT(1) AND 
	NOT Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_HUNS(0) AND 
	NOT Inst_Timer_Block/S_HUNS(1) AND Inst_Timer_Block/S_HUNS(2) AND 
	NOT Inst_Timer_Block/S_HUNS(3))
	OR (NOT Inst_Timer_Block/S_2BIT(1) AND 
	Inst_Timer_Block/S_2BIT(0) AND NOT Inst_Timer_Block/S_TENS(0) AND 
	NOT Inst_Timer_Block/S_TENS(1) AND Inst_Timer_Block/S_TENS(2) AND 
	NOT Inst_Timer_Block/S_TENS(3)));

FTCPE_s_disp: FTCPE port map (s_disp,s_disp_T,CLK,NOT BTN<0>,'0','1');
s_disp_T <= (Inst_clk_div/disp_count(0) AND 
	Inst_clk_div/disp_count(10) AND Inst_clk_div/disp_count(1) AND 
	Inst_clk_div/disp_count(2) AND Inst_clk_div/disp_count(3) AND 
	Inst_clk_div/disp_count(4) AND Inst_clk_div/disp_count(5) AND 
	Inst_clk_div/disp_count(6) AND Inst_clk_div/disp_count(7) AND 
	Inst_clk_div/disp_count(8) AND Inst_clk_div/disp_count(9) AND 
	Inst_clk_div/disp_count(11) AND Inst_clk_div/disp_count(12));


Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FDDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 FTDCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC2C256-7-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCCIO-1.8                     
  2 KPR                              74 KPR                           
  3 KPR                              75 KPR                           
  4 KPR                              76 KPR                           
  5 KPR                              77 KPR                           
  6 KPR                              78 KPR                           
  7 KPR                              79 KPR                           
  8 VCCAUX                           80 KPR                           
  9 KPR                              81 KPR                           
 10 KPR                              82 KPR                           
 11 KPR                              83 KPR                           
 12 KPR                              84 VCC                           
 13 KPR                              85 KPR                           
 14 KPR                              86 KPR                           
 15 KPR                              87 KPR                           
 16 KPR                              88 KPR                           
 17 KPR                              89 GND                           
 18 KPR                              90 GND                           
 19 KPR                              91 KPR                           
 20 KPR                              92 KPR                           
 21 KPR                              93 VCCIO-1.8                     
 22 KPR                              94 BTN<1>                        
 23 KPR                              95 KPR                           
 24 KPR                              96 KPR                           
 25 KPR                              97 KPR                           
 26 KPR                              98 KPR                           
 27 VCCIO-1.8                        99 GND                           
 28 KPR                             100 KPR                           
 29 GND                             101 KPR                           
 30 KPR                             102 KPR                           
 31 KPR                             103 KPR                           
 32 KPR                             104 KPR                           
 33 KPR                             105 KPR                           
 34 KPR                             106 KPR                           
 35 KPR                             107 KPR                           
 36 GND                             108 GND                           
 37 VCC                             109 VCCIO-1.8                     
 38 CLK                             110 KPR                           
 39 SW<0>                           111 KPR                           
 40 KPR                             112 KPR                           
 41 KPR                             113 KPR                           
 42 KPR                             114 KPR                           
 43 KPR                             115 KPR                           
 44 KPR                             116 KPR                           
 45 KPR                             117 KPR                           
 46 KPR                             118 KPR                           
 47 GND                             119 KPR                           
 48 KPR                             120 KPR                           
 49 KPR                             121 KPR                           
 50 KPR                             122 TDO                           
 51 KPR                             123 GND                           
 52 KPR                             124 SW<1>                         
 53 CAT<1>                          125 KPR                           
 54 CAT<5>                          126 ANO<0>                        
 55 VCCIO-1.8                       127 VCCIO-1.8                     
 56 CAT<0>                          128 ANO<1>                        
 57 CAT<4>                          129 ANO<2>                        
 58 CAT<3>                          130 ANO<3>                        
 59 CAT<7>                          131 KPR                           
 60 CAT<2>                          132 KPR                           
 61 CAT<6>                          133 KPR                           
 62 GND                             134 KPR                           
 63 TDI                             135 KPR                           
 64 LD<3>                           136 KPR                           
 65 TMS                             137 KPR                           
 66 LD<2>                           138 KPR                           
 67 TCK                             139 KPR                           
 68 LD<1>                           140 KPR                           
 69 LD<0>                           141 VCCIO-1.8                     
 70 KPR                             142 KPR                           
 71 KPR                             143 BTN<0>                        
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
        PGND  = Unused I/O configured as additional Ground pin
         KPR  = Unused I/O with weak keeper (leave unconnected)
         WPU  = Unused I/O with weak pull up (leave unconnected)
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
      VCCAUX  = Power supply for JTAG pins
   VCCIO-3.3  = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I
   VCCIO-2.5  = I/O supply voltage for LVCMOS25, SSTL2_I
   VCCIO-1.8  = I/O supply voltage for LVCMOS18
   VCCIO-1.5  = I/O supply voltage for LVCMOS15, HSTL_I
        VREF  = Reference voltage for indicated input standard
       *VREF  = Reference voltage pin selected by software
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc2c256-7-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Set Unused I/O Pin Termination              : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Enable Input Registers                      : ON
Function Block Fan-in Limit                 : 38
Use DATA_GATE Attribute                     : ON
Set Tristate Outputs to Termination Mode    : KEEPER
Default Voltage Standard for All Outputs    : LVCMOS18
Input Limit                                 : 32
Pterm Limit                                 : 28