Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedWed Jun 24 16:18:29 2015 product_versionVivado v2015.1 (64-bit)
build_version1215546 os_platformWIN64
registration_id211017451_0_0_353 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a100t
target_packagecsg324 target_speed-3
random_id071473ccaa0852ca9803133c6a2a17f6 project_id8e49ca1c3f794dfcbe570b1ba284a4b9
project_iteration0

user_environment
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
cpu_nameIntel(R) Core(TM) i7-4510U CPU @ 2.00GHz cpu_speed2594 MHz
total_processors1 system_ram17.000 GB

vivado_usage
project_data
srcsetcount=4 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1

unisim_transformation
pre_unisim_transformation
bufg=2 carry4=19 fdce=68 fdre=51
gnd=4 ibuf=2 lut1=68 lut2=82
lut3=7 lut4=3 lut5=25 lut6=17
obuf=5 srl16e=2 vcc=5
post_unisim_transformation
bufg=2 carry4=19 fdce=68 fdre=51
gnd=4 ibuf=3 lut1=68 lut2=82
lut3=7 lut4=3 lut5=25 lut6=17
obuf=5 srl16e=2 vcc=5

placer
usage
lut=105 ff=119 bram36=0 bram18=0
ctrls=7 dsp=0 iob=8 bufg=0
global_clocks=2 pll=0 bufr=0 nets=372
movable_instances=298 pins=1550 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=2.052000

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a100tcsg324-3 package=csg324 speedgrade=-3 version=2015.1
platform=nt64 temp_grade=extended process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=0.000000 pct_inputs_defined=33 user_junc_temp=25.5 (C)
ambient_temp=25.0 (C) user_effective_thetaja=4.6 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=5.7 (C/W)
user_board_temp=25.0 (C) junction_temp=25.5 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=0.105767 dynamic=0.008677
effective_thetaja=4.6 thetasa=4.6 (C/W) thetajb=5.7 (C/W) off-chip_power=0.000000
clocks=0.000900 logic=0.000406 signals=0.000418 i/o=0.006953
devstatic=0.097090 vccint_voltage=1.000000 vccint_total_current=0.016784 vccint_dynamic_current=0.001792
vccint_static_current=0.014992 vccaux_voltage=1.800000 vccaux_total_current=0.018393 vccaux_dynamic_current=0.000252
vccaux_static_current=0.018141 vcco33_voltage=3.300000 vcco33_total_current=0.005949 vcco33_dynamic_current=0.001949
vcco33_static_current=0.004000 vcco25_voltage=2.500000 vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco18_voltage=1.800000 vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco15_voltage=1.500000 vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vccaux_io_voltage=1.800000 vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccbram_voltage=1.000000 vccbram_total_current=0.000245 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000245 mgtavcc_voltage=1.000000 mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000 mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 vccadc_voltage=1.800000 vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 confidence_level_design_state=High confidence_level_clock_activity=Low confidence_level_io_activity=Medium
confidence_level_internal_activity=Medium confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=105 slice_luts_fixed=0 slice_luts_available=63400 slice_luts_util_percentage=0.17
lut_as_logic_used=103 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=0.16
lut_as_memory_used=2 lut_as_memory_fixed=0 lut_as_memory_available=19000 lut_as_memory_util_percentage=0.01
lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=2 lut_as_shift_register_fixed=0
slice_registers_used=119 slice_registers_fixed=0 slice_registers_available=126800 slice_registers_util_percentage=0.09
register_as_flip_flop_used=119 register_as_flip_flop_fixed=0 register_as_flip_flop_available=126800 register_as_flip_flop_util_percentage=0.09
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=126800 register_as_latch_util_percentage=0.00
f7_muxes_used=0 f7_muxes_fixed=0 f7_muxes_available=31700 f7_muxes_util_percentage=0.00
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=15850 f8_muxes_util_percentage=0.00
slice_used=52 slice_fixed=0 slice_available=15850 slice_util_percentage=0.33
slicel_used=29 slicel_fixed=0 slicem_used=23 slicem_fixed=0
lut_as_logic_used=103 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=0.16
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=67 using_o6_output_only_fixed=
using_o5_and_o6_used=36 using_o5_and_o6_fixed= lut_as_memory_used=2 lut_as_memory_fixed=0
lut_as_memory_available=19000 lut_as_memory_util_percentage=0.01 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=2 lut_as_shift_register_fixed=0 using_o5_output_only_used=0 using_o5_output_only_fixed=
using_o6_output_only_used=2 using_o6_output_only_fixed= using_o5_and_o6_used=0 using_o5_and_o6_fixed=
lut_flip_flop_pairs_used=109 lut_flip_flop_pairs_fixed=0 lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_util_percentage=0.17
fully_used_lut_ff_pairs_used=80 fully_used_lut_ff_pairs_fixed= lut_ff_pairs_with_unused_lut_used=4 lut_ff_pairs_with_unused_lut_fixed=
lut_ff_pairs_with_unused_flip_flop_used=25 lut_ff_pairs_with_unused_flip_flop_fixed= unique_control_sets_used=7 minimum_number_of_registers_lost_to_control_set_restriction_used=33(Lost)
memory
block_ram_tile_used=0 block_ram_tile_fixed=0 block_ram_tile_available=135 block_ram_tile_util_percentage=0.00
ramb36_fifo_used=0 ramb36_fifo_fixed=0 ramb36_fifo_available=135 ramb36_fifo_util_percentage=0.00
ramb18_used=0 ramb18_fixed=0 ramb18_available=270 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=240 dsps_util_percentage=0.00
clocking
bufgctrl_used=2 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=6.25
bufio_used=0 bufio_fixed=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_fixed=0 mmcme2_adv_available=6 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=6 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=96 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=24 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
lut2_used=82 lut2_functional_category=LUT fdce_used=68 fdce_functional_category=Flop & Latch
fdre_used=51 fdre_functional_category=Flop & Latch lut5_used=25 lut5_functional_category=LUT
carry4_used=19 carry4_functional_category=CarryLogic lut6_used=17 lut6_functional_category=LUT
lut3_used=7 lut3_functional_category=LUT obuf_used=5 obuf_functional_category=IO
lut1_used=5 lut1_functional_category=LUT lut4_used=3 lut4_functional_category=LUT
ibuf_used=3 ibuf_functional_category=IO srl16e_used=2 srl16e_functional_category=Distributed Memory
bufg_used=2 bufg_functional_category=Clock
io_standard
pci33_3=0 hsul_12=0 lvcmos15=0 sstl135=0
lvttl=0 blvds_25=0 lvcmos33=1 diff_sstl15=0
hstl_i=0 diff_mobile_ddr=0 lvcmos25=0 sstl135_r=0
hstl_ii=0 mobile_ddr=0 lvcmos12=0 lvcmos18=0
hstl_i_18=0 diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0
sstl18_ii=0 sstl15=0 sstl15_r=0 lvds_25=0
diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0
diff_sstl18_i=0 diff_sstl18_ii=0 diff_sstl15_r=0 diff_sstl135=0
diff_sstl135_r=0

router
usage
lut=106 ff=119 bram36=0 bram18=0
ctrls=7 dsp=0 iob=8 bufg=0
global_clocks=2 pll=0 bufr=0 nets=372
movable_instances=298 pins=1550 bogomips=0 high_fanout_nets=0
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=129540 actual_expansions=453465 router_runtime=38.915000

synthesis
command_line_options
-part=xc7a100tcsg324-3 -name=default::[not_specified] -top=wrapper -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=default::10000
-shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:00:26s memory_peak=606.832MB memory_gain=396.379MB hls_ip=0