Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedMon Jun 22 18:45:42 2015 product_versionVivado v2015.1 (64-bit)
build_version1215546 os_platformWIN64
registration_id210714591_0_0_522 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a100t
target_packagecsg324 target_speed-1
random_id3f8c5819cb875163b358f6b98870f011 project_id3bb35a1d167b4f7d8eca9742f60d0ca1
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz cpu_speed2494 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=17 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=2 totalimplruns=2 board=Nexys4 DDR

unisim_transformation
pre_unisim_transformation
bufg=5 bufh=2 carry4=207 fdce=34
fdpe=57 fdre=3787 fdse=103 gnd=77
ibuf=9 idelayctrl=1 idelaye2=16 in_fifo=2
iobufds_intermdisable=2 iobuf_intermdisable=16 iserdese2=16 lut1=620
lut2=574 lut3=901 lut4=965 lut5=901
lut6=1246 mmcme2_adv=2 muxf7=32 obuf=51
obufds=1 obuft=2 oddr=5 oserdese2=42
out_fifo=4 phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1
phy_control=1 plle2_adv=1 ram32m=104 srl16e=17
vcc=69 xadc=1
post_unisim_transformation
bufg=5 bufh=2 carry4=207 fdce=34
fdpe=57 fdre=3787 fdse=103 gnd=77
ibuf=9 ibufds_intermdisable_int=4 ibuf_intermdisable=16 idelayctrl=1
idelaye2=16 inv=3 in_fifo=2 iserdese2=16
lut1=620 lut2=574 lut3=901 lut4=965
lut5=901 lut6=1246 mmcme2_adv=2 muxf7=32
obuf=49 obufds=2 obuft=18 obuftds=4
oddr=5 oserdese2=42 out_fifo=4 phaser_in_phy=2
phaser_out_phy=4 phaser_ref=1 phy_control=1 plle2_adv=1
ramd32=624 rams32=208 srl16e=17 vcc=69
xadc=1

placer
usage
lut=4412 ff=3873 bram36=0 bram18=0
ctrls=190 dsp=0 iob=82 bufg=0
global_clocks=4 pll=1 bufr=0 nets=11301
movable_instances=10161 pins=62354 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=36.887000

ip_statistics
clk_wiz_v5_1/1
iptotal=1 component_name=clk_wiz_0 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=2
clkin1_period=10.0 clkin2_period=10.0 use_power_down=false use_reset=false
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
mig_7series_v2_3/1
iptotal=1 language=Verilog synthesis_tool=Vivado level=CONTROLLER
axi_enable=0 no_of_controllers=1 interface_type=DDR2 axi_enable=0
clk_period=3333 phy_ratio=4 clkin_period=4999 vccaux_io=1.8V
memory_type=COMP memory_part=mt47h64m16hr-25e dq_width=16 ecc=OFF
data_mask=1 ordering=STRICT burst_mode=8 burst_type=SEQ
output_drv=HIGH use_cs_port=1 use_odt_port=1 rtt_nom=50
memory_address_map=BANK_ROW_COLUMN refclk_freq=200 debug_port=OFF internal_vref=1
sysclk_type=NO_BUFFER refclk_type=USE_SYSTEM_CLOCK
xadc_wiz_v3_0/1
iptotal=1 component_name=xadc_wiz_0 enable_axi=false enable_axi4stream=false
dclk_frequency=100 enable_busy=true enable_convst=false enable_convstclk=false
enable_dclk=true enable_drp=true enable_eoc=true enable_eos=true
enable_vbram_alaram=false enable_vccddro_alaram=false enable_vccint_alaram=false enable_vccaux_alaram=false
enable_vccpaux_alaram=false enable_vccpint_alaram=false ot_alaram=false user_temp_alaram=false
timing_mode=continuous channel_averaging=16 sequencer_mode=on startup_channel_selection=contineous_sequence

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a100tcsg324-1 package=csg324 speedgrade=-1 version=2015.1
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=3.000000 pct_inputs_defined=3 user_junc_temp=29.4 (C)
ambient_temp=25.0 (C) user_effective_thetaja=4.6 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=5.7 (C/W)
user_board_temp=25.0 (C) junction_temp=29.4 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=0.972853 dynamic=0.865648
effective_thetaja=4.6 thetasa=4.6 (C/W) thetajb=5.7 (C/W) off-chip_power=0.632684
clocks=1.719688 logic=0.011512 signals=0.014548 mmcm=0.106557
pll=0.000000 i/o=0.607483 phaser=0.102361 xadc=0.001940
devstatic=0.107206 vccint_voltage=1.000000 vccint_total_current=0.087310 vccint_dynamic_current=0.069833
vccint_static_current=0.017477 vccaux_voltage=1.800000 vccaux_total_current=0.174823 vccaux_dynamic_current=0.156467
vccaux_static_current=0.018356 vcco33_voltage=3.300000 vcco33_total_current=0.029985 vcco33_dynamic_current=0.025985
vcco33_static_current=0.004000 vcco25_voltage=2.500000 vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco18_voltage=1.800000 vcco18_total_current=0.592704 vcco18_dynamic_current=0.588704
vcco18_static_current=0.004000 vcco15_voltage=1.500000 vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vccaux_io_voltage=1.800000 vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccbram_voltage=1.000000 vccbram_total_current=0.000289 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000289 mgtavcc_voltage=1.000000 mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000 mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 vccadc_voltage=1.800000 vccadc_total_current=0.020800 vccadc_dynamic_current=0.000800
vccadc_static_current=0.020000 confidence_level_design_state=High confidence_level_clock_activity=High confidence_level_io_activity=Low
confidence_level_internal_activity=Medium confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=4385 slice_luts_fixed=0 slice_luts_available=63400 slice_luts_util_percentage=6.92
lut_as_logic_used=3952 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=6.23
lut_as_memory_used=433 lut_as_memory_fixed=0 lut_as_memory_available=19000 lut_as_memory_util_percentage=2.28
lut_as_distributed_ram_used=416 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=17 lut_as_shift_register_fixed=0
slice_registers_used=3873 slice_registers_fixed=0 slice_registers_available=126800 slice_registers_util_percentage=3.05
register_as_flip_flop_used=3873 register_as_flip_flop_fixed=0 register_as_flip_flop_available=126800 register_as_flip_flop_util_percentage=3.05
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=126800 register_as_latch_util_percentage=0.00
f7_muxes_used=32 f7_muxes_fixed=0 f7_muxes_available=31700 f7_muxes_util_percentage=0.10
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=15850 f8_muxes_util_percentage=0.00
slice_used=1636 slice_fixed=0 slice_available=15850 slice_util_percentage=10.32
slicel_used=1092 slicel_fixed=0 slicem_used=544 slicem_fixed=0
lut_as_logic_used=3952 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=6.23
using_o5_output_only_used=1 using_o5_output_only_fixed= using_o6_output_only_used=3051 using_o6_output_only_fixed=
using_o5_and_o6_used=900 using_o5_and_o6_fixed= lut_as_memory_used=433 lut_as_memory_fixed=0
lut_as_memory_available=19000 lut_as_memory_util_percentage=2.28 lut_as_distributed_ram_used=416 lut_as_distributed_ram_fixed=0
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=0 using_o6_output_only_fixed=
using_o5_and_o6_used=416 using_o5_and_o6_fixed= lut_as_shift_register_used=17 lut_as_shift_register_fixed=0
using_o5_output_only_used=15 using_o5_output_only_fixed= using_o6_output_only_used=2 using_o6_output_only_fixed=
using_o5_and_o6_used=0 using_o5_and_o6_fixed= lut_flip_flop_pairs_used=5219 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_util_percentage=8.23 fully_used_lut_ff_pairs_used=2247 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=850 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=2122 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=190 minimum_number_of_registers_lost_to_control_set_restriction_used=631(Lost)
memory
block_ram_tile_used=0 block_ram_tile_fixed=0 block_ram_tile_available=135 block_ram_tile_util_percentage=0.00
ramb36_fifo_used=0 ramb36_fifo_fixed=0 ramb36_fifo_available=135 ramb36_fifo_util_percentage=0.00
ramb18_used=0 ramb18_fixed=0 ramb18_available=270 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=240 dsps_util_percentage=0.00
clocking
bufgctrl_used=4 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=12.50
bufio_used=0 bufio_fixed=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=2 mmcme2_adv_fixed=1 mmcme2_adv_available=6 mmcme2_adv_util_percentage=33.33
plle2_adv_used=1 plle2_adv_fixed=1 plle2_adv_available=6 plle2_adv_util_percentage=16.67
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=1 bufhce_fixed=0 bufhce_available=96 bufhce_util_percentage=1.04
bufr_used=0 bufr_fixed=0 bufr_available=24 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=1 xadc_fixed=1 xadc_available=1 xadc_util_percentage=100.00
primitives
fdre_used=3711 fdre_functional_category=Flop & Latch lut6_used=1210 lut6_functional_category=LUT
lut4_used=966 lut4_functional_category=LUT lut5_used=892 lut5_functional_category=LUT
lut3_used=886 lut3_functional_category=LUT ramd32_used=624 ramd32_functional_category=Distributed Memory
lut2_used=571 lut2_functional_category=LUT lut1_used=327 lut1_functional_category=LUT
rams32_used=208 rams32_functional_category=Distributed Memory carry4_used=207 carry4_functional_category=CarryLogic
fdse_used=85 fdse_functional_category=Flop & Latch obuf_used=49 obuf_functional_category=IO
fdpe_used=43 fdpe_functional_category=Flop & Latch oserdese2_used=42 oserdese2_functional_category=IO
fdce_used=34 fdce_functional_category=Flop & Latch muxf7_used=32 muxf7_functional_category=MuxFx
obuft_used=18 obuft_functional_category=IO srl16e_used=17 srl16e_functional_category=Distributed Memory
iserdese2_used=16 iserdese2_functional_category=IO idelaye2_used=16 idelaye2_functional_category=IO
ibuf_intermdisable_used=16 ibuf_intermdisable_functional_category=IO ibuf_used=9 ibuf_functional_category=IO
oddr_used=5 oddr_functional_category=IO phaser_out_phy_used=4 phaser_out_phy_functional_category=IO
out_fifo_used=4 out_fifo_functional_category=IO obuftds_used=4 obuftds_functional_category=IO
ibufds_intermdisable_int_used=4 ibufds_intermdisable_int_functional_category=IO bufg_used=4 bufg_functional_category=Clock
inv_used=3 inv_functional_category=LUT phaser_in_phy_used=2 phaser_in_phy_functional_category=IO
obufds_used=2 obufds_functional_category=IO mmcme2_adv_used=2 mmcme2_adv_functional_category=Clock
in_fifo_used=2 in_fifo_functional_category=IO xadc_used=1 xadc_functional_category=Others
plle2_adv_used=1 plle2_adv_functional_category=Clock phy_control_used=1 phy_control_functional_category=IO
phaser_ref_used=1 phaser_ref_functional_category=IO idelayctrl_used=1 idelayctrl_functional_category=IO
bufh_used=1 bufh_functional_category=Clock
io_standard
pci33_3=0 hsul_12=0 lvcmos15=0 sstl135=0
lvttl=0 diff_sstl15_r=0 hstl_ii=0 blvds_25=0
lvcmos33=1 diff_sstl15=0 hstl_i=0 diff_mobile_ddr=0
lvcmos25=0 mobile_ddr=0 lvcmos12=0 lvcmos18=0
hstl_i_18=0 diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0
sstl18_ii=1 sstl15=0 sstl15_r=0 sstl135_r=0
lvds_25=0 diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0
tmds_33=0 diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0
ppds_25=0 diff_sstl18_i=0 diff_sstl18_ii=1 diff_sstl135=0
diff_sstl135_r=0

router
usage
lut=4906 ff=3873 bram36=0 bram18=0
ctrls=190 dsp=0 iob=82 bufg=0
global_clocks=4 pll=1 bufr=0 nets=11301
movable_instances=10161 pins=62354 bogomips=0 high_fanout_nets=6
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=6207516 actual_expansions=125492277 router_runtime=191.365000

synthesis
command_line_options
-part=xc7a100tcsg324-1 -name=default::[not_specified] -top=looper1_1 -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=default::10000
-shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:00:34s memory_peak=658.457MB memory_gain=379.035MB hls_ip=0