ssg_decoder Project Status (08/05/2011 - 17:52:22) | |||
Project File: | ssg_decoder.xise | Parser Errors: | No Errors |
Module Name: | ssg_decoder | Implementation State: | Synthesized |
Target Device: | xc6slx16-3csg324 |
|
No Errors |
Product Version: | ISE 13.2 |
|
191 Warnings (191 new) |
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 266 | 18224 | 1% | |
Number of Slice LUTs | 293 | 9112 | 3% | |
Number of fully used LUT-FF pairs | 204 | 355 | 57% | |
Number of bonded IOBs | 251 | 232 | 108% | |
Number of BUFG/BUFGCTRLs | 1 | 16 | 6% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fri Aug 5 17:52:22 2011 | 0 | 191 Warnings (191 new) | 7 Infos (7 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |