ssg_decoder Project Status (08/05/2011 - 17:52:22)
Project File: ssg_decoder.xise Parser Errors: No Errors
Module Name: ssg_decoder Implementation State: Synthesized
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 13.2
  • Warnings:
191 Warnings (191 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 266 18224 1%
Number of Slice LUTs 293 9112 3%
Number of fully used LUT-FF pairs 204 355 57%
Number of bonded IOBs 251 232 108%
Number of BUFG/BUFGCTRLs 1 16 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Aug 5 17:52:22 20110191 Warnings (191 new)7 Infos (7 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/05/2011 - 17:52:22