Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedFri Jun 12 11:16:10 2015 product_versionVivado v2015.1 (64-bit)
build_version1215546 os_platformWIN64
registration_id210658864_0_0_152 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a200t
target_packagesbg484 target_speed-1
random_id7f284563c2b954dcabf398e932e4e124 project_id4f1072c258ac45c89fabef616c3072a2
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz cpu_speed2494 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=11 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=2 totalimplruns=2

unisim_transformation
pre_unisim_transformation
bufg=1 carry4=66 fdre=403 fdse=4
gnd=13 ibuf=14 lut1=241 lut2=33
lut3=41 lut4=45 lut5=56 lut6=169
muxf7=7 obuf=15 ramb18e1=1 vcc=11
post_unisim_transformation
bufg=1 carry4=66 fdre=403 fdse=4
gnd=13 ibuf=14 lut1=241 lut2=33
lut3=41 lut4=45 lut5=56 lut6=169
muxf7=7 obuf=15 ramb18e1=1 vcc=11

placer
usage
lut=322 ff=403 bram36=0 bram18=1
ctrls=36 dsp=0 iob=29 bufg=0
global_clocks=1 pll=0 bufr=0 nets=1136
movable_instances=894 pins=5415 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=2.726000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=403 srls_augmented=0
srls_newly_gated=0 srls_total=0 bram_ports_augmented=0 bram_ports_newly_gated=0
bram_ports_total=2 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=0
c_enable_32bit_address=0 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=3 c_byte_size=9 c_algorithm=1 c_prim_type=1
c_load_init_file=1 c_init_file_name=[user-defined] c_init_file=charLib.mem c_use_default_data=1
c_default_data=0 c_has_rsta=0 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=0 c_has_regcea=0 c_use_byte_wea=0
c_wea_width=1 c_write_mode_a=WRITE_FIRST c_write_width_a=8 c_read_width_a=8
c_write_depth_a=2048 c_read_depth_a=2048 c_addra_width=11 c_has_rstb=0
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=0
c_has_regceb=0 c_use_byte_web=0 c_web_width=1 c_write_mode_b=WRITE_FIRST
c_write_width_b=8 c_read_width_b=8 c_write_depth_b=2048 c_read_depth_b=2048
c_addrb_width=11 c_has_mem_output_regs_a=1 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=0 c_count_18k_bram=1
c_est_power_summary=Estimated Power for IP _ 1.2196 mW

report_utilization
slice_logic
slice_luts_used=322 slice_luts_fixed=0 slice_luts_available=133800 slice_luts_util_percentage=0.24
lut_as_logic_used=322 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=0.24
lut_as_memory_used=0 lut_as_memory_fixed=0 lut_as_memory_available=46200 lut_as_memory_util_percentage=0.00
slice_registers_used=403 slice_registers_fixed=0 slice_registers_available=267600 slice_registers_util_percentage=0.15
register_as_flip_flop_used=403 register_as_flip_flop_fixed=0 register_as_flip_flop_available=267600 register_as_flip_flop_util_percentage=0.15
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=267600 register_as_latch_util_percentage=0.00
f7_muxes_used=7 f7_muxes_fixed=0 f7_muxes_available=66900 f7_muxes_util_percentage=0.01
f8_muxes_used=0 f8_muxes_fixed=0 f8_muxes_available=33450 f8_muxes_util_percentage=0.00
slice_used=173 slice_fixed=0 slice_available=33450 slice_util_percentage=0.52
slicel_used=113 slicel_fixed=0 slicem_used=60 slicem_fixed=0
lut_as_logic_used=322 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=0.24
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=280 using_o6_output_only_fixed=
using_o5_and_o6_used=42 using_o5_and_o6_fixed= lut_as_memory_used=0 lut_as_memory_fixed=0
lut_as_memory_available=46200 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=0 lut_as_shift_register_fixed=0 lut_flip_flop_pairs_used=551 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=133800 lut_flip_flop_pairs_util_percentage=0.41 fully_used_lut_ff_pairs_used=151 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=229 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=171 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=36 minimum_number_of_registers_lost_to_control_set_restriction_used=93(Lost)
memory
block_ram_tile_used=0.5 block_ram_tile_fixed=0 block_ram_tile_available=365 block_ram_tile_util_percentage=0.14
ramb36_fifo_used=0 ramb36_fifo_fixed=0 ramb36_fifo_available=365 ramb36_fifo_util_percentage=0.00
ramb18_used=1 ramb18_fixed=0 ramb18_available=730 ramb18_util_percentage=0.14
ramb18e1_only_used=1
dsp
dsps_used=0 dsps_fixed=0 dsps_available=740 dsps_util_percentage=0.00
clocking
bufgctrl_used=1 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=3.13
bufio_used=0 bufio_fixed=0 bufio_available=40 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_fixed=0 mmcme2_adv_available=10 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=10 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=20 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=120 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=40 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=399 fdre_functional_category=Flop & Latch lut6_used=133 lut6_functional_category=LUT
lut5_used=78 lut5_functional_category=LUT carry4_used=66 carry4_functional_category=CarryLogic
lut4_used=53 lut4_functional_category=LUT lut3_used=43 lut3_functional_category=LUT
lut2_used=35 lut2_functional_category=LUT lut1_used=22 lut1_functional_category=LUT
obuf_used=15 obuf_functional_category=IO ibuf_used=14 ibuf_functional_category=IO
muxf7_used=7 muxf7_functional_category=MuxFx fdse_used=4 fdse_functional_category=Flop & Latch
ramb18e1_used=1 ramb18e1_functional_category=Block Memory bufg_used=1 bufg_functional_category=Clock
io_standard
lvds_25=0 diff_hstl_i=0 hstl_i=0 lvcmos12=0
ppds_25=0 diff_sstl18_i=0 lvcmos15=0 diff_sstl135=0
lvttl=0 diff_sstl15_r=0 lvcmos33=1 hstl_ii=0
diff_sstl15=0 lvcmos25=1 hsul_12=0 diff_sstl18_ii=0
lvcmos18=0 diff_hsul_12=0 hstl_i_18=0 hstl_ii_18=0
sstl18_i=0 sstl18_ii=0 sstl15=0 sstl15_r=0
sstl135=0 sstl135_r=0 rsds_25=0 diff_hstl_ii=0
tmds_33=0 diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0
diff_sstl135_r=0 pci33_3=0 mobile_ddr=0 diff_mobile_ddr=0
blvds_25=0

router
usage
lut=345 ff=403 bram36=0 bram18=1
ctrls=36 dsp=0 iob=29 bufg=0
global_clocks=1 pll=0 bufr=0 nets=1136
movable_instances=894 pins=5415 bogomips=0 high_fanout_nets=0
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
estimated_expansions=461754 actual_expansions=905370 router_runtime=60.178000

synthesis
command_line_options
-part=xc7a200tsbg484-1 -name=default::[not_specified] -top=GPIO_demo -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=default::10000
-shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:00:28s memory_peak=632.629MB memory_gain=427.820MB hls_ip=0

xsim
command_line_options
-sim_mode=post-synthesis -sim_type=timing