Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


software_version_and_target_device
date_generatedWed Jul 29 14:50:22 2015 product_versionVivado v2015.2 (64-bit)
build_version1266856 os_platformWIN64
registration_id210714591_1777503789_0_454 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a200t
target_packagesbg484 target_speed-1
random_idf4fca05a742c5d23a9e22dc9110e8647 project_id022b67297a304477b0847e0daddb20d2
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz cpu_speed2494 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=18 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=4 totalimplruns=4 board=Nexys Video

unisim_transformation
pre_unisim_transformation
bufg=7 bufh=2 carry4=611 fdce=2
fdpe=69 fdre=9225 fdse=298 gnd=471
ibuf=9 iddr=2 idelayctrl=1 idelaye2=16
in_fifo=2 iobuf=2 iobufds_diff_out_intermdisable=2 iobuf_intermdisable=16
iserdese2=16 lut1=869 lut2=1021 lut3=2284
lut4=2261 lut5=2015 lut6=2411 mmcme2_adv=2
muxf7=57 muxf8=4 obuf=34 obufds=1
obuft=2 oddr=5 oserdese2=43 out_fifo=4
phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1 phy_control=1
plle2_adv=1 ram32m=131 ramb18e1=2 srl16e=21
srlc32e=1 vcc=273 xadc=1
post_unisim_transformation
bufg=7 bufh=2 carry4=611 fdce=2
fdpe=69 fdre=9225 fdse=298 gnd=471
ibuf=11 ibufds_intermdisable_int=4 ibuf_intermdisable=16 iddr=2
idelayctrl=1 idelaye2=16 inv=3 in_fifo=2
iserdese2=16 lut1=869 lut2=1021 lut3=2284
lut4=2261 lut5=2015 lut6=2411 mmcme2_adv=2
muxf7=57 muxf8=4 obuf=34 obufds=2
obuft=20 obuftds=4 oddr=5 oserdese2=43
out_fifo=4 phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1
phy_control=1 plle2_adv=1 ramb18e1=2 ramd32=786
rams32=262 srl16e=21 srlc32e=1 vcc=273
xadc=1

placer
usage
lut=8800 ff=8902 bram36=0 bram18=2
ctrls=353 dsp=0 iob=69 bufg=0
global_clocks=7 pll=1 bufr=0 nets=25622
movable_instances=21681 pins=125660 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=82.834000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=8902 srls_augmented=0
srls_newly_gated=0 srls_total=22 bram_ports_augmented=0 bram_ports_newly_gated=0
bram_ports_total=4 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=0
c_enable_32bit_address=0 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=3 c_byte_size=9 c_algorithm=1 c_prim_type=1
c_load_init_file=1 c_init_file_name=[user-defined] c_init_file=charLib.mem c_use_default_data=0
c_default_data=0 c_has_rsta=0 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=0 c_has_regcea=0 c_use_byte_wea=0
c_wea_width=1 c_write_mode_a=WRITE_FIRST c_write_width_a=8 c_read_width_a=8
c_write_depth_a=2048 c_read_depth_a=2048 c_addra_width=11 c_has_rstb=0
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=0
c_has_regceb=0 c_use_byte_web=0 c_web_width=1 c_write_mode_b=WRITE_FIRST
c_write_width_b=8 c_read_width_b=8 c_write_depth_b=2048 c_read_depth_b=2048
c_addrb_width=11 c_has_mem_output_regs_a=1 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=0 c_count_18k_bram=1
c_est_power_summary=Estimated Power for IP _ 1.2196 mW
clk_wiz_v5_1/1
iptotal=1 component_name=clk_wiz_0 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=4
clkin1_period=10.0 clkin2_period=10.0 use_power_down=false use_reset=false
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
div_gen_v5_1/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=div_gen x_ipversion=5.1 x_ipcorerevision=7 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_xdevicefamily=artix7 c_has_aresetn=0 c_has_aclken=0
c_latency=31 algorithm_type=1 divisor_width=21 dividend_width=29
signed_b=0 divclk_sel=1 fractional_b=0 fractional_width=21
c_has_div_by_zero=0 c_throttle_scheme=3 c_tlast_resolution=0 c_has_s_axis_divisor_tuser=0
c_has_s_axis_divisor_tlast=0 c_s_axis_divisor_tdata_width=24 c_s_axis_divisor_tuser_width=1 c_has_s_axis_dividend_tuser=0
c_has_s_axis_dividend_tlast=0 c_s_axis_dividend_tdata_width=32 c_s_axis_dividend_tuser_width=1 c_m_axis_dout_tdata_width=56
c_m_axis_dout_tuser_width=1
mig_7series_v2_3/1
iptotal=1 language=Verilog synthesis_tool=Vivado level=CONTROLLER
axi_enable=0 no_of_controllers=1 interface_type=DDR3 axi_enable=0
clk_period=2500 phy_ratio=4 clkin_period=5000 vccaux_io=1.8V
memory_type=COMP memory_part=mt41k256m16xx-125 dq_width=16 ecc=OFF
data_mask=1 ordering=NORM burst_mode=8 burst_type=SEQ
ca_mirror=OFF output_drv=LOW use_cs_port=0 use_odt_port=1
rtt_nom=40 memory_address_map=BANK_ROW_COLUMN refclk_freq=200 debug_port=OFF
internal_vref=1 sysclk_type=NO_BUFFER refclk_type=USE_SYSTEM_CLOCK

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a200tsbg484-1 package=sbg484 speedgrade=-1 version=2015.2
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=10.000000 pct_inputs_defined=3 user_junc_temp=27.8 (C)
ambient_temp=25.0 (C) user_effective_thetaja=3.3 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=5.0 (C/W)
user_board_temp=25.0 (C) junction_temp=27.8 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=0.854829 dynamic=0.705250
effective_thetaja=3.3 thetasa=4.6 (C/W) thetajb=5.0 (C/W) off-chip_power=0.543005
clocks=1.065429 logic=0.031552 signals=0.031418 bram=0.001584
mmcm=0.085718 pll=0.090210 i/o=0.293098 phaser=0.116971
xadc=0.003880 devstatic=0.149579 vccint_voltage=1.000000 vccint_total_current=0.183029
vccint_dynamic_current=0.149709 vccint_static_current=0.033319 vccaux_voltage=1.800000 vccaux_total_current=0.230165
vccaux_dynamic_current=0.199367 vccaux_static_current=0.030799 vcco33_voltage=3.300000 vcco33_total_current=0.006101
vcco33_dynamic_current=0.001101 vcco33_static_current=0.005000 vcco25_voltage=2.500000 vcco25_total_current=0.000000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco18_voltage=1.800000 vcco18_total_current=0.000000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco15_voltage=1.500000 vcco15_total_current=0.493702
vcco15_dynamic_current=0.488702 vcco15_static_current=0.005000 vcco135_voltage=1.350000 vcco135_total_current=0.000000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco12_voltage=1.200000 vcco12_total_current=0.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vccaux_io_voltage=1.800000 vccaux_io_total_current=0.000000
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccbram_voltage=1.000000 vccbram_total_current=0.000943
vccbram_dynamic_current=0.000121 vccbram_static_current=0.000822 mgtavcc_voltage=1.000000 mgtavcc_total_current=0.000000
mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000 mgtavtt_total_current=0.000000
mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 vccadc_voltage=1.800000 vccadc_total_current=0.021600
vccadc_dynamic_current=0.001600 vccadc_static_current=0.020000 confidence_level_design_state=High confidence_level_clock_activity=High
confidence_level_io_activity=Low confidence_level_internal_activity=Medium confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=8779 slice_luts_fixed=0 slice_luts_available=133800 slice_luts_util_percentage=6.56
lut_as_logic_used=8253 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=6.17
lut_as_memory_used=526 lut_as_memory_fixed=0 lut_as_memory_available=46200 lut_as_memory_util_percentage=1.14
lut_as_distributed_ram_used=504 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=22 lut_as_shift_register_fixed=0
slice_registers_used=8902 slice_registers_fixed=0 slice_registers_available=267600 slice_registers_util_percentage=3.33
register_as_flip_flop_used=8902 register_as_flip_flop_fixed=0 register_as_flip_flop_available=267600 register_as_flip_flop_util_percentage=3.33
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=267600 register_as_latch_util_percentage=0.00
f7_muxes_used=57 f7_muxes_fixed=0 f7_muxes_available=66900 f7_muxes_util_percentage=0.09
f8_muxes_used=4 f8_muxes_fixed=0 f8_muxes_available=33450 f8_muxes_util_percentage=0.01
slice_used=3409 slice_fixed=0 slice_available=33450 slice_util_percentage=10.19
slicel_used=2246 slicel_fixed=0 slicem_used=1163 slicem_fixed=0
lut_as_logic_used=8253 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=6.17
using_o5_output_only_used=2 using_o5_output_only_fixed= using_o6_output_only_used=6219 using_o6_output_only_fixed=
using_o5_and_o6_used=2032 using_o5_and_o6_fixed= lut_as_memory_used=526 lut_as_memory_fixed=0
lut_as_memory_available=46200 lut_as_memory_util_percentage=1.14 lut_as_distributed_ram_used=504 lut_as_distributed_ram_fixed=0
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=0 using_o6_output_only_fixed=
using_o5_and_o6_used=504 using_o5_and_o6_fixed= lut_as_shift_register_used=22 lut_as_shift_register_fixed=0
using_o5_output_only_used=12 using_o5_output_only_fixed= using_o6_output_only_used=10 using_o6_output_only_fixed=
using_o5_and_o6_used=0 using_o5_and_o6_fixed= lut_flip_flop_pairs_used=10702 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=133800 lut_flip_flop_pairs_util_percentage=8.00 fully_used_lut_ff_pairs_used=4986 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=1937 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=3779 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=353 minimum_number_of_registers_lost_to_control_set_restriction_used=994(Lost)
memory
block_ram_tile_used=1 block_ram_tile_fixed=0 block_ram_tile_available=365 block_ram_tile_util_percentage=0.27
ramb36_fifo_used=0 ramb36_fifo_fixed=0 ramb36_fifo_available=365 ramb36_fifo_util_percentage=0.00
ramb18_used=2 ramb18_fixed=0 ramb18_available=730 ramb18_util_percentage=0.27
ramb18e1_only_used=2
dsp
dsps_used=0 dsps_fixed=0 dsps_available=740 dsps_util_percentage=0.00
clocking
bufgctrl_used=7 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=21.88
bufio_used=0 bufio_fixed=0 bufio_available=40 bufio_util_percentage=0.00
mmcme2_adv_used=2 mmcme2_adv_fixed=1 mmcme2_adv_available=10 mmcme2_adv_util_percentage=20.00
plle2_adv_used=1 plle2_adv_fixed=1 plle2_adv_available=10 plle2_adv_util_percentage=10.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=20 bufmrce_util_percentage=0.00
bufhce_used=1 bufhce_fixed=0 bufhce_available=120 bufhce_util_percentage=0.83
bufr_used=0 bufr_fixed=0 bufr_available=40 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=1 xadc_fixed=0 xadc_available=1 xadc_util_percentage=100.00
primitives
fdre_used=8551 fdre_functional_category=Flop & Latch lut6_used=2360 lut6_functional_category=LUT
lut4_used=2269 lut4_functional_category=LUT lut3_used=2218 lut3_functional_category=LUT
lut5_used=1965 lut5_functional_category=LUT lut2_used=973 lut2_functional_category=LUT
ramd32_used=756 ramd32_functional_category=Distributed Memory carry4_used=605 carry4_functional_category=CarryLogic
lut1_used=500 lut1_functional_category=LUT fdse_used=280 fdse_functional_category=Flop & Latch
rams32_used=252 rams32_functional_category=Distributed Memory fdpe_used=69 fdpe_functional_category=Flop & Latch
muxf7_used=57 muxf7_functional_category=MuxFx oserdese2_used=43 oserdese2_functional_category=IO
obuf_used=34 obuf_functional_category=IO srl16e_used=21 srl16e_functional_category=Distributed Memory
obuft_used=20 obuft_functional_category=IO iserdese2_used=16 iserdese2_functional_category=IO
idelaye2_used=16 idelaye2_functional_category=IO ibuf_intermdisable_used=16 ibuf_intermdisable_functional_category=IO
ibuf_used=11 ibuf_functional_category=IO bufg_used=7 bufg_functional_category=Clock
oddr_used=5 oddr_functional_category=IO phaser_out_phy_used=4 phaser_out_phy_functional_category=IO
out_fifo_used=4 out_fifo_functional_category=IO obuftds_used=4 obuftds_functional_category=IO
muxf8_used=4 muxf8_functional_category=MuxFx ibufds_intermdisable_int_used=4 ibufds_intermdisable_int_functional_category=IO
inv_used=3 inv_functional_category=LUT ramb18e1_used=2 ramb18e1_functional_category=Block Memory
phaser_in_phy_used=2 phaser_in_phy_functional_category=IO obufds_used=2 obufds_functional_category=IO
mmcme2_adv_used=2 mmcme2_adv_functional_category=Clock in_fifo_used=2 in_fifo_functional_category=IO
iddr_used=2 iddr_functional_category=IO fdce_used=2 fdce_functional_category=Flop & Latch
xadc_used=1 xadc_functional_category=Others srlc32e_used=1 srlc32e_functional_category=Distributed Memory
plle2_adv_used=1 plle2_adv_functional_category=Clock phy_control_used=1 phy_control_functional_category=IO
phaser_ref_used=1 phaser_ref_functional_category=IO idelayctrl_used=1 idelayctrl_functional_category=IO
bufh_used=1 bufh_functional_category=Clock
io_standard
lvds_25=0 diff_hstl_i=0 hstl_i=0 ppds_25=0
diff_sstl18_i=0 lvcmos15=1 diff_sstl135=0 lvttl=0
blvds_25=0 hstl_ii=0 hsul_12=0 mini_lvds_25=0
diff_hstl_ii_18=0 lvcmos12=0 diff_sstl15_r=0 lvcmos33=1
diff_sstl15=1 lvcmos25=0 diff_sstl18_ii=0 lvcmos18=0
hstl_i_18=0 diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0
sstl18_ii=0 sstl15=1 sstl15_r=0 sstl135=0
sstl135_r=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 diff_sstl135_r=0 pci33_3=0 mobile_ddr=0
diff_mobile_ddr=0

router
usage
lut=9478 ff=8902 bram36=0 bram18=2
ctrls=353 dsp=0 iob=69 bufg=0
global_clocks=7 pll=1 bufr=0 nets=25622
movable_instances=21681 pins=125660 bogomips=0 high_fanout_nets=7
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=11983368 actual_expansions=41046125 router_runtime=188.734000

synthesis
command_line_options
-part=xc7a200tsbg484-1 -name=default::[not_specified] -top=looper1_1 -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=default::10000
-shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:01:21s memory_peak=731.215MB memory_gain=451.473MB hls_ip=0