Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
date_generatedThu Oct 30 17:33:04 2014 product_versionVivado v2014.2 (64-bit)
build_version932637 os_platformWIN64
registration_id210658864_0_0_152 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a35t
target_packagecpg236 target_speed-1
random_idecbf5bb9f7825bedbf03d828823632b1 project_id5a0a66509cf94eff927e609263b1752c
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz cpu_speed2494 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=0 constraintsetcount=0 designmode=GateLvl prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=[unknown] implstrategy=Vivado Implementation Defaults currentsynthesisrun=[unknown] currentimplrun=impl_1
totalsynthesisruns=0 totalimplruns=1

unisim_transformation
pre_unisim_transformation
bufg=4 carry4=57 fdce=167 fdpe=46
fdre=69 gnd=12 ibuf=22 ldce=72
lut1=102 lut2=44 lut3=113 lut4=121
lut5=83 lut6=179 muxf7=8 muxf8=4
obuf=28 vcc=15
post_unisim_transformation
bufg=4 carry4=57 fdce=167 fdpe=46
fdre=69 gnd=12 ibuf=22 ldce=72
lut1=102 lut2=44 lut3=113 lut4=121
lut5=83 lut6=179 muxf7=8 muxf8=4
obuf=28 vcc=15

placer
usage
lut=464 ff=354 bram36=0 bram18=0
ctrls=132 dsp=0 iob=50 bufg=0
global_clocks=4 pll=0 bufr=0 nets=1239
movable_instances=1049 pins=5929 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=1.849000

report_utilization
slice_logic
slice_luts_used=463 slice_luts_fixed=0 slice_luts_available=20800 slice_luts_util_percentage=2.22
lut_as_logic_used=463 lut_as_logic_fixed=0 lut_as_logic_available=20800 lut_as_logic_util_percentage=2.22
lut_as_memory_used=0 lut_as_memory_fixed=0 lut_as_memory_available=9600 lut_as_memory_util_percentage=0.00
slice_registers_used=354 slice_registers_fixed=0 slice_registers_available=41600 slice_registers_util_percentage=0.85
register_as_flip_flop_used=282 register_as_flip_flop_fixed=0 register_as_flip_flop_available=41600 register_as_flip_flop_util_percentage=0.67
register_as_latch_used=72 register_as_latch_fixed=0 register_as_latch_available=41600 register_as_latch_util_percentage=0.17
f7_muxes_used=8 f7_muxes_fixed=0 f7_muxes_available=16300 f7_muxes_util_percentage=0.04
f8_muxes_used=4 f8_muxes_fixed=0 f8_muxes_available=8150 f8_muxes_util_percentage=0.04
slice_used=268 slice_fixed=0 slice_available=8150 slice_util_percentage=3.28
slicel_used=206 slicel_fixed=0 slicem_used=62 slicem_fixed=0
lut_as_logic_used=463 lut_as_logic_fixed=0 lut_as_logic_available=20800 lut_as_logic_util_percentage=2.22
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=381 using_o6_output_only_fixed=
using_o5_and_o6_used=82 using_o5_and_o6_fixed= lut_as_memory_used=0 lut_as_memory_fixed=0
lut_as_memory_available=9600 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_fixed=0
lut_as_shift_register_used=0 lut_as_shift_register_fixed=0 lut_flip_flop_pairs_used=647 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_util_percentage=3.11 fully_used_lut_ff_pairs_used=161 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=184 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=302 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=132 minimum_number_of_registers_lost_to_control_set_restriction_used=862(Lost)
memory
block_ram_tile_used=0 block_ram_tile_fixed=0 block_ram_tile_available=50 block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0 ramb36_fifo*_fixed=0 ramb36_fifo*_available=50 ramb36_fifo*_util_percentage=0.00
ramb18_used=0 ramb18_fixed=0 ramb18_available=100 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_fixed=0 dsps_available=90 dsps_util_percentage=0.00
clocking
bufgctrl_used=4 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=12.50
bufio_used=0 bufio_fixed=0 bufio_available=20 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_fixed=0 mmcme2_adv_available=5 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=5 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=10 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=72 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=20 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
lut6_used=179 lut6_functional_category=LUT fdce_used=167 fdce_functional_category=Flop & Latch
lut4_used=121 lut4_functional_category=LUT lut3_used=113 lut3_functional_category=LUT
lut5_used=83 lut5_functional_category=LUT ldce_used=72 ldce_functional_category=Flop & Latch
fdre_used=69 fdre_functional_category=Flop & Latch carry4_used=57 carry4_functional_category=CarryLogic
fdpe_used=46 fdpe_functional_category=Flop & Latch lut2_used=44 lut2_functional_category=LUT
obuf_used=28 obuf_functional_category=IO ibuf_used=22 ibuf_functional_category=IO
muxf7_used=8 muxf7_functional_category=MuxFx lut1_used=5 lut1_functional_category=LUT
muxf8_used=4 muxf8_functional_category=MuxFx bufg_used=4 bufg_functional_category=Clock
io_standard
sstl135=0 lvttl=0 lvcmos12=0 blvds_25=0
lvcmos33=1 diff_sstl15=0 hstl_ii=0 diff_mobile_ddr=0
lvcmos25=0 diff_sstl18_ii=0 hstl_i=0 mobile_ddr=0
hsul_12=0 sstl135_r=0 lvcmos15=0 lvcmos18=0
hstl_i_18=0 diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0
sstl18_ii=0 sstl15=0 sstl15_r=0 lvds_25=0
diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0
diff_sstl18_i=0 diff_sstl15_r=0 diff_sstl135=0 diff_sstl135_r=0
pci33_3=0

router
usage
lut=499 ff=354 bram36=0 bram18=0
ctrls=132 dsp=0 iob=50 bufg=0
global_clocks=4 pll=0 bufr=0 nets=1239
movable_instances=1049 pins=5929 bogomips=0 high_fanout_nets=0
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=1048764 actual_expansions=951614 router_runtime=20.995000