BASYSDEMO Project Status
Project File: BasysDemo.ise Current State: Programming File Generated
Module Name: BasysDemo
  • Errors:
No Errors
Target Device: xc3s100e-4vq100
  • Warnings:
17 Warnings
Product Version: ISE, 8.1.03i
  • Updated:
Thu May 25 09:44:21 2006
 
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 59 1,920 3%  
Number used as Flip Flops 58      
Number used as Latches 1      
Number of 4 input LUTs 111 1,920 5%  
Logic Distribution    
Number of occupied Slices 73 960 7%  
Number of Slices containing only related logic 73 73 100%  
Number of Slices containing unrelated logic 0 73 0%  
Total Number 4 input LUTs 135 1,920 7%  
Number used as logic 111      
Number used as a route-thru 23      
Number used as Shift registers 1      
Number of bonded IOBs 61 66 92%  
IOB Flip Flops 1      
IOB Latches 1      
Number of GCLKs 4 24 16%  
Total equivalent gate count for design 1,377      
Additional JTAG gate count for IOBs 2,928      
 
Performance Summary
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu May 25 09:43:33 2006013 Warnings2 Infos
Translation ReportCurrentThu May 25 09:43:39 2006000
Map ReportCurrentThu May 25 09:43:46 200601 Warning2 Infos
Place and Route ReportCurrentThu May 25 09:44:04 200603 Warnings2 Infos
Static Timing ReportCurrentThu May 25 09:44:11 2006002 Infos
Bitgen ReportCurrentThu May 25 09:44:21 2006000