BASYSDEMO Project Status | |||
Project File: | BasysDemo.ise | Current State: | Programming File Generated |
Module Name: | BasysDemo |
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No Errors |
Target Device: | xc3s100e-4vq100 |
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17 Warnings |
Product Version: | ISE, 8.1.03i |
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Thu May 25 09:44:21 2006 |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Total Number Slice Registers | 59 | 1,920 | 3% | |
Number used as Flip Flops | 58 | |||
Number used as Latches | 1 | |||
Number of 4 input LUTs | 111 | 1,920 | 5% | |
Logic Distribution | ||||
Number of occupied Slices | 73 | 960 | 7% | |
Number of Slices containing only related logic | 73 | 73 | 100% | |
Number of Slices containing unrelated logic | 0 | 73 | 0% | |
Total Number 4 input LUTs | 135 | 1,920 | 7% | |
Number used as logic | 111 | |||
Number used as a route-thru | 23 | |||
Number used as Shift registers | 1 | |||
Number of bonded IOBs | 61 | 66 | 92% | |
IOB Flip Flops | 1 | |||
IOB Latches | 1 | |||
Number of GCLKs | 4 | 24 | 16% | |
Total equivalent gate count for design | 1,377 | |||
Additional JTAG gate count for IOBs | 2,928 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Thu May 25 09:43:33 2006 | 0 | 13 Warnings | 2 Infos |
Translation Report | Current | Thu May 25 09:43:39 2006 | 0 | 0 | 0 |
Map Report | Current | Thu May 25 09:43:46 2006 | 0 | 1 Warning | 2 Infos |
Place and Route Report | Current | Thu May 25 09:44:04 2006 | 0 | 3 Warnings | 2 Infos |
Static Timing Report | Current | Thu May 25 09:44:11 2006 | 0 | 0 | 2 Infos |
Bitgen Report | Current | Thu May 25 09:44:21 2006 | 0 | 0 | 0 |